Chapter 1 Introduction of Electronic Packaging

Transcription

1 Chapter 1 Introduction of Electronic Packaging 1

2 Introduction of Electronic Packaging 2

3 Why Need Package? IC Foundry Packaging house Module Sub-system Product 3

4 Concept of Electric Packaging 4

5 Moore s s Law Gordon Moore Minimum feature (transistor) size, but overall size of chip was increasing Moore s Law: Largely as a result of feature size shrinkage, chip power was roughly doubly every 18 months, with a concurrent reduction in cost. Year of Introduction Transistors , , , , ,000 Intel386 processor ,000 Intel486 processor ,180,000 Intel Pentium processor ,100,000 Intel Pentium II processor ,500,000 Intel Pentium III processor ,000,000 Intel Pentium 4 processor ,000,000 Intel Itanium processor ,000,000 Intel Itanium 2 processor ,000,000 5

6 Classification of Electronic Packaging 0-level: interconnection system 1-level (component-level): package for silicon ICs 1.5-level: direct chip on board, intermediate level between the 1- & 2-level package 2-level (board-level): package for PCB as a modulus 3-level (system-level): package for specific functional system 6

7 Purpose of IC Packaging IC-to PCB circuit connection and trace density relaxing Example: IC pad pitch < solder bump pitch < solder ball pitch in flip-chip package Outline dimension standardization Unity of package configuration and interconnection for convenient usage in industry (module) IC chip heat dissipation Heat dissipation channels: conduction (> 85%), convection (10~15%) and radiation (<5%) Thermal conductivity dominates PKG thermal performance IC chip protection Mechanical strength 7

8 Birth of Electronic Packaging Can type package Origin: 1890 s census Herman Hollerith: mechanical tabulating machine derived by electrical motor that introduced the punch card (one of earliest computers) ENIAC: Electronic Numeric Integrator and Calculator, the worldwide 1 st electronic computer (World War II, 1947; vacuum tube-based computer limited operating time due to tube burnout) Vacuum tube: the first generation of electronic package (1900 s ~1950 s) 8

9 IC Package History 9

10 Package Category 10

11 Category of Package Type By material Ceramic Epoxy mounding compound (EMC) By inner interconnection (chip-to-package) Wire bonding (W/B) Control collapsed chip connection (C4), flip-chip bonding (FC) Tab automatic bonding (TAB) By outer interconnection (package-to-pcb) Pin through hole (PTH) Surface mount technology (SMT) By chip carrier material Leadframe Substrate 11

12 General Classification by configuration 2 DIP ZIP SIP PGA S-DIP SOP (Dual in-line Package) (Zigzag in-line Package) (Single in-line Package) (Pin Grid Array) (Shrink DIP) (Small Outline Package) IC 4 TSOP HSOP QFP (Thin Small Outline Package) (SOP with Heat Sink) (Quad Flat Package) TQFP (Thin Quad Flat Package) HQFP (QFP with Heat Sink) BQFP (QFP with Bumper) GQFP (QFP with Guard Ring) 2 SOJ (Small Outline J-leaded Package) J- HSOJ (SOJ with Heat Sink) QFJ (Quad Flat J-leaded Package) 2 SOI (Small Outline I-leaded Package) Joint Electron Device Engineering Council, JEDEC Electronic Industries Association of Japan, EIAJ International Electrotechnical Commission, IEC I- 4 TCP (TAB) HSOI (SOI with Heat Sink) 4 QFI (Quad Flat I-leaded Package) HQFI QFN BGA (QFI with Heat Sink) (Quad Flat Non-leaded Package) (Ball Grid Array) (Tape Carrier Package) (Tape Automatic Bonding) 12

13 Package Family/Outline 13

14 Package Family/Outline 14

15 Package Family/Outline 15

16 Package Family/Outline 16

17 Packaging Efficiency Comparison 17

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19 Package Structure Design 19

20 How to determine a Package structure? PKG pin count number (Rent s rule) I/O number = ( n 1) N n: divergence of CMOS transistor N: total transistor number Applications PKG families (dual, quad, chip scale, BGA, TAB) Packaging dimensions Physical / geometrical constraints Thermal performance Thermal resistance (Theta-jc, Theta-jb & Theta-ja) Mechanical performance Warpage, solder fatigue life Electrical performance Cost Signal and power integrity 20

21 The Circuit Configuration of a CMOS Output Buffer Complementary Metal Oxide Semiconductor CMOS V CC R s pmos Drain-source resistance V R s = I OL d V CC V fi (A) First incident voltage V fi = Z 0 Z + 0 R s V CC V I V O nmos Bump V OH V fi (B) R s 0 1 Switch Time Delay TIME (nsec) GND 21

22 Three Legs of Package Material & structure Computer aid engineering (CAE) Weibull distribution ANSYS, ABQUS, LsDYNA Design for reliability (DFR) IcePAK, Fluent Optimization Reliable package and Reliability testing data analysis (RTDA) Failure mode effective analysis (FMEA) 22

23 Design for Reliability 23

24 Package Reliability Testing Items 22/lot: evaluation qualification (engineering) 77/lot: formal qualification (release to production) 24

25 Process Qualification Items 25

26 Process Qualification Items 26

27 Process Interaction on Failure Mechanisms 27

28 Failure Analysis Procedure 28

29 Bathtub Curve Unit: ppm/khrs Early Failure Rate (EFR) Wear-out Failure Rate (WFR ) Stable Failure Rate (SFR ) 29

30 Market Tendency 30

31 Sale Revenues of IC Industry 31

32 Roadmap of Assembly Market 32

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35 Trend of Package Service in Semiconductor Industry Strategical alliance with front-end foundry houses Ally with foundry houses to be a co-developing relationship Secure the production capacity from allied foundry houses Maintain the leading position of the cutting edge technology Mergence fashion Massive economic of scale Discontinuity of packaging technology Low cost, high quality and worldwide business capability Advanced packaging technology Advanced technology equal to high profit Align with the development of IC technology (Moore s law) Increase the gap distance between the competitors Flip-chip technology becomes the mainstream technology 35

36 Growth and Stimulation of Backend Business 36