Understand the design, features, operation, and application of the Data Transfer Controller (DTC) and DMA Controller (DMAC).

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1 Module Introduction Purpose This training module provides an overview of the peripherals in H8S series microcontrollers that you can use to transfer data without interrupting the CPU. Objective Understand the design, features, operation, and application of the Data Transfer Controller (DTC) and DMA Controller (DMAC). Content 23 pages 4 questions Learning Time 45 minutes 1

2 DTC Basics Uses up to 1KB of on-chip RAM and provides up to 85 channels for data transfer Transfers data between memory and I/Os without interrupting the CPU 2

3 DTC Features Up to 85 channels can be used Transfer is possible over any number of channels. Transfer information is stored in RAM. One activation source can trigger a number of data transfers (Chain Transfer). Multiple transfer modes Normal, Repeat, and Block Transfer modes available Option to select incrementing, decrementing, or fixed source/destination Direct specification of 16MB address space possible Transfer can be set in byte or word units Interrupt or software activation possible Can be halted by setting Module Standby mode 3

4 DTC Implementation 4

5 DTC Registers in On-chip RAM 5

6 DTC Operation Trigger Vector 0 Read Vector CPU Address 0x400 0xec00 Read Register Information CPU Address 0xffec00 DTC Register Information DTC updates register information 0x4ff Transfer Occurs according to register information 0xffefff XFER DONE 6

7 Termination of DTC Transfers CHNE =1? Yes No Count = 0 Or DISEL = 1? Yes No Clear Activation Flag Clear DTCER END Interrupt Exception Handling Termination 7

8 DTC Operating Modes Normal mode One transfer request transfers 1 byte or 1 word. Memory addresses are incremented or decremented by 1 or 2. Up to 65,536 transfers are possible. Repeat mode One transfer request transfers 1 byte or 1 word. Memory addresses are incremented or decremented by 1 or 2. After the specified number of transfers (1 to 256), the initial state resumes and operation continues. Block Transfer mode One transfer request transfers a data block of the specified size. Block size is from 1 to 256 bytes or words. Up to 65,536 transfers are possible. A block area can be designated at either the source or destination. 8

9 Chained Transfer Mode Transfer 0 Register Information (SAR0) (DAR0) (SAR1) Transfer 1 Register Information RAM (DAR1) 9

10 DTC Offloads the CPU DTC-based Transfers CPU Tasks DTC register = HEADER Clean-up interrupt (Header end) DTC register = DATA Clean-up interrupt (DATA end) DTC register = TAIL Clean-up interrupt (TAIL end) Post processing CPU Totals (using DTC) 3 interrupts (context switch) 6 word writes (HEADER, DATA and TAIL register settings) [Number of CPU cycles = 30, minimum: (3 x 6) + (6 x 2) ] CPU-based Transfers CPU Tasks 3 HEADER interrupts 256 DATA interrupts 4 TAIL interrupts Post processing CPU Totals (DTC not used) 263 interrupts (context switch) 263-byte write for data Uncounted writes for stack operations (at least 263x2 for PC, CCR) [Number of CPU cycles = 1578, minimum: 263 x 6 ] 10

13 DMA Controller Basics The DMA Controller Is included in some high-performance H8S MCUs Transfers data from memory to memory and I/O to memory without interrupting CPU Gets the following information from the CPU: Read/Write Starting address of memory block of data Device address Amount of data to be transferred Takes control of the bus (CPU releases the bus) Transfers the data based on information contained in DMA registers Sends interrupt when data transfer is completed Allows three data sizes: 1 byte, 1 word, or 1 block 13

14 DMA Controller Features Choice of Short-Address mode or Full-Address mode Short-Address mode Maximum of 4 channels can be used In Single-Address mode, transfers can be performed in one bus cycle In Dual-Address mode, transfers can be performed in two bus accesses Full-Address mode Maximum of 2 channels can be used 16MB address space can be specified directly Byte or word can be set as the transfer unit Activation sources: internal interrupt, external request, auto-request 16-bit TPU, SCI, A/D, external request, auto request interrupts Module Standby mode can be set to save power 14

15 DMAC Implementation TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 DEND0A DEND0B DEND1A DEND1B Data Buffer Control Logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Channel 0 0A 0B Channel 1 1A 1B Internal Data Bus Address Buffer Internal Data Bus Processor MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Module Bus 15

16 DMAC Register Blocks Channel 0A MRA0A Channel 0 MRA0A IOAR0A MRA0B ETCR0A DMACR0A IOAR0A IOAR0B Channel 0B MRA0B ETCR0A ETCR0B IOAR0B DMACR0A DMACR0B ETCR0B DMACR0B Full-Address mode (Channels A and B operate combined.) Short-Address mode (Channels A and B operate independently.) 16

17 Short-/Single-Address Mode Only a source or destination address is specified. (The other device is external.) A23 to A0 Transfers occur in one bus cycle using DACK pin in place of address specifying I/O 1 to 65,536 transfers Sequential, Idle, and Repeat modes are supported Memory address is incremented or decremented by 1 or 2. Memory address is fixed in Idle mode Activation is via an external source 17

18 Short-Address/Dual-Address Mode One of the addresses is 24 bits wide; the other is 16 bits wide Transfers take two bus accesses: one for read; another for write A23 to A0 Activation sources include external request and internal functions such as 16-bit TPU and A/D A15 to A0 18

19 Features Short-Address/Dual-Address Mode One of the addresses is 24 bits wide; the other is 16 bits wide. Transfers take two bus accesses: one for read; another for write 1 to 65,536 transfers Sequential, Idle, and Repeat modes are supported Memory address is incremented or decremented by 1 or 2 in Sequential and Repeat modes Memory address is fixed in Idle mode. Activation sources include 16-bit TPU, A/D, and external request 19

20 Full-Address Mode Both source and destination addresses are 24 bits wide. Normal and Block Transfer modes A23 to A0 Normal mode transfer activated by auto-request or external request Block mode activated by TPU, SCI, external request or A/D converter A23 to A0 *if internal memory is used for source and destination addresses 20

21 Details Full-Address Mode Both source and destination addresses are 24 bits wide Transfers take two cycles: one for read; another for write 1 to 65,536 transfers Normal and Block Transfer modes are supported Normal mode transfer activated by auto-request or external request - 1-byte or 1-word transfer executed for one transfer request - Choice of burst or cycle-steal transfer, activated by auto request Block mode is activated by TPU, SCI, external request, or A/D converter - Specified block size transfer is executed for one transfer request - Block size: 1 to 256 bytes or words 21

22 DTC vs. DMAC Similarities SAR, DAR, TC Many activation sources A/D, Timers, S/W, etc Interrupt generation Byte or word transfers Control over incrementing or decrementing SAR/DAR Normal, Repeat, and Block Transfer modes Differences DMA is faster, 1 transfer/cycle DMA is all done in H/W DMA channels are limited by H/W DMA is about 7 times faster than DTC DTC many virtual H/W channels DTC channels can be chained DTC uses on-chip RAM DTC is much more flexible 22

25 Module Summary Data Transfer Controller DMA Controller DTC vs. DMAC 25

Hello and welcome to this Renesas Interactive module that provides an overview of the RX DMA Controller

Hello and welcome to this Renesas Interactive module that provides an overview of the RX DMA Controller 1 The purpose of this Renesas Interactive module is to give you a basic understanding of the RX Direct