VLSI-Design of Non-Volatile Memories

Transcription

1 VLSI-Design of Non-Volatile Memories Bearbeitet von Giovanni Campardo, Rino Micheloni, David Novosel 1. Auflage Buch. xxviii, 582 S. Hardcover ISBN Format (B x L): 15,5 x 23,5 cm Gewicht: 2270 g Weitere Fachgebiete > Technik > Elektronik > Halb- und Supraleitertechnologie schnell und portofrei erhältlich bei Die Online-Fachbuchhandlung beck-shop.de ist spezialisiert auf Fachbücher, insbesondere Recht, Steuern und Wirtschaft. Im Sortiment finden Sie alle Medien (Bücher, Zeitschriften, CDs, ebooks, etc.) aller Verlage. Ergänzt wird das Programm durch Services wie Neuerscheinungsdienst oder Zusammenstellungen von Büchern zu Sonderpreisen. Der Shop führt mehr als 8 Millionen Produkte.

2 Contents Foreword: Non-Volatile Memory Technology Evolution...XVII Systems Needs for Non-Volatile Storage...XVIII NOR Flash Memory... XXI NAND Flash Memory...XXIII New Memory Concepts...XXV Conclusions...XXVIII 1 Non-Volatile Memory Design Introduction Main Features of Non-Volatile Memories Program Erase Distributions and Cycles Read Mode Architecture Write Mode Architecture Erase Mode Architecture Elements of Reliability Influence of Temperature and Supply Voltage Lab Activities Working Tools Shmoo Plots Testing Memory Pins Description Bibliography Process Aspects Introduction Main Steps of Fabrication for a CMOS Process Bibliography The MOSFET Transistor and the Memory Cell The MOSFET Transistor Transistors Available The Memory Cell Reading Characteristics Programming Program Algorithm... 57

3 X Contents 3.7 Erase Operation Erasing at Constant Voltage Constant Current Erase Erasing at Negative Gate and Triple-Well Array Erase Algorithm Bibliography Passive Components MOS Capacitors CMOS Technology Capacitors Integrated Resistors Bibliography Fundamental Circuit Blocks Introduction NMOS and CMOS Inverters The Cascode Differential Stage The Source Follower Voltage References NMOS CMOS Self-Biased Generator Band-Gap Reference Current Mirrors NMOS and CMOS Schmitt Trigger Voltage Level Shifter Latch Power On Reset Circuits Analog Switch Bootstrap PUSH-PULL Bootstrap PUSH-PULL Bootstrap with Anti-Glitch PUSH-PULL Bootstrap for a Large Load Oscillators Circuits to Detect Third Level Signals VDD Low Detector Bibliography Layout Custom Layout A Three-Inputs NAND A Three-Inputs NOR An Interdigitized Inverter and a Capacitor Area and Perimeter Parasitic Capacitances Automatic Layout Bibliography

4 Contents XI 7 The Organization of the Memory Array Introduction: EPROM Memories Flash Memory Organization: The Sectors An Array of Sectors Other Types of Array DINOR Arrays (Divided Bit Line NOR) AND Arrays NAND Architecture Bibliography The Input Buffer A Discussion on Input and Output Levels Input Buffers Examples of Input Buffers Automatic Stand-By Mode Bibliography Decoders Introduction Word Line Capacitance and Resistance Row Decoders NMOS Row Decoder CMOS Row Decoders A Dynamic CMOS Row Decoding A Semistatic CMOS Row Decoder Row Decoders for Low Supply Voltage Row Pre-Decoder at High Voltage Sector Decoding Memory Space for Test: the OTP Rows Hierarchical Row Decoding Read & Program Erase Low Switching ConsumptionRow Decoder Column Decoders Bibliography Boost Introduction Boost Techniques One-Shot Local Boost Double-BoostRow Decoder The Issue of the Recharge ofc BOOST Double-Path Boost Circuitry Boosted Voltages Switch Leakage Recovery Circuits Bibliography

5 XII Contents 11 Synchronization Circuits ATD Multiple ATD Management Let s Connect the ATD to the Boost Circuitry Equalization of the Sense Amplifier: SAEQ Word Line Overvoltage: One Shot Boost Word Line Overvoltage: Charge Pump The ENDREAD Signal The Cells Used by the Dummy Sense Amplifiers ATD ENDREAD Overlap Sequential Reads Asynchronous Page Mode The Synchronous Burst Mode Bibliography Reading Circuits The Inverter Approach Differential Read with Unbalanced Load Differential Reading with Current Offset Semi-Parallel Reference Current Techniques to Speed Up Read Equalization Precharge Clamping of the MAT and REF Nodes Differential Read with Current Mirror The Flash Cell Reading at Low VDD Amplified I/V Converter Amplified Semi-Parallel Reference Sizing of the Main Mirror Dynamic Analysis of the Sense Amplifier Precharge of the Output Stage of the Comparator Issues of the Reference EPROM-Like Reference Mini-Matrix Mirrored Reference Current The Verify Operation Erase Program Bibliography Multilevel Read Multilevel Storage Current Sensing Method Multilevel Programming Current/Voltage Reference Network Voltage Sensing Method

6 Contents XIII 13.6 Sample & Hold Sense Amplifier Closed-Loop Voltage Sensing Hierarchical Row Decoding for Multiple Sensing Loops A/D Conversion Low Power Comparator Bibliography Program and Erase Algorithms Memory Architecture from the Program-Erase Functionality Point of View User Command to Program and Erase Program Algorithm for Bi-Level Memories Program Algorithm for Multilevel Memories Erase Algorithm Test Algorithms Bibliography Circuits Used in Program and Erase Operations Introduction Dual Voltage Devices Charge Pumps Different Types of Charge Pumps Dickson Pump Based on Bipolar Diodes Dickson Pump Based on Transistor-Based Diodes Charge Pump Based on Pass Transistors Voltage Doubler Voltage Tripler High Voltage Limiter Charge Pumps for Negative Voltages Voltage Regulation Principles Gate Voltage Regulation Circuit Structure Frequency Compensation Positive Power Supply Rejection Ratio (PSRR) Program Gate Voltage Drain Voltage Regulation and Temperature Dependence Bibliography High-Voltage ManagementSystem Introduction Sectors Biasing Local Sector Switch Stand-By Management High-Voltage Management Architecture Overview High-Voltage Read Path High-Voltage Program Path

7 XIV Contents High-Voltage Erase Path Modulation Effects Program Drain Voltage Modulation Body Voltage Modulation Source Voltage Modulation Bibliography Program and Erase Controller FSM Controller STD Cell Implementation of the FSM PLA Implementation of the FSM Microcontroller Bibliography Redundancy and Error Correction Codes Redundancy Redundancy & Read Path Yield UPROM Cells Read Circuitry for the UPROM Cells Supply Circuitry for the UPROM Cells The First Read After Power On Reset Error Correction Codes Elements of Coding Theory A Memory with ECC Bibliography The Output Buffer Introduction NMOS Output Buffer A CMOS Super Output Buffer The High Voltage Tolerance Issue Noise Induced on the Signal Circuitry by Commutation of the Output Buffers Bibliography Test Modes Introduction An Overview on Test Modes DMA Test Fast DMA Oxide Integrity Test Bibliography ESD & Latch-Up Notes on Bipolar Transistors Latch-Up

8 Contents XV 21.3 Bipolar Transistors Used in Flash Memories Distribution of Power Supplies and ESD Protection Network Bibliography From Specification Analysis to Floorplan Definition Introduction Matrix Organization Matrix Row Dimensioning Dimensioning the Sectors Memory Configurations Organization of Column Decoding Redundancy First Considerations on Read Mode Architecture of the Reference Read Problems for a Non-Static Memory Erase and Program Circuits Pad Placement Control Logic and Related Circuitry Bibliography Photoalbum Introduction Figures Index The Photos Subject Index