Mosel Vitelic (IBM-Siemens) V53C181608K60 1Mx16 CMOS EDO DRAM

Transcription

1 May 19, 1998 Mosel Vitelic (IBM-Siemens) V53C181608K60 1Mx16 CMOS EDO DRAM Abstract: The Mosel Vitelic V53C181608K60 is a 1Mx16 CMOS DRAM featuring EDO Page Mode Operation, self-refresh, hidden refresh and a 1K-cycle refresh with 16Kb page size. The die markings indicate that the part was designed by an IBM-Siemens design team. The device is manufactured in a double-metal, approximately 0.5µm CMOS technology. This report contains the device description, die photograph, die markings, package photograph and X-rays and full-chip schematics. For questions, comments or more information about this report, or for any additional technical needs concerning semiconductor technology, please call a Sales Representative at Chipworks. Telephone (613) Facsimile (613)

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3 Mosel Vitelic V53C181608K60 1Mx16 CMOS DRAM Page 1 Contents: List Of Figures...2 Introduction...6 Access Devices and Cells...6 Die Architecture...8 Data Bus Architecture...8 Reference Cells...9 Memory Configuration...10 Address Pin Configurations...10 Write-Per-Bit...11 Self-Refresh...12 Test Modes...13 Burn-In...13 Multi-Bit Test...13 ID ROM...14 Cell Stress Test...14 Multiple Row Access...14 X- Boost...15 Comments:...15 Signal Naming Conventions...16 Signal Cross-Reference Conventions...16 Top Level Block Diagram... Tab 1 Data Path... Tab 2 Address Path... Tab 3 Clocks... Tab 4 Voltage Generators and Power-Up... Tab 5 Row Redundancy Programming... Tab 6 Column Redundancy Programming... Tab 7 Test Control Logic... Tab 8 Mode Signal Generators... Tab 9 ID Readout Circuitry... Tab 10 Signal Cross-Reference... Tab 11 Appendix A: Comparison with IBM PT3D and Siemens HYB BSJ Tab 12

4 Mosel Vitelic V53C181608K60 1Mx16 CMOS DRAM Page 2 List Of Figures Package Markings Package X-Ray Photograph Pin Configuration Die Markings Annotated Die Photograph Bonding Pad Configuration Data Bus Architecture - Array Half Data Bus Architecture - Center Strip Symbol Conventions Symbol Definitions Symbol Definitions Symbol Definitions Symbol Definitions Transistor Size Notation Chip Block Diagram Data Path Main Memory (2 Sectors) Cells and Sense Amplifiers YC Access Devices YB Access Devices YA Access Devices DB Sense Amp and DB Precharge Write Drivers Data Valid Generator Data Line MUX (x modes) Data Line MUX (x1 mode) DATAIN Generator (x modes) DATAIN Generator (x1 Mode) DL7 to DL10 Buffer DATA/DL MUX (x16 mode) DATA/DL MUX (x8 Mode) DATA/DL MUX (x4/x8 Modes) to-1 MUX (1-bit slice) DATA/DL MUX (x1 Mode) Per-Bit Write Enable Generator DATAEN Generator I/O Buffers I/O Buffer Control Circuitry I/O Output Driver I/O Input Buffer Multi-Bit Test Circuitry Multi-Bit Test (x1, x4 Write) Multi-Bit Test (x8) Multi-Bit Test (x4) Multi-Bit Test (x1 Read) Data Valid Combiner

5 Mosel Vitelic V53C181608K60 1Mx16 CMOS DRAM Page Address Path Address Buffer A [7:0] Address Buffer A8 Address Buffer A9 Address Buffer A10 Address Buffer A11 Address Buffer Address Input Buffer Address Drivers AL10 Address Driver Address Drivers AB [7:2] Address Switch Row Address Path Row Address Register Row Predecoders Row Access Row Decoder Redundant Row Register Redundant Row Decoder Dummy Row Encoder Dummy Row Decoder X - Generator SN_ Pull-Down SN_ Pull-Up Row Clock Repeaters Column Decoders YA Generator YB Generator YC Generator Databus Precharge Generator Redundant Column Decoder Redundant Col. Test Addr. Generator Refresh Counter Bit Decoder Bit Factor AP Bit Factor AP Bit Factor AP Bit Factors AP[4:3] A9C Address Driver Block Decoder Block Active Detector Clocks Row Clocks RAS Buffer [RAS_] Input Buffer Alternate [RAS_] Input Buffer RAS Clocks RAS3_ Generator RAS4, RAS5_, RAS6_ Generator RAS Lock Row Lock Fuse Options Self-Refresh Timer

6 Mosel Vitelic V53C181608K60 1Mx16 CMOS DRAM Page Self-Refresh Oscillator Self-Refresh Clock Generator Self-Refresh Counter Self-Refresh Counter Cell Self-Refresh Timer Decoder Counter Fuse Options Counter Fuse Options Column Clocks [UCAS_] Buffer [LCAS_] Buffer Spare [CAS_] Buffer Spare [CAS_] Buffer ATD Combiner Address Transition Detectors Transition Detector Self-Refresh Timer Enable CBR_ and WCBR_ Detector Hidden Refresh Detector CBR3_ and AYS Generator I/O Clocks WE_ Buffer [OE_] Buffer WRITE_ Generator [OE_] Buffer Fuse Option WMASKLD_ Generator READY Generators Voltage Generators and Power-Up Power-Up Circuitry VCC Regulator Voltage Reference THRADJ Generator Internal VCC Regulator VPP Generator Ring Oscillator Non-Overlapping Pulses Generator VPP Clock Level Shifter VPP Pump Voltage Comparator Progammable Voltage Generator Row Redundancy Programming Row Redundancy Programming Redundant Row Fuses (Bits 5-0) Redundant Row Fuses (Bits 9-6) bit Redundancy Register Row Redundancy Enable Row Redundancy Enable Fuse Row Redundancy Test Column Redundancy Faulty Column Addr. Comparator

7 Mosel Vitelic V53C181608K60 1Mx16 CMOS DRAM Page Test Control Logic Test Address Register Test Address Register Test Mode Decoder Test Mode Decoder Test Mode Fuses TMR1_ Generator WCBR Generator Mode Signal Generators Mode Signal Generator Bond Options Bond Options ID Readout Circuitry ID Shift Register Clock Generator Bit ID Shift Register Shift Register Element ID Register Readout Enable A Comparison with IBM and Siemens Parts A.1 Die Marking Comparison A.2 Die Marking Comparison - 2 A.3 Mosel Vitelic V53C181608K60 Die Markings A.4 Siemens HYB BSJ-60 (D2) Die Markings A.5 Siemens HYB BSJ-60 (C3) Die Markings A.6 IBM PT3D Die Markings A.7 Siemens HYB BSJ-60 (D2) Package X-Ray A.8 Siemens HYB BSJ-60 (D2) Die Photograph A.9 Siemens HYB BSJ-60 (C3) Package X-Ray A.10 Siemens HYB BSJ-60 (C3) Die Photograph A.11 IBM PT3D Package X-Ray A.12 IBM PT3D Die Photograph