Compiling for deeply embedded and heterogeneous signal processing systems

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1 Compiling for deeply embedded and heterogeneous signal processing systems Jeronimo Castrillon Cfaed Chair for Compiler Construction (CCC) 5G Summit, Dresden, Germany September 29, 2016

Multi-Processor/core Systems on Chip HW complexity Increasing number of cores Increasing heterogeneity Number of PEs 16 14 12 10 8 6 4 2 OMAP1 OMAP Family Snapdragon Family OMAP2 PE Count in SoCs

2 Multi-Processor/core Systems on Chip HW complexity Increasing number of cores Increasing heterogeneity Number of PEs OMAP1 OMAP Family Snapdragon Family OMAP2 PE Count in SoCs OMAP4470 OMAP4430 OMAP3640 OMAP3530 S3 MSM8060 S1 QSD8650 S2 MSM8255 OMAP5430 S4 APQ8064 S4 MSM8960 Heterogeneity and size Year [Castrill14] MEM subsystem DMAs, semaphores PMU TI Keystone II L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Ephiphany IV Source: 2

3 Multi-Processor/core Systems on Chip SW productivity gap How to program these systems? Meet performance/energy reuirements Massive MIMO 5G High-perf. Codes Complex Beamform. Fragmented tools, different runtimes/os on ARM and DSP, 500+ pages on APIs Homogeneous! OpenMP support uses 1/3 of program memory! MEM subsystem DMAs, semaphores PMU TI Keystone II L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Ephiphany IV Source: 3

4 Multi-Processor/core Systems on Chip SW productivity gap How to program these systems? Meet performance/energy reuirements Massive MIMO 5G High-perf. Codes Complex Beamform. Fragmented tools, different runtimes/os on ARM and DSP, 500+ pages on APIs Homogeneous! OpenMP support uses 1/3 of program memory! 4 MEM subsystem DMAs, semaphores PMU TI Keystone II L2 VLIW DSP Communication support HW ueues,l2 Network Processor NoC Need for software Packet DMA automation tools Peripherals Ephiphany IV Source:

Programming flow MEM subsystem DMAs, semaphores PMU Dataflow application Architecture model L2 VLIW DSP,L2 NoC Peripherals Non-functional specification Communication support HW ueues Network

PNchann el_f re_ coef = fi PNargs_ifft_r.PNnum_f re_ coef = 0U; PNargs_ifft_r.PNchann el_t ime_ coef = si PNargs_ifft_r.

5 Programming flow MEM subsystem DMAs, semaphores PMU Dataflow application Architecture model L2 VLIW DSP,L2 NoC Peripherals Non-functional specification Communication support HW ueues Network Processor Packet DMA Analysis Synthesis Code generation [Castrill14] Property models (timing, energy, error, ) taskparams.arg0 = (xdc_uarg)&pnargs_src PNargs_ifft_r.ID = 6U; PNargs_ifft_r.PNchann el_f re_ coef = fi PNargs_ifft_r.PNnum_f re_ coef = 0U; PNargs_ifft_r.PNchann el_t ime_ coef = si PNargs_ifft_r.channel = 1; sink_left = IPCllmrf_open(3, 1, 1); sink_right = IPCllmrf_open(7, 1, 1); PNargs_sink.ID = 7U; PNargs_sink.PNchannel _in_ left = sink_l PNargs_sink.PNnum_in_ left = 0U; PNargs_sink.PNchannel _in_ righ t = sink_ PNargs_sink.PNnum_in_ righ t = 0U; taskparams.priority = 1; ti_sysbios_knl_task_c reat e((ti_sysbios_knl_ &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_fft taskparams.priority = 1; ti_sysbios_knl_task_c reat e((ti_sysbios_knl_ ft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_iff taskparams.priority = 1; ti_sysbios_knl_task_c reat e((ti_sysbios_knl_ fft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_sin taskparams.priority = 1; 5

6 Dataflow programming models Graph representation of applications Implicit repetitive execution of tasks Good model for streaming applications Good match for signal processing & multi-media applications Large body of research on multiple flavors of these models Properties: No race conditions, determinism, strong/weak guarantees Static Dynamic 6

$Language: C for process networks FIFO Channels Processes & networks typedef struct { int i; double d; } my_struct_t; PNchannel my_struct_t S; PNchannel int A = {1, 2, 3}; /* Initialization */$

7 Language: C for process networks FIFO Channels Processes & networks typedef struct { int i; double d; } my_struct_t; PNchannel my_struct_t S; PNchannel int A = {1, 2, 3}; /* Initialization */ PNchannel short C[2], D[2], F[2], G[2]; PNkpn AudioAmp PNin(short A[2]) PNout(short B[2]) PNparam(short boost){ while (1) PNin(A) PNout(B) { for (int i = 0; i < 2; i++) B[i] = A[i]*boost; }} PNprocess Amp1 = AudioAmp PNin(C) PNout(F) PNparam(3); PNprocess Amp2 = AudioAmp PNin(D) PNout(G) PNparam(10); 7 [Sheng14]

8 Architecture model and constraints System model including: Topology, interconnect, memories Computation: uarch model Communication: cost functions MCA standardizing it to SHIM 2.0 [Oden13] Constraints Time constraints Mapping constraints 1 ms 3 ms 1 ms Platform constraints 8

Analysis and synthesis: Overview CPN application Analysis: Instrumentation, profiling, tracing Seuential performance estimation Time-annotated traces

9 Analysis and synthesis: Overview CPN application Analysis: Instrumentation, profiling, tracing Seuential performance estimation Time-annotated traces Architecture model Mapping and scheduling Parallel perf. estimation Mapping configuration Non-functional specification Increase resources [Castrill13] 9

Example 1) From LabVIEW to Tomahawk Platform Baseband processing application (data dependent execution paths) Visit demo booth Automatic code generation Duo-PE3 VDSP RISC Duo-PE2 VDSP RISC FPGA-

10 Example 1) From LabVIEW to Tomahawk Platform Baseband processing application (data dependent execution paths) Visit demo booth Automatic code generation Duo-PE3 VDSP RISC Duo-PE2 VDSP RISC FPGA- Interface ADPLL AVS Contr. Router (1,0) hs-serial Router (0,0) Duo-PE0 VDSP RISC Duo-PE1 VDSP RISC FEC SD Tomahawk2_core hs-serial hs-serial CM APP Duo-PE7 VDSP RISC Duo-PE6 VDSP RISC hs-serial Router (1,1) hs-serial Router (0,1) UART- GPIO parallel Duo-PE4 VDSP RISC Duo-PE5 VDSP RISC ADPLL DDR- SDRAM- Interface Tomahawk Chip (accelerators for baseband processing) [Arnold13] 10

11 Example 2) LTE application mapping Cortessy: Silexica Software Solutions GmbH 11

12 Example 2) LTE application execution Schedule Cortessy: Silexica Software Solutions GmbH 12

13 Example 2) LTE application: Results Peak Power (W) 8,62 2,79 1,71 2,08 Execution Time (ms) ,5 327,8 348,2 3 2,5 2 1,5 1 0, ,5 1 0,5 0 Average Power (W) 2,62 1,99 1,55 1,64 Power Efficiency (1/(W*second)) 1,443 Reference (LoadBalancer) 1,164 Constraint = 2s 0,631 Constraint = 1s 0,334 Constraint = 0.35s Cortessy: Silexica Software Solutions GmbH 13

GmbH National Instruments German Cluster of

14 Acknowledgements Vodafone Chair for Mobile Communications Systems Silexica Software Solutions GmbH National Instruments German Cluster of Excellence: Center for Advancing Electronics Dresden ( 14

15 Thanks! Questions?

16 References [Castrill14] J. Castrillon and R. Leupers, Programming Heterogeneous MPSoCs: Tool Flows to Close the Software Productivity Gap. Springer, 2014 [Sheng14] W. Sheng, S. Schürmans, M. Odendahl, M. Bertsch, V. Volevach, R. Leupers, and G. Ascheid, A compiler infrastructure for embedded heterogeneous MPSoCs, Parallel Comput. 40, 2 (February 2014), [Oden13] M. Odendahl, et al., Split-cost communication model for improved MPSoC application mapping, In International Symposium on System on Chip pp. 1-8, 2013 [Castrill13] J. Castrillon, R. Leupers, and G. Ascheid, MAPS: Mapping concurrent dataflow applications to heterogeneous MPSoCs, IEEE Transactions on Industrial Informatics, vol. 9, no. 1, pp , 2013 [Arnold13] O. Arnold, et al. Tomahawk - Parallelism and Heterogeneity in Communications Signal Processing MPSoCs. TECS,

Programming Heterogeneous Embedded Systems for IoT

Programming Heterogeneous Embedded Systems for IoT Jeronimo Castrillon Chair for Compiler Construction TU Dresden jeronimo.castrillon@tu-dresden.de Get-together toward a sustainable collaboration in IoT