An Efficient Low Area Implementation of 2-D DCT on FPGA

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1 An Efficient Lw Area Implementatin f 2-D DCT n FPGA Atakan Dğan Anadlu University, Electrical and Electrnics Engineering, Eskişehir, Turkey atdgan@anadlu.edu.tr Abstract This paper presents the design and implementatin fr 2-D discrete csine transfrm (DCT) with the gal f achieving lw area utilizatin and high-speed peratin n FPGAs. The design is based n the rw-clumn decmpsitin technique, which requires tw successive 1-D DCT transfrms and a transpse memry between them fr string and transpsing the results f the first 1-D DCT. The prpsed implementatin f 2-D DCT is capable f cmpressing at least 70 images per secnd in 720x480 reslutin n Xilinx Spartan 3E and 30 images per secnd in 1920x80 reslutin n Xilinx Virtex 7 FPGA. Cnsequently, the prpsed 2-D DCT design and implementatin can be very useful in varius image and vide cmpressing applicatins. 1. Intrductin The discrete csine transfrm (DCT) plays a key rle in JPEG fr still picture cmpressin [1], ITU H.261 [2] fr telecnferencing, and MPEG fr multimedia applicatins [3]. Fr example, in JPEG baseline encder, an input image is split int nn-verlapping blcks f 8 8 pixels, the pixel values are level shifted frm unsigned integer t signed integer, and then 2- D DCT cmputatin is perfrmed n each blck. Amng the varius architectures and algrithms prpsed fr the cmputatin f 2-D DCT, a ppular apprach is the rwclumn decmpsitin methd [4-]. Its ppularity can be attributed t the fllwing facts: (i) It is based n the separability prperty f 2-D DCT and enables the cmputatin f 2-D DCT by using tw successive 1-D DCT transfrms. (ii) It requires a cntrl lgic with lwer cmplexity due t its regularity and mdularity. (iii) It reduces the cmputatinal cmplexity f 2-D DCT by a factr f fur. Fr an 8x8 input matrix, 2-D DCT algrithm requires 4096 multiplicatin and 4096 additin peratins. The rw-clumn decmpsitin methd, n the ther hand, nly needs 24 multiplicatin and 24 additin peratins. In this study, the 2-D DCT architecture intrduced by [4] fr an ASIC implementatin is adpted, and is mdified fr a lw area implementatin n FPGA. There are f curse several reasns why [4] is chsen t be implemented n FPGA: (i) It explits the rw-clumn decmpsitin. Thus, using single 1-D DCT cre in a time-shared manner is expected t result in lw area utilizatin. (ii) It uses a shift-register based transpse buffer that saves blck RAM resurces. (iii) The cntrl lgic can be distributed amng its cmpnents, which results in simpler finite state machines. The rest f the paper is rganized as fllws. Sectin 2 presents details f the prpsed 2-D DCT architecture. Sectin 3 gives the implementatin results and cmpares against ther cres frm the literature. Finally, Sectin 4 cncludes the paper D DCTArchitecture The verview f the prpsed FPGA implementatin f 2-D DCT architecture is shwn Fig. 1, which is inspired by [4]. With respect t Fig. 1, the main cmpnents include ping buffer, png buffer, 1-D DCT, transpse buffer, and utput buffer. It shuld be nted here that the mdificatins t [4] include png buffer peratin, inclusin f a pipeline register and runding lgic in 1-D DCT, utput buffer, and a stppable pipeline. Cmmn t these cmpnents are their input and utput interfaces, which are similar t writing int r reading frm a FIFO buffer and described as fllws: - Input interface: A cmpnent cnsumes a new data wrd n writedata bus in the next rising edge f clck signal if writeen is asserted while full is nt asserted during the current clck perid. Thus, the asserted full signal indicates that the cmpnent cannt currently accept a new data wrd. writedata, input, 8-, -, r 96-bit writeen, input, 1-bit full, utput, 1-bit - Output interface: A cmpnent prduces a new data wrd n readdata bus in the next rising edge f clck signal if readen is asserted while empty is nt asserted during the current clck perid. Nte that if empty is nt asserted, there is a valid data wrd available n readdata bus; therwise, cmpnent cannt prvide a new data wrd in the current clck cycle. readdata, utput, -, r 96-bit readen, input, 1-bit empty, utput, 1-bit As a result f their afrementined input and utput interfaces, fur main cmpnents are seamlessly cnnected in Fig. 1 as fllws: - readdata (Output) writedata (Input): Data bus between prducer and cnsumer cmpnents is established. - empty (Output) inverter writeen (Input): Prducer cmpnent can write int cnsumer cmpnent. - readen (Input) inverter full (Output): Cnsumer cmpnent can read frm prducer cmpnent. After the detailed descriptin f input and utput interfaces, hw each f five cmpnents cntributes t the cmputatin f 2-D DCT will be explained in the fllwing sectins Ping Buffer Ping buffer is basically a 96-bit shift-register whse peratin is cntrlled by a tw-state {empty, full} finite state machine (FSM) as fllws: - empty (serial-in): If writeen is asserted, a new -bit wrd is serially shifted int ping buffer. Once the eighth

2 Ping Buffe r 96 Mux Png Buffe 1-D DC T Transpse Buffer 96 MuxSel Reset Clck Output Buffer Fig. 1. Architecture f 2-D DCT hardware -bit wrd is inserted int the buffer, FSM ges t the ther state. As a result, ping buffer requires at least eight clck cycles t becme full. In empty state, full and empty utput - full (parallel-ut): If readen is asserted, 96-bit current state f ping buffer is shifted ut and FSM ges t the ther state. Thus, ping buffer becmes in empty state again. In full state, full and empty utput signals are asserted and deasserted, respectively. Cnsequently, it takes a ttal f 64+8=72 clck cycles fr an 8x8 matrix f pixels, where 64 cycles are spent fr lading all elements f 8x8 matrix int the buffer, and 8 cycles are needed fr transferring 8x8 matrix rw by rw t png buffer Png Buffer Png buffer is simply a 96-bit register whse peratin is managed by a fur-state {ned_dct_empty, ned_dct_full, twd_dct_empty, twd_dct_full} finite state machine as fllws: - ned_dct_empty (parallel-in): If writeen is asserted, a new 96-bit wrd (a rw f eight pixels) is laded and FSM ges t ned_dct_full state. MuxSel signal is nt asserted s as t lad frm ping buffer. In this state, full and empty utput - ned_dct_full (cefficient cmputatin): A new 1-D DCT cefficient is cmputed based n the current state f png buffer in every clck cycle. Since there are eight pixels per rw, the machine stays here nly fr eight clck cycle. At the end f the eighth clck cycle, during which the last cefficient fr a rw is being cmputed, it ges t twd_dct_empty state if the eighth rw is being prcessed; therwise, it makes a transitin t ned_dct_empty state. In this state, full and empty utput signals are asserted and deasserted, respectively. - twd_dct_empty (parallel-in): This state is similar t ned_dct_empty state except that MuxSel signal is asserted in rder t lad frm transpse buffer (a clumn f eight 1- D DCT cefficients) instead f ping buffer. - twd_dct_full (cefficient cmputatin): This state is similar t ned_dct_full state except that it ges t either ned_dct_empty state if the eighth clumn is being prcessed, r twd_dct_empty state at the end f the eighth clck cycle. With respect t the png buffer peratin, 64+8=72 clck cycles are required fr the cmputatin f 1-D and 2-D DCT cefficients. As a result, png buffer cmpletes the prcessing f 8x8 matrix f pixels in 144 clck cycles. Furthermre, ping and png buffers tgether intrduces (72+144)-8=208 clck cycles f latency D DCT Accrding t [9], eight-pint 1-D DCT can be cmputed based n the rw-clumn decmpsitin technique as fllws:

3 writedata[11:0] writedata[95:84] writedata[23:] writedata[83:72] writedata[35:24] writedata[71:60] writedata[47:36] writedata[59:48] w[9:0 w[19: w[29:20 w[39:30 88 Registe Clc 88 Run Run Run Run Fig. 2. Architecture f 1-D DCT hardware where z i is the transfrmed cefficient, x i is the pixel data, a=c 1, b=c 2, c=c 3, d=c 4, e=c 5, f=c 6, g=c 7, C i =0,5cs(kπ/16), i=0,1,..7, and k=1,2,..7. Let X 0 = x 0 +x 7, X 2 = x 1 +x 6, X 4 = x 2 +x 5, X 6 = x 3 +x 4, X 1 = x 0 -x 7, X 3 = x 1 -x 6, X 5 = x 2 -x 5, and X 7 = x 3 -x 4. In rder t calculate the cefficients by means f these equatins, 1-D DCT architecture in Fig. 2 is designed. In Fig. 2, the tpmst cmpnent is used t cmpute either X 0 =(x 0 +x 7 ) when =0 r X 1 =(x 0 -x 7 ) when =1, and s n. As a result, is asserted nly if an dd-indexed cefficient {z 1, z 3, z 5, z 7 } is calculated; cmpnents find ut either {X 0, X 2, X 4, X 6 } r {X 1, X 3, X 5, X 7 } in parallel. After add/sub peratins, fur integer multiplicatin peratins are perfrmed in parallel fr every cefficient. In Fig. 2, w[39:0] dentes the set f weights used during a multiplicatin. Fr example, z 2 = b * X 0 + f * X 2 f * X 4 b * X 6 and w[39:0] ={b *, f *, -f *, -b * }, where * is used t indicate -bit 2 s cmplement representatins f the related weight values. Even thugh it is nt shwn in Fig. 2, there is single 8 40-bit lk-up table where it is addressed by 3-bit index value f the cefficient being cmputed and its each 40-bit rw stres fur weights in 2 s cmplement representatin per cefficient. After multiplicatin peratins, there is 88-bit register whse peratin is cntrlled by a tw state {empty, full} FSM as fllws: - empty: If writeen is asserted, a new 88-bit wrd is laded int register and FSM ges t the ther state. In empty state, full signal is deasserted, and empty_transpse (empty signal fr transpse buffer) and empty_utbuff (empty signal fr utput buffer) signals are asserted. - full: While either 1-D DCT r 2-D DCT cefficient is cmputed, if either readen_transpse r readen_utbuff is asserted, 88-bit current state f register is prvided with either transpse buffer r utput buffer, respectively. Furthermre, FSM stays in this state if writeen is fund t be asserted; therwise, it ges t the ther state. In this state, full signal is asserted nly if readen_transpse r readen_utbuff is nt asserted, and empty_transpse and empty_utbuff signals are deasserted, respectively. -bit result {r 21, r 20,, r 0 } f signed multiplicatin is runded t -bit 2 s cmplement number by a cmbinatinal lgic circuit based n the sign f result as fllws: - psitive: There are three cases: If {r 21, r 20,, r } is the maximum psitive number, the runded result is equal t {r 21, r 20,, r }. If {r 21, r 20,, r } is nt the maximum psitive number and r 9 =0, the runded result is equal t {r 21, r 20,, r }.

4 If {r 21, r 20,, r } is nt the maximum psitive number and r 9 =1, the runded result is equal t {r 21, r 20,, r } negative: If r 9 =0, it is equal t {r 21, r 20,, r }; therwise, {r 21, r 20,, r } + 1. After runding, a fur-input, -bit adder tree is utilized t find ut either 1-D r 2-D cefficient value in 2 s cmplement representatin. It shuld be nted that 1-D DCT cmpnent adds nly ne clck cycle f latency due t its register, which results in 208+1=209 clck cycles f latency in ttal Transpse Buffer Transpse buffer is a 63 =756-bit shift-register whse peratin is similar t the ne in [4]. There are tw related scenaris: - serial-in: If writeen is asserted due t deasserting empty_transpse during 1-D DCT cmputatin, a new - bit cefficient is serially shifted in transpse buffer. Fr bth scenaris, full and empty signals are never asserted and deasserted, respectively. - parallel-ut: Cnsider that shift_register={reg 62, reg 62,, reg 0 } is cmpsed f 63 -bit registers. When the shift register becmes full, a set f eight registers clumn={reg 56, reg 48, reg 40, reg 32, reg 24, reg 16, reg 8, reg 0 } hlds the first clumn f 1-D DCT cefficients. In the next clck cycle, the 64th 1-D DCT cefficient is shifted in while the first clumn is laded int png buffer, in which bth writeen and readen are asserted. After the right-shift, clumn will hld the secnd clumn f 1-D DCT cefficients. In a similar manner, whenever readen is asserted by png buffer, the buffer is shifted t the right and clumn stres the next clumn cefficients Output Buffer Output buffer hlds 2-D DCT cefficients and prvides islatin between 2-D DCT hardware in Fig. 1 and anther cmpnent that will be cnnected its utput. Output buffer has tw registers, namely reg 0 and reg 1, and their peratin is cntrlled by a three-state {empty, almst-full, full} FSM as fllws: - empty: Bth registers are empty. If writeen is asserted, a new -bit wrd is laded int reg 0 and FSM ges t almst-full state. In empty state, full and empty utput - almst-full: If bth writeen and readen are asserted r deasserted, it stays in this state. Furthermre, if they are asserted, a new wrd is laded int reg 0. If writeen is asserted, but readen is deasserted, a new wrd is laded int reg 1 and it ges t full state. If writeen is nt asserted, but readen is asserted, it ges t empty state since reg 0 has been read. In almst-full state, full and empty utput full: If readen is asserted, it ges t almst-full state while ld reg 1 is cpied int reg 0. In full state, full and empty utput signals are asserted and deasserted, respectively. It shuld be emphasized that utput buffer cmpnent intrduces nly ne clck cycle f latency, which results in 209+1=2 clck cycles f ttal latency fr the prpsed 2-D DCT hardware. 3. Implementatin Results and Cmparisns The 2-D DCT design presented in this study is described as a device independent fashin in Verilg HDL, simulated and verified by a test-bench using Xilinx ISim, and synthesized using Xilinx ISE 14.7 fr Xilinx Spartan 3E (XC3S500E- 5VQ0), Virtex IV (XC4VSX35-FF668), and Virtex 7 (XC7VX330T-3FFG1157) FPGA devices. The prpsed 2-D DCT architecture is cmpared against tw ther cmpetitive designs implemented fr Virtex IV and Spartan 3E by [6] and [8] in Table 1 and Table 2, respectively. It shuld be nted here that bth [6] and [8] are based n the rwclumn decmpsitin methd and use tw 1-D DCT cres with a transpse buffer between them. Their main difference is due t their implementatins f 1-D DCT cre, which will als be evident in the fllwing tables. Table 1. Device utilizatins using Xilinx Virtex IV Lgic Utilizatin Used [6] Used Available Number f Slices Number f Slice Flip Flps Number f 4 input LUTs Number f bnded IOBs Number f DSP48s Blck RAMs Table 2. Device utilizatins using Xilinx Spartan 3E Lgic Utilizatin Used [8] Used Available Number f Slices Number f Slice Flip Flps Number f 4 input LUTs Number f bnded IOBs Number f MULT18X18SIOs Accrding t Table 1, the prpsed design and [6] result in similar device utilizatins except fr DSP48 and Blck RAM resurces. The design in [6] des nt use any multiplier and relies heavily n Blck RAMs fr the implementatin f a 2-D DCT architecture based n distributed arithmetic. In terms f the frequency f these designs, n the ther hand, [6] achieves arund MHz as cmpared t MHz by the presented design. Accrding t Table 2, the prpsed design is clearly superir t [8] that implements a scaled 1-D DCT algrithm. Hwever, [8] with the running frequency f MHz seems t be faster than the 2-D DCT cre that achieves 80.5 MHz n Spartan 3E. The prpsed 2-D DCT hardware with a latency f 2 clck cycles per 8x8 pixel blck, when mapped t a Spartan 3E and Virtex 7 FPGA, takes abut 2.6 µs and 1.02 µs per blck, respectively. These prcessing rates are enugh fr achieving at least 70 fps fr images with 720x480 pixels n Spartan 3E, and 30 fps fr images with 1920x80 pixels. Cnsequently, the presented 2-D DCT can be used as a cre f an M-JPEG vide cmpressr directed t SDTV r HDTV applicatins. 4. Cnclusins In this paper, a lw area 2-D 8 8 DCT architecture is presented, and its implementatin results are cmpared against tw ther cmpetitive design frm the literature. In rder t

5 keep the FPGA device utilizatin as lw as pssible, the prpsed design is based n the rw-clumn decmpsitin methd, which results in a time-shared use f single 1-D DCT cre fr cmputing 1-D and 2-D DCT cefficients and a transpse buffer fr keeping and transpsing the 1-D cefficients. The prpsed 2-D DCT cre is described in synthesizable Verilg HDL. The synthesis results shw that it requires lw area and achieves high prcessing rates that may be useful in M-JPEG vide cmpressr directed t SDTV r HDTV applicatins. 5. References [1] G. K. Wallace, "The JPEG still picture cmpressin standard, Cmmunicatins f the ACM, vl.34, n. 4, pp.30-44, April [2] M. L. Liu, "Overview f the p x 64 kbit/s vide cding standard," Cmmunicatins f the ACM, vl. 34, N. 4, pp , April [3] D. L. Gall, "MPEG: a vide cmpressin standard fr multimedia applicatins", Cmmunicatins f the ACM, vl. 34, n. 4, pp , April [4] S.-C. Hsia, S.-H. Wang, "Shift-register-based data transpsitin fr cst-effective discrete csine transfrm", IEEE Transactins n Very Large Scale Integratin (VLSI) Systems, vl. 15, n. 6, pp , June [5] L. V. Agstini, I. S. Silva, S. Bampi, "tiplierless and fully pipelined JPEG cmpressin sft IP targeting FPGAs", Micrprcessrs and Micrsystems, vl. 31, n. 8, pp , December [6] R. E. Atani, M. Babli, S. Mirzakuchaki, S. E. Atani, B. Zamanly, "Design and implementatin f a 118 MHz 2D DCT prcessr", IEEE Internatinal Sympsium n Industrial Electrnics, 2008, pp [7] E. D. Kusuma, T. S. Widd, "FPGA implementatin f pipelined 2D-DCT and quantizatin architecture fr JPEG image cmpressin", Internatinal Sympsium in Infrmatin Technlgy, 20, pp [8] T. Pradeepthi, A. P. Ramesh, "Pipelined architecture f 2D- DCT, quantizatin and zigzag prcess fr JPEG image cmpressin using VHDL", Internatinal Jurnal f VLSI Design & Cmmunicatin Systems, vl. 2, n. 3, pp. 99-1, September [9] S. Sanjeevannanavar, N. Nagamani, "Efficient design and FPGA implementatin f JPEG encder using Verilg HDL", Internatinal Cnference n Nanscience, Engineering and Technlgy, 2011, pp [] A. Madisetti, A. N. Willsn, Jr., "A 0 MHz 2-D 8x8 DCT/IDCT prcessr fr HDTV applicatins", IEEE Transactins n Circuits and Systems fr Vide Technlgy, vl. 5, n. 2, pp , April 1995.

It has hardware. It has application software.

It has hardware. It has application software. Q.1 What is System? Explain with an example A system is an arrangement in which all its unit assemble wrk tgether accrding t a set f rules. It can als be defined as a way f wrking, rganizing r ding ne