Part II: 8086/8088 Hardware Specifications and Interfacing Dr. Mohammed Morsy

Transcription

1 Part II: 8086/8088 Hardware Specificatins and Interfacing Dr. Mhammed Mrsy 1

2 Intrductin This curse cvers: Assembly language Prgramming (Intel x86) General system design cncepts, devices and supprt chips Specifically cvers architecture f the Intel micrprcessrs Hardware cnfiguratin and cntrl f: Cmmn micrprcessr supprt chips, e.g. Interrupt cntrller, Ppular I/O devices, e.g. UART, parallel IO, timers This part cvers: Intel 8086, 8088 prcessr hardware specificatins Memry Interfacing, basic I/O interfacing, Interrupts Textbk: Barry B. Brey, 'The Intel Micrprcessrs, Fifth Editin 2

3 Systems Overview General Purpse Cmputing Systems Persnal Cmputers, laptps, wrkstatins, mainframes and servers Embedded Systems It is a system whse principal functin is nt cmputatinal, but which is cn-trlled by a cmputer embedded within it Cnsumer electrnics such as Cell phnes, pagers, digital cameras, camcrders, PDAs, DVD players, calculatrs Autmbiles Transmissin cntrl, cruise cntrl, fuel injectin, antilck brakes, active suspensin Cyber-Physical Systems Integratins f cmputatin, netwrking, and physical prcesses 3

4 Cmputatinal Elements Micrprcessrs The CPU is a unit that fetches and prcesses a set f general-purpse instructins The CPU instructin set includes instructins fr data transfer, ALU peratins, stack peratins, input and utput (IO) peratins and prgram cntrl, sequencing and supervising peratins A micrprcessr is a single VLSI chip that has a CPU and may als have ther units (e.g. caches, flating pint prcessing arithmetic unit, pipelining and super-scaling units) that are additinally present and result in faster prcessing f instructins. Examples: Intel 8085, Intel x86 prcessrs, Mtrla 68HCxxx, Sun Sparc, IBM PwerPC etc. 4

5 Cmputatinal Elements Micrcntrllers A micrcntrller is a single chip unit which, thugh having limited cmputatinal capabilities, pssesses enhanced input-utput capabilities and a number f n-chip functinal units Particularly suited fr use in embedded systems fr real-time cntrl applicatins with n-chip prgram memry and devices Cmmn peripherals include serial cmmunicatin devices, timers, cunters, pulse-width mdulatrs, analg-t-digital and digital-t-analg cnvertrs Examples: Mtrla 68HC11xx, HC12xx, HC16xx, Intel 8051, 80251, PIC 16F84, PIC18, ARM9, ARM7, Atmel AVR etc. 5

6 Cmputatinal Elements Digital Signal Prcessr Essential fr systems that require large number f peratins n digital signals, which are the digital encding f analg signals like vide and audi They carry ut cmmn signal prcessing tasks like signal filtering, transfrmatins r cmbinatins Used widely in image prcessing applicatins, multimedia, audi, vide, HDTV, DSP mdem and telecmmunicatin prcessing systems. They perfrm math-intensive peratins, including peratins like multiplicatin and divisin. Examples: TI TMS320Cxx, Analg Devices SHARC, Mtrla 5600xx, etc. 6

7 Cmputatinal Elements Prgrammable Lgic Devices (PLD)/ Field Prgrammable Gate Arrays (FPGA) Cntains general purpse lgic elements that can be prgrammed t implement desired functinality, very flexible fr implementing custm lgic circuits PLD usually are smaller and cntain prgrammable gates like AND/OR arrays FPGAs prvide lt mre functinality and can be used t implement cmplex designs FPGAs can have n-chip micrprcessrs, memry, DSP, cmmunicatin devices Examples: Xilinx Virtex, Spartan series FPGAs, Actel, Altera, Lattice, QuickLgic 7

8 Cmputatinal Elements Applicatin Specific Integrated Circuits (ASICs)/ System-n-a-chip (SOCs) Custm designed VLSI chips that perfrm the required functin Functinality can be integrated using IP (Intellectual prperty) cres General purpse prcessrs are als available as IP cres and can be integrated n the chip Embedded prcessrs are available frm ARM, Intel, Texas Instruments and varius ther vendrs Only feasible fr high vlume, relatively high cst systems as initial csts and time-t -market can be significant 8

9 Intel x86 Family Evlutin In this curse we fcus n the Intel x86 architecture, assciated peripherals and assembly language prgramming. Hwever, cncepts cvered apply t ther lgic families. 4004: 4 -bit micrprcessr 4KB main memry 45 instructins PMOS technlgy 50 KIPS 8008: (1971) 8 -bit versin f KB main memry 48 instructins NMOS technlgy 8080: (1973) 8 -bit micrprcessr. 64KBmain memry. 2 micrsecnds clck cycle time; 500,000 instructins/sec. 10X faster than

10 Intel x86 Family Evlutin 8085: (1977) 8-bit micrprcessr - upgraded versin f the KB main memry. 1.3 micrsecnds clck cycle time; 769,230 instructins/sec. 246 instructins. Intel sld 100 millin cpies f this 8-bit micrprcessr. 8086: (1978) 8088 (1979) 16-bitmicrprcessr. 1MB main memry. 2.5 MIPS (400 ns). 4- r 6-byte instructin cache. Other imprvements included mre registers and additinal instructins : (1983) 16-bit micrprcessr very similar in instructin set t the MB main memry. 4.0 MIPS (250 ns/8mhz). 10

11 Intel x86 Family Evlutin Reprt the Intel x86 prcessr family enhancements shwing the fllwing: Fabricatin technlgy, transistr cunt, and chip area. Operating frequency, bus width, and thrughput in MIPS. Ntable enhancements and breakthrughs Applicatins and limitatins f each generatin 11

12 Prcessr Basic Cmpnents 12

13 Prcessr Basic Architecture (Vn Neumann Bus Architecture) 13

14 8086/88 Device Specificatins Bth are packaged in DIP (Dual In-Line Packages) 1. The 8086 has 16-bit data bus (AD 0 -AD 15 ), but the 8088 has 8-bit data bus (AD 0 -AD 7 ). 2. The 8086 has M/IO, but the 8088 has IO/ M 8086 draws a maximum supply current f 360 ma, 8088 draws a maximum supply current f 340 ma. Bth micrprcessrs perates in ambient temperature between 0 C and 70 C. Extended temperature-range versins are available 14

15 8086 Pinut 15

16 8086 Pin Functins 16

17 8086 Pin Functins 17

18 8086 Pin Functins 18

19 8086 Pin Functins 19

20 8086 Pin Functins 20

21 Clck Generatin The 8284A is an ancillary cmpnent t the 8086/8088 Clck generatin RESET synchrnizatin READY synchrnizatin Peripheral clck signal 21

22 Clck Generatin 22

23 8284A Clck Generatr 23

24 8284A Clck Generatr Crystal is cnnected t X1 and X2. XTAL OSC generates square wave signal at crystal's frequency which feeds: An inverting buffer (utput OSC) which is used t drive the EFI input f ther 8284As. 2-t-1 MUX: F/ C selects XTAL r EFI external input. The MUX drives a divide-by-3 cunter (15MHz t 5MHz). This drives: The READY flip-flp (READY synchrnizatin). A secnd divide-by-2 cunter (2.5MHz clk fr peripheral cmpnents). The RESET flip-flp. CLK which drives the 8086 CLK input. 24

25 8284A Clck Generatr RESET: Negative edge-triggered flip-flp applies the RESET signal t the 8086 n the falling edge The 8086 samples the RESET pin n the rising edge Crrect reset timing requires that the RESET input t the micrprcessr becmes a lgic 1 NO LATER than 4 clcks after pwer up and stay high fr at least 50µs 25

26 8284A Clck Generatr 26

27 Bus Buffering and Latching Fr very large systems, the buses are buffered. WHY? The address/data bus are multiplexed t save the number f pins required fr the 8086/8088 IC. They must be demultiplexed. WHY? All cmputer systems have three buses: Address bus Data bus Cntrl bus These buses must be present t interface memry and I/O. 27

28 Bus Buffering and Latching Cmputer systems have three buses: Address, Data, and Cntrl The Address and Data bus are multiplexed (shared)due t pin limitatins n the The ALE pin is used t cntrl a set f latches. All signals MUST be buffered Buffered Latches fr A0-A15 Cntrl and A16-A19+ BHE are buffered separately. Data bus buffers must be bidirectinal buffers. In an 8086 system, the memry is designed with tw banks High bank cntains the higher rder 8-bits and lw bank the lwer rder 8-bits Data can be transferred as 8 bits frm either bank r 16-bits frm bth BHE pin selects the high-rder memry bank 28

29 Bus Buffering and Latching 29

30 Timing In General The 8086/8088 uses the memry and I/O in perids f time called bus cycle. Each bus cycle equal t 4 system-clcking perids (T states). If the clck is perated at 5 MHz, ne bus cycle is cmpleted in 800ns. The 8086/8088 reads r writes data at the rate f 1.25 millin times a secnd. 30

31 Timing In General During the first clcking perid (T 1 ): The address is placed n the Address/Data bus. Cntrl signals (M/ IO, ALE and DT/ R) specify memry r I/O, latch the address nt the address bus and set the directin f data transfer n data bus During the secnd clcking perid (T 2 ): The 8086/8088 issues the RDr WR signal fr read r write the data The 8086/8088 issues DEN enables the memry r I/O device t receive the data fr writes and the 8086/8088 t receive the data fr reads 31

32 Timing In General During the third clcking perid (T 3 ): This cycle is prvided t allw memry t access data. READY is sampled at the end f T 2 If lw, T 3 becmes a wait state Otherwise, the data bus is sampled at the end f T 3 During the furth clcking perid (T 4 ): All bus signals are deactivated, in preparatin fr next bus cycle Data is sampled fr reading Data writes ccur fr writing 32

33 Bus Timing 33

34 Bus Timing 34

35 Read Bus Timing 35

36 Read Bus Timing 36

37 Bus Timing Each BUS CYCLE n the 8086 equals fur system clcking perids (T states) The clck rate is 5MHz, therefre ne Bus Cycle is 800ns and the transfer rate is 1.25MHz Memry specificatins (memry access time) must match cnstraints f system timing Fr example, bus timing fr a read peratin shws almst 600ns are needed t read data Hwever, memry must access faster due t setup times, e.g. Address setup and data setup 37

38 Bus Timing READY: An input t the 8086 that causes wait states fr slwer memry and I/O cmpnents A wait state (T W ) is an extra clck perid inserted between T 2 and T 3 t lengthen the bus cycle 38

39 Minimum Mde versus Maximum Mde Minimum mde: It is the least expensive way t perate the 8086/8088. It csts less because all the cntrl signals are generated inside the micrprcessr. It allws the 8085A peripherals t be used. Maximum mde: It is drpped frm the Intel family beginning frm All the cntrl signals must be externally generated. An external bus cntrller is used. It is used nly when the system cntains external cprcessr. 39

40 8288 Bus Cntrller 40

41 MAX Mde 8086 System 41