ALU Design. ENG2410 Digital Design Datapath Design. Parts of CPU. Memory and I/O. Resources. Week #9 Topics. School of Engineering 1

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1 ENG2410 Digital Design Datapath Design Datapath cnsists f: Parts f CPU Registers, Multiplexrs, Adders, Subtractrs and lgic t perfrm peratins n data (Cmb Lgic) Cntrl unit Generates signals t cntrl data-path Accepts status signals t perfrm sequencing Fall 2017 S. Areibi Schl f Engineering University f Guelph Cntrl Data Path 4 Week #9 Tpics Memry and I/O Data Paths and Operatins The Arithmetic/Lgic Unit Register Transfer Operatins Micr-Operatins Multiplexer-Based Transfer Bus-Based Transfer Cmplete Data Path Design Pipelining Cntrl Unit + Data Path + Memry + Input/Output = Micr-cmputer System MEMORY Input and Output 2 5 Resurces Chapter #7, Man Sectins 7.2 Register Transfers 7.3 Register Transfer Operatins 7.4 VHDL and RTL 7.5 Micr Operatins 7.6 Multiplexer Based Transfers 7.8 Bus Based Transfers ALU Design 3 6 Schl f Engineering 1

2 Arithmetic Lgic Unit (ALU) Single Stage ALU The ALU is a cmbinatinal circuit that perfrms a set f basic arithmetic and lgic peratins. An adder can perfrm additin, subtractin, Lgic unit can perfrm AND, OR, NOT peratins Select lines are used t determine the peratin t be perfrmed. Design a 1-bit Arithmetic unit Design a 1-bit Lgic unit Cmbine the tw units t frm a 1-bit Arithmetic/Lgic Use S2 t chse either Arithmetic r Lgic Operatins Replicate as many times t frm an n-bit ALU 7 10 ALU Design using Hierarchy Arithmetic Circuit The ALU will have: 2 cntrl lines S 0,S 1 fr peratin selectins (+/-) 1 cntrl line S 2 t select lgical versus arithmetic peratins The basic cmpnent f an arithmetic circuit is a: N-bit Ripple Carry Adder (Parallel Adder). By cntrlling the data inputs t the parallel adder, it is pssible t btain different types f arithmetic peratins (C in is als an input) Select lines S0, S1 can be used t cntrl input Y. Why? Hw? Start designing in parts 8 11 Recall Design f Adder/Subtractr Single Stage Design B 0 B 0 01 S lw fr add, high fr subtract Inverts each bit f B if S is 1 Adds 1 t make 2 s cmplement 9 12 Schl f Engineering 2

3 Use MUX instead f XOR B 1 B 1 B 0 B 0 MUX S S 0 MUX 0 S Design f B Select Lgic Use a 4-t-1 Mux (Straight Frward Slutin). Can we d better? YES: simplify the expressin frm the truth table using a K-Map A 1 A 0 C 2 FA C 1 FA C 0 S 1 S Functinality 1-bit (Single Stage) Arithmetic Circuit Hw d we implement this? 0 B B 1 MUX The B lgic is nthing but a 2-t-1 Mux instead f the 4-t-1 Mux S 1 S Lking Inside 4-Bit Arithmetic Circuit What pssible functinality can I achieve if I cntrl the Y Value t the n-bit Adder? B Input Lgic 0 B B Duplicating the ne stage fur times will prduce a 4-bit circuit Table Functinality Schl f Engineering 3

4 Lgic Sectin Design One Stage Lgic Circuit Generus number f peratins Arithmetic/Lgic Unit The lgic circuit can be cmbined with the arithmetic circuit t prduce an ALU. I. Selectin variables S 1 and S 0 can be cmmn t bth circuits, II. A third selectin variable S 2 can be used t differentiate between the lgic and arithmetic peratins. One Stage ALU Mux t chse Arithmetic r Lgic One Stage Arithmetic Circuit N-bit ALU Schl f Engineering 4

5 n-bit ALU Duplicate the ne stage n times!! Register Transfer Language (RTL) Register Transfer Language (RTL): used t describe CPU rganizatin in high-level terms RTL expressins are made up f elements which describe the registers being manipulated, and the micr-ps being perfrmed n them Here are the basic cmpnents f RTL expressins: Resulting Cntrl The ne stage ALU can prvide I. 8 arithmetic, and II. 4 lgic peratins. Register Transfer Language (RTL) Registers named in uppercase PC, IR (instructin), R3 The peratins n the data in registers are called micrperatins Micr-Operatins RTL Basic peratins f the datapath Example: 1. Mving data frm ne register t anther 2. Adding the cntents f tw registers 3. Incrementing the cntents f a register The cntrl unit prvides the signals that sequence the micr-peratins in a prescribed manner The results f a currently executing micr-peratin may determine bth the sequence f cntrl signals and the sequence f future micr-peratins t be executed (e.g. BNE) A micr peratin is expected t cmplete in ne clck Schl f Engineering 5

6 RTL Syntax nt VHDL (but similar) Transfer frm R1 t R2 R2 R1 1. R2 is destinatin 2. R1 is surce Cnditinal If(K1 = 1) then (R2 R1) K1: R2 R1 as a shrter frm K1: R2 R1 Transfer Transfer at the clck edge When K1 is high n bits wide Types f Micr-peratins 1. Transfer (have just lked at) 2. Arithmetic 3. Lgic 4. Shift Nte memry transfers Symbls DR M[AR] (cntents f Memry) Arithmetic Basic ps (additin, subtractin,..) R0 R1 + R2 Subtractin by 2 s cmplement Schl f Engineering 6

7 Ntatin is Shrthand fr Hardware Multiplexer-Based Transfers Cnsider and Nte: verflw and carry registers X K1: R1 R1 + R2 XK1 : R1 R1 + R2 + 1 There are ccasins when a register receives data frm tw r mre different surces at different times. Recall that multiplexers are used t cnditinally transfer values frm the input t the utput Lgic Micr-peratins Multiplexer-Based Transfers Cnsider if ( K1 = 1) then ( R0 R1) else if ( K 2 = 1) then R0 R2 OR ntatin a little cnfusing ( K1+ K 2) : R1 R1 R2 Shws tw types f syntax fr ORs Which can als be expressed as K1: R0 R1, K1 K 2 : R0 R2 Blck diagram? Shift Micrperatins Multiplexer Blck Diagram Here just the basic ne-bit shifts K1: R0 R1, K1 K 2 : R0 R2 Bit falls ff the end, zer shifted in Schl f Engineering 7

8 Detailed Bus-Based Transfers A Bus is a shared transfer path. It is characterized by a set f cmmn lines (i) Data + (ii) Cntrl, (iii) Status The cntrl signals fr the lgic select a single surce and ne r mre destinatins n any clck cycle. SRC1 DEST1 SRC2 DEST Simple Case: using Muxes! Signals frm the Cntrl Unit Bus Based Transfer Signals S 2, S 1, S 0 select the surce R1R0, R2R0 Signals L 0, L 1, L 2 enable lading f the registers. The single bus (n the right) One mux One utput bus Capabilities?? Bus-Based Transfers Hw abut when there are lts f registers? We can use buses and send data ver cmmn set f wires Busses are mre efficient scheme fr transferring data between registers! Transfers Only single surce Abut ½ the hardware Select/Lad Signals (table) Limitatins! Schl f Engineering 8

Three-State Bus Remember three-state drivers allw having multiple utputs share wire Nte the small inverted triangle dentes the 3-state utput f the register.

9 Three-State Bus Remember three-state drivers allw having multiple utputs share wire Nte the small inverted triangle dentes the 3-state utput f the register. A bus can be cnstructed with the three state buffers. Many three state buffer utputs can be cnnected tgether t frm a bit line f a bus less delay than multiplexer based systems Memry Transfers Usually ne r mre buses assciated with memry Address Data Nte that memry can be slwer, s may have t use cmplex timing Address n ne clck cycle Data latched at later clck cycle Same Example with 3-State Prperties f Memry Ntice that bth systems in the figure have the same capability in term f transfers. Hwever the 3-state bus has: Fewer wires Fewer cmpnents Easier t expand! 1. Vlatile Memry disappears if pwer ges ut Typical cmputer RAM Static RAM (SRAM), Cache Dynamic RAM (DRAM) Main Memry 2. Nnvlatile ROM Flash memries Magnetic memries like disk, tape Simple View f RAM Memry Transfer Wrd size n-bits Sme capacity 2 k k bits f address line A read line A write line Schl f Engineering 9

10 Memry Transfer Data Paths --> ALU + Strage Read: DR M[AR] where M dentes Memry, DR dentes Data Register, and AR dentes Address Register Write: M[AR] DR Write: M[A1] D2 Cmputer Systems ften emply a number f strage elements in cnjunctin with a shared peratin unit called an Arithmetic/Lgic Unit (ALU) t frm data path. T perfrm a micr peratin, the cntents f a specified surce register is applied t the inputs f the shared ALU. The ALU perfrms an peratin, and the result f this peratin is transferred t a destinatin register Memry Transfer Data Paths, single clck cycle Since the ALU is designed as a pure cmbinatinal circuit, the entire register transfer peratin frm the surce registers, thrugh the ALU, and int the destinatin register is perfrmed in ne clck cycle. Pint t an address in Memry Read data frm the Memry and Write Int Register D2, D1, D Datapath Retrieve Data Cmplete Datapath Design Write back Results Number Crunching Schl f Engineering 10

11 Datapath A Simple bus-based data path: fur registers, an ALU, and a shifter. Each register is cnnected t tw multiplexers t frm ALU input buses A and B (Register File) Anther Mux is used t chse between Registers and a cnstant. Functinal Unit: ALU and a shifter Anther Mux is used t chse between Functinal Unit and external data (Memry) Datapath Fur status bits are shwn (V,C,N,Z) that can be used by the cntrl unit It is useful t have certain infrmatin based n the results f an ALU peratin available fr use by the cntrl unit t make decisins.??? Make Crrectins Skip an instructin Lps If/Else Statements Datapath Example: R1 R2+R3 Blue signals are generated by cntrl Decder alng with the Lad-enable signal determines the destinatin Register (R0,R1,R2,R3) Signals? A, B select MB Select G Select MF Select MD Select Destinatin (D) Lad enable Datapath MB Select determines if the surce B is a Register r Cnstant. G Select determines the peratin t be perfrmed by ALU. MF Select determines if the utput is the ALU r Shifter MD Select determines if the input t the Register File is the Functin Unit r external Data. Timing f Datapath Schl f Engineering 11

Timing All can ccur in ne clck cycle, but Signals must be available in time t prpagate thrugh muxes, ALU and Be at Register inputs by next ps-edge Pipelining 67 70 Data Path Timing Pipelining The

12 Timing All can ccur in ne clck cycle, but Signals must be available in time t prpagate thrugh muxes, ALU and Be at Register inputs by next ps-edge Pipelining Data Path Timing Pipelining The figure shws the maximum delay values fr each f the cmpnents f a typical data path: 1. 4ns (3ns + 1ns) t read tw perands frm register file. 2. 4ns t perfrm an peratin. 3. 4ns (1ns + 3ns) t write inf back Ttal 12 ns t perfrm a single micr peratin. The rate f executin is then set at 1/12ns = 83.3MHz Can we make it faster? Pipelining explits parallelism at the instructin level. Pipelining is an implementatin technique in which multiple instructins are verlapped in executin. Tday pipelining is key t making prcessrs fast Perfrmance Imprvement Assembly Line Analgy t Data Path Pipeline In additin t prviding a data path that perfrms the necessary register transfer micr peratins, we need t be cncerned abut the speed r rate at which the micr peratins are perfrmed. Hw? A custm prduct being built may pass the assembly line many times befre it is cmpleted. A cnveyr belt mves cmpnents frm stage t stage This technique increases thrughput I. First we need t knw the maximum speed by which ur data path can be run. II. Then we will explre hw we can make it faster.(pipelining) Schl f Engineering 12

Pipelining: Example Cnventinal Data Path Timing Laundry Ann, Brian, Cathy, Dave each have ne lad f clthes t wash, dry, and fld Washer takes 30 minutes Dryer takes40minutes Flder takes 20 minutes A B

13 Pipelining: Example Cnventinal Data Path Timing Laundry Ann, Brian, Cathy, Dave each have ne lad f clthes t wash, dry, and fld Washer takes 30 minutes Dryer takes40minutes Flder takes 20 minutes A B C D The figure shws the maximum delay values fr each f the cmpnents f a typical data path: 1. 4ns (3ns + 1ns) t read tw perands frm register file. 2. 4ns t perfrm an peratin. 3. 4ns (1ns + 3ns) t write inf back Ttal 12 ns t perfrm a single micr peratin. The rate f executin is then set at 1/12ns = 83.3MHz Can we make it faster? T a s k O r d e r Sequential Laundry 6 PM Midnight Time A B C D Pipelined Data Path Timing We can break the delay f 12ns by inserting registers between the different cmpnents f the system. A register is inserted between the functin unit and the register file (OF) Anther register can be inserted between the functin unit and MUX D. (EX + WB) 3 stage pipeline: OF / EX / WB The maximum delay nw is 5ns allwing a maximum clck frequency f 200 MHz Sequential laundry takes (90 x 4 = 360 minutes) 6 hurs fr 4 lads If they learned pipelining, hw lng wuld laundry take? Pipelining Lessns Pipelining T a s k O r d e r 6 PM Time A B C D Tt Time: 210 minutes!! versus 360 with n pipelining Ptential speedup = Number pipe stages Unbalanced lengths f pipe stages reduces speedup Time t fill pipeline and time t drain it reduces speedup Pipelining desn t help latencyf single task, it helps thrughputf entire wrklad 3 Stages Operand Fetch Execute Write Back Schl f Engineering 13

14 Nn-Pipelined Data Path Cnventinal data path 7 x 12ns = 84ns Each peratin takes 12 ns 79 Pipelining Cnventinal data path 7 x 12ns = 84ns Pipelined data path 9 x 5ns = 45ns 80 Summary Data Paths are an essential part f any CPU. ALUs (Arithmetic Lgic Units) are at the heart f any Data Path. Multiplexrs and Tri-State buffers are used extensively in Data Paths (data mvement) Pipelining is a technique t: Imprve thrughput by verlapping instructin executin. Des nt imprve the latency f each instructin.. 81 Schl f Engineering 14

It has hardware. It has application software.

It has hardware. It has application software. Q.1 What is System? Explain with an example A system is an arrangement in which all its unit assemble wrk tgether accrding t a set f rules. It can als be defined as a way f wrking, rganizing r ding ne