Embedded Test Resource to Reduce the Required Memory and Channels of Tester

Size: px

Start display at page:

Download "Embedded Test Resource to Reduce the Required Memory and Channels of Tester"

Charles Bailey
5 years ago
Views:

1 IMTC 25 Instrumentatin and Measurement Technlgy Cnference Ottawa, Canada, 7-9 May 25 Embedded Test Resurce t Reduce the Required Memry and Channels f Tester Yinhe Han Yu Hu Huawei Li iawei Li Institute f Cmputing Technlgy, C Beijing, 8 Graduate Schl f the Chinese Academy f Sciences, Beijing, 39 P. O. Bx 274, Beijing, 8, Peple s Republic f China {yinhes, lxw}ict.ac.cn Abstract An embedded test stimulus decmpressr is presented t generate the test patterns, which can reduce the required vectr memry and channels f autmatic test equipment(ate). The decmpressr cnsists f a peridically alterable MU netwrk which has multiple cnfiguratins t decde the input infrmatin flexibly. A cmplete synthesis flw is presented t generate the MUs netwrk autmatically. With the dedicated effrts, the lwcst ATE with lw data bandwidth can be used t test the systemn-a-chip with high cmplexity. Keywrds Autmatic Test Equipment, Test Stimulus Decmpressr, MUs Netwrk I. INTRODUCTION Testing digital circuit accunts fr a large part f the cst t design, manufacture and service an electric system a trend that is prjected t cntinue and accelerate []. With increasing the cmplexity and perfrmance requirements f system-n-a-chip (SC), the expensive test resurces must be augmented int the ATE t test the big-irn. These test resurces include: the large-vlume vectr memry t stre the test patterns, the number f test channels t drive and mnitr the signals and the high test frequency t prvide the at-speed test capacity, etc.. The ATEs with expensive resurces, at ver $3.5 millin apiece fr a 52-pin, 4- MHz versin, represent a large and significant cntributin t the verall cst f a chip. Stimulus Lw-Cst ATE D ec m pr e ss r /RZ%DQG:LGWK +LJK%DQG:LGWK Cre Scan-Based Circuit Respnse Fig. The cnceptual test architecture with embedded test resurce C m p ac t r Test resurce embedded n chip can be used t mitigate the requirement f tester which has high-vlume vectr memry and the great number f channels. The cnceptual test architecture with embedded test resurce is shwn in Fig. A stimulus decmpressr and a respnse cmpactr are inserted between the ATE and circuit-under-test(cut). The cmpressed stimulus data are transferred frm the vectr memry f ATE t the n-chip decmpressr thrugh few data channels. The decmpressr decdes the cmpressed stimulus int riginal test patterns and applies them t the CUT. The test respnses are utputted t a cmpactr and then the cmpacted data are transferred t ATE t cmpare. Thus, nly the lwer data bandwidth is required in the ATE, which means a lw-cst ATE can be used t test a high-cmplexity SOC. As described in the abve paragraph, tw kinds f test resurces can be placed n chip. In this paper, the test stimulus decmpressr will be fcused n. Test stimulus cmpressin is a very well researched tpic and a number f techniques have been presented. Glmb[2], VIHC[3], dictinary-based[4][5], nine cded[6] are sme cding techniques t cmpress the test stimulus. Reda [7] presents a mutatin decder t cmpress test patterns int bit stream that indicates which bits need t be flipped in current test slice t btain the subsequent ne. LFSRs are applied in [8] t expand the input infrmatin. A large LFSR driven by few external pins is presented. It is cmpsed f a large number f smaller LFSRs, each f which feeds a scan chain. The mutatin versin f LFSR: ring generatr is presented in [9]. Sme ther LFSRs-based techniques are presented in [][]. The ORs netwrk can be used as a decmpressr. They are shwn in [2][3][4][5]. These methds use a netwrk cnsisted by OR gates t expand the input infrmatin. It is a very efficient methd if cmbined with the custm test cmpactin algrithm. In this paper, we will present a decmpressr based n the peridically alterable MUs netwrk, which is lcated between the external input pins and inputs f scan chains. Cmpared t previus ORs netwrk and LFSRs, the cnnectins between external pins and scan chains in the prpsed MUs netwrk can be altered. This means that the slver wuld easily find a slutin, which prvides a mre flexible decding scheme /5/$2. 25 IEEE /5/$2. 25 IEEE 9 Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

2 The rest f this paper is rganized int fur sectins: the prpsed decmpressin architecture is intrduced in Sectin 2. Sectin 3 intrduces hw t design the MUs netwrk. The experimental results are analyzed in the Sectin 4. II. PROPOSED MUS NETWORK DECOMPRESSOR The prpsed embedded dempressin architecture based n MUs netwrk decmpressr is shwn in Fig 2. There are N external scan-in pins that feeds M internal scan chains thrugh the MUs decmpressr, where M>>N. The prpsed scan architecture is similar t the Illinis scan architecture [9] where multiple scan chains are fed thrugh a single scan-in pin. Hwever, the decmpressin architecture presented in this paper is mre efficient than [9] as the cnnectin relatins between the external scanin pins and the internal scan chains can be altered peridically, which results in generating small number f mre effective patterns. The peridic recnfiguratin f the mapping between the scan-in pins and the internal scan chains is dne by changing the cntrl signals f the MU's decmpressr. The cntrl signals are generated by the Cntrl Unit. The Cntrl Unit cnsists f a T-cunter that runs fr T cycles and a T-Shifter which is cmpsed by T registers. The mapping relatin between scan-in pins and the internal scan chains is laded int the T-Shifter thrugh a separate external pin as shwn in the Fig 2. External Pin External Pin 2 External Pin 3 External Pin 4 Embedded Decmpressr MUs Netwrk Cntrl Unit Scan Chain Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 Scan Chain 7 Scan Chain 8 Fig 2. The Prpsed Embedded Decmpressin Hardware It is bvius that the recnfiguratin perid is equal t the length f T-bit shifter, which is als equal t the number f selecting lines in MUs netwrk. Thus, if the number f cnfiguratins f MUs netwrk is C, then the recnfiguratin perid f MUs netwrk T shuld be cnstrained as : T Lg ( C 2 ) Like the ORs netwrk, the MUs netwrk can be represented as a matrix in the frmulatin calculatin. If the input data and utput data f MUs netwrk are and Y, Embedded Cmpactr and the MUs matrix is M, then the relatin between and Y is: [ M ] [ ] = [ Y ] Because the MUs netwrk can be altered, M may be variable in different perids. There is a set f MUs matrixes: {M, M 2,, M C }. In the i th perid, if M i is selected, the decding prcedure will be further calculated as: [ M i ] [ i )* T +,..., i* T ] = [ Y( i )* T +,..., Yi* ( T Equatin.The decding prcedure f MUs Netwrk. M = r r..., and the superscript TR means the transpse. Cmpared t the matrix f ORs netwrk, each rw vectr r i in M i nly cntains single since ne scan chain is nly cnnected t ne targeted external input pin. An example is shwn as: where [ r ] TR i 2 N [Example] In a circuit, 3 external input pins drive 8 scan chains. The MUs netwrk has tw cnfiguratins. One f them is :{-(), 2-(3), 3-(2), 4-(2), 5-(), 6-(), 7-(2), 8-(3) }, where A-(B) means the A th scan chain is driven by B th external input pin. Under these cnnectin relatins, the MUs matrix is: M = Anther cnfiguratin is: {-(), 2-(), 3-(), 4-(2), 5-(2), 6-(2), 7-(3), 8-(3) }. Under these cnnectin relatins, the MUs matrix is: M 2 = The MUs netwrk can be cnstructed by sme MUs gates. The implement f MUs netwrk f the abve example is shwn in Fig 3. It cnsists 5 tw inputs MUs gates. Because there are tw cnfiguratins, nly ne cntrl line f MUs netwrk is required. The Pin 4 is used t change the cnfiguratin. If the cntrl line is, the first cnfiguratin M is selected. Otherwise, the secnd cnfiguratinm 2 is selected. ] 9 Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

3 Pin Pin 2 Pin 3 Pin 4 MUs Netwrk Scan Chain Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 Scan Chain 7 Scan Chain 8 Fig 3. The internal structure f MUs Netwrk III. THE SYNTHESIS OF EMBEDDED MUS NETWORK DECOMPRESSOR If the length f the lngest scan chain is L and the number f patterns is P, then the ttal test pattern will cntain L P scan slices. These slices can be partitined int B= L P / T blcks. A blck can be represented by a scan chain incmpatible graph CI-Graph: G(V,E). In this graph, each nde in V represents a scan chain. If the values f tw ndes: V i and V j are incmpatible, there will be a edge between them. The fllwing definitin describes the incmpatible prperty: Definitin: T a scan chain S i, S i [q] is the value f q th scan cell in S i. Given tw scan chains S i, S j, they are incmpatible, if q( q L), then (S i [q]=, S j [q]=) r (S i [q]=, S j [q]=). An example f CI- Graph is shwn in Fig. 4. In the figure, the recnfiguratin perid is assumed as 5 cycles and each fragment f scan chain cntains 5 cells. The blck is cnsisted by 8 scan chains, which crrespnds t 8 ndes in CI-Graph. Cnsidering the scan chain, it is incmpatible with chain 5, chain 7 in the first cell and incmpatible with chain 2, chain 7 in the third cell. S the nde is cnnected with nde 5, 7, and 2. Chain Chain 2 Chain 3 Chain 4 Chain 5 Chain 6 Chain 7 Chain 8 st 2 nd 3 rd 4 th 5 th Perid: 5 cycles Fig 4. An example f CI-Graph CI-Graph 7 6 In the CI-Graph, if cnsidering the cmpatibility, the ndes can be partitined int sme independent sets. In each independent set, any pair f ndes is cmpatible. Thus, the scan chains whse crrespnding ndes are included in an independent set, can be assigned t ne external input. Hence, the fllwing synthesis rule can be btained: Synthesis Rule. If a CI-Graph is partitined int sme independent sets, these independent sets will crrespnd t a cnfiguratin. The scan chains within ne independent set can be cnnected t ne external input pin. In rder t get the least number f external inputs, the least number f independent sets need be fund. It is well knwn that hw t partitin a graph int independent sets is a graph clring prblem. The least number f independent sets is equivalent t btaining the least number f distinct clrs t cver all ndes in CI-Graph. Prperty gives the limitatin: Prperty. If the least number f distinct clrs f each CI- Graph in the ttal pattern is: {G, G 2,, G B } and G=Max(G,G 2,,G B ), the maximum cmpressin rati f MUs netwrk will be cnstrained as: Max ( CR) ( M G) / M where CR is the cmpressin rati, it is calculated as: CR= N. f utputs f MUs Netwrk - N. f inputs f MUs Netwrk N. f utputs f MUs Netwrk The M is the number f scan chains. The least number f distinct clrs is knwn as the chrmatic number. The chrmatic number prblem is a well-knwn NP-Cmplete in graph thery. Many algrithms have been prpsed t btain apprximate clring in reasnable time[2]. T tw CI-Graphs G and G 2, if they satisfy the fllwing tw cnditins, they are N-Mergeability: 92 Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

4 . One graph is a subgraph f anther graph; 2. After merging G and G 2 t a new graph G, the chrmatic number in G is nt greater than N. The set f ndes in new G is V(G)={v v VG ( ) rv V( G2 )) } and the set f edges is E(G)={e e E( G ) re E( G2 ) }). If tw CI-Graphs are nt N-Mergeability, they will be N- Cnflict. Based n the definitin f N-Mergeability, the fllwing prperty abut the area verhead f MUs netwrk can be btained: Prperty 2. If all CI-Graphs are gruped int sme N- Mergeability sets and in each set any pair f CI-Graphs is N-Mergeability, then the least number f cnfiguratins in MUs netwrk is equal t the least number f N- Mergeability sets. Crrespnding t L P / T blcks, there are L P/ T riginal CI-Graphs. Hwever, it des nt mean that the MUs netwrk requires s many cnfiguratins. In fact, the CI-Graphs in a N-Mergeability set can be merged int ne CI-Graph. Similar t least number f external inputs number, the least number f cnfiguratins can be reduced t a graph clring prblem. It is als NP- Cmplete. Many heuristic algrithms can be applied. In this paper, a simple heuristic apprach based n the ccurring rder t merge CI-Graphs is presented t save cmputing time: interacted with Design Cmplier, which is general cmmercial synthesis tl. Start Input the test patterns Partitin the test patterns t blcks. Use the graph-clring algrithm t get the least number f inputs f MUs netwrk. Call CI-Graphs Merging Algrithm t get the incmpatible graphs sets. Use the synthesis rule t get the verilg gate netlist f MUs netwrk. CI-Graphs Merging Algrithm Fig 5. The Synthesis Flw f MUs netwrk Given test patterns: the number f patterns is P and the length f scan chain is L; () Partitin the patters int L P / T blcks; (2) Cnstruct the CI-Graph fr every blck. GL is the CI- Graph list; (3) Select the first CI-Graph in GL as G; (4) While GL is nt empty i. Select a new CI-Graph in GL as G ; ii. If G and G are N-Mergeability, then merge G and G ; (5) GL is nt empty, g t step (4). Algrithm. CI-Graphs Merging Algrithm Cmbining the abve prcedures f MUs netwrk generatin, the cmplete lgic synthesis flw f MUs netwrk decmpressr is depicted in Fig. 5. The flw is implemented using C language cde. It can be easily IV. EPERIMENTAL RESULTS All the algrithms prpsed in this paper are implemented by C language. The test patterns f stuck-at fault are generated by MinTest[7]. The chrmatic numbers f CI-Graphs are btained by the J. Culbersn s[8] prgram. The prpsed experiment flw is: The incmpatible infrmatin f scan chains is recrded as DIMACS standard graph frmat file first. Then the MAIS prgram is called t get the number f independent sets which is anther representatin f the chrmatic number. The maximum chrmatic number is regarded as the inputs f MUs netwrk. Anther script is used t cnvert the independent sets t scan pins grups which can be synthesized int the MUs cnnectin relatins. All the prgrams are executed n the Linux platfrm. 93 Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

5 Table. The required tester memry and channels reductin f MUs netwrk decmpressr Cres N. Len. MinTest MUs Netwrk Decmpressr SC SC N. TDV N. External In N. CDV CR Pat Cnf. S , 7 8 2, % S ,434 8, % S , ,6 89.8% S , ,6 73.9% S ,4 23 8,3 88.6% Avg Cres OR [2] Table 2. The required tester memry cmparing t OR-based and LFSR-based Techniques OR-based OR +Overlap[4] Mutatin +OR[7] Virtual Scan [3] LFSR-based Seed Cmpressin [] EDT[9] 3-Stage[] Prpsed S327 25,344 4,45 5,783 2,788,824,285,585,32 2,52 S585 22,784 3,99,798 76,2 2,438 9,85,584 8,36 S ,28 4,492 3, ,6 S ,856 5, ,264 38,58 34,767 3,458 3,56 25,6 S ,796 2, ,636 22,37 29,397 8,568 27,248 8,3 In the first series f experiments, five large benchmark circuits are selected as circuits under test. The synthesis flw in Fig 5 is used t get the MUs netwrk. The experimental results are listed in Table. In Table, the N. SC, Len. SC, N. Pat, N. External In, N. Cnf. is the number f scan chains, the length f lngest scan chain, the number f MinTest[7] patterns, the number f external inputs, and the number f cnfiguratins in MUs netwrk. TDV is the riginal test data vlume and CDV is the cmpressed test data vlume. The CR is the cmpressin rati. The number f scan chains is selected as t all cases. Frm the Table, we can see, after cmpressin, abut 85% f vectr memry can be saved t the five ISCAS89 circuits n average. In the test channels reductin, after cmpressin, nly 5 channels are required n average, which are least than the expected channels. In the secnd experiment, ur methd is cmpared t the ther prpsed embedded test resurce such as OR-based and LFSR-based techniques. The required data memry f these techniques are listed in Table 2. T the mst f benchmark circuits, the prpsed methd can btain the best results. Even cmparing t EDT, which is regarded as the best tl in cmmercial level, ur methd can btain the better results three f fur circuits. T these three circuits, abut mre 2.2% cmpressin rati can be btained cmpared t EDT n average. V. CONCLUSIONS In this paper, the peridically alterable MUs netwrk is prpsed as an n-chip test resurce t decde the stimulus data, which nt nly reduces the required tester channels, but als reduces the tester memry. The MUs decmpressr can be designed as a play-and-plug cre, which has been shwn t be especially efficient t the large system-n-a-chip in the lw-cst testing envirnment. VI. REFERENCES [] ITRS. 2 Editin. [2] A. Chandra, K. Chakrabarty, System-n-a-Chip Test Data Cmpressin and Decmpressin Architectures Based n Glmb Cdes, Trans. n CAD, 2:3-2, Mar, 2. [3] P. T. Gnciari, B. Al-Hashimi, and N, Niclici, Integrated Test Data Decmpressin and Cre Wrapper Design fr Lw- Cst System-n-a-Chip Testing, Prc. f ITC, pp , 22. [4]. Sun, L. Kinney and B. Vinnakta, Cmbining Dictinary Cding And LFSR Reseeding Fr Test Data Cmpressin, Prc. f DAC, 24 [5] L. Li, K. Chakrabarty, Test Data Cmpressin Using Dictinaries with Fixed-Length Indices, Prc. f VTS, 23. [6] M. Tehranipur, M. Nurani, K. Chakrabarty, Nine-Cded Cmpressin Technique with Applicatin t Reduced Pin- Cunt Testing and Flexible On-Chip Decmpressin, Prc. f DATE, Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

6 [7] S. Reda, A. Orailglu, Reducing Test Applicatin Time Thrugh Test Data Mutatin Encding, Prc. f DATE, pp , 22. [8] A. Jas, B. Puya, N.A. Tuba, Virtual Scan Chains: A Means fr Reducing Scan Length in Cres, Prc. f VTS, pp.73-78, 2. [9] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, Embedded Deterministic Test, Trans. On CAD, 23(5), 24. [] C.V. Krishna, A. Jas, and N. A. Tuba, Reducing test data vlume using LFSR reseeding with seed cmpressin, Prc. f ITC, 22 [] C.V Krishna, N. A. Tuba, 3-Stage Variable Length Cntinuus-Flw Scan Vectr, Prc. f ICCAD, 23. [2] I. Bayraktarglu and A. Orailglu, Test vlume and applicatin time reductin thrugh scan chains cncelment, Prc. f DAC, pp. 5-55, 2. [3] L. Wang,. Wen, H. Furukawa, F. Hsu, S. Lin, S. Tsai, K. S. Abdel-Hafez, and S. Wu, VirtualScan: A New Cmpressed Scan Technlgy fr Test Cst Reductin, Prc. f ITC, 24. [4] W. Ra, I. Bayraktarglu and A. Orailglu, Test Applicatin Time and Vlume Cmpressin Thrugh Seed Overlapping, Prc. f DAC, pp , 23. [5] I. Bayraktarglu, A. Orailglu, Decmpressin Hardware Determinatin fr Test Vlume and Time Reductin thrugh Unified Test Pattern Cmpactin and Cmpressin, Prc. f VTS, 23 [6] M. Sharma, J. H. Patel, J. Rearick, Test Data Cmpressin and Test Time Reductin f Lngest-Path-Per-Gate Test based n Illinis Scan Architecture, Prc. f VTS, 23. [7] I. Hamzaglu and J. H. Patel, Test set cmpactin algrithms fr cmbinatinal circuits, Prc. f ICCAD, pp , 998. [8] J. C. Culbersn, Iterated Greedy Graph Clring and the Difficulty Landscape, Technical Reprt, TR-92-7, University f Alberta, Canada, 99, [9] I. Hamzaglu and J.H. Patel, Reducing Test Applicatin Time fr Full Scan Embedded Cres, Prc. f DFT, pp , Authrized licensed use limited t: INSTITUTE OF COMPUTING TECHNOLOGY CAS. Dwnladed n February, 29 at 3:2 frm IEEE plre. Restrictins apply.

Using SPLAY Tree s for state-full packet classification

Using SPLAY Tree s for state-full packet classification Curse Prject Using SPLAY Tree s fr state-full packet classificatin 1- What is a Splay Tree? These ntes discuss the splay tree, a frm f self-adjusting search tree in which the amrtized time fr an access,