International Journal of Engineering & Science Research

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Internatinal Jurnal f Engineering & Science Research EFFICIENT BUILT-IN SELF-REPAIR STRATEGY FOR EMBEDDED SRAM WITH SELECTABLE REDUNDANCY ABSTRACT AK Sunil Kumar* 1, C Narasimhulu 2 1 M-Tech Schlar,

1 Internatinal Jurnal f Engineering & Science Research EFFICIENT BUILT-IN SELF-REPAIR STRATEGY FOR EMBEDDED SRAM WITH SELECTABLE REDUNDANCY ABSTRACT AK Sunil Kumar* 1, C Narasimhulu 2 1 M-Tech Schlar, VLSI System Design, Department f ECE, SREC, Nandyal (A.P), India. 2 Assistant Prfessr, Department f ECE, Department f ECE, SREC, Nandyal (A.P), India. Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy fr embedded memries. This paper prpses an efficient BISR strategy which cnsists f a Built-In Self-Test (BIST) mdule, a Built-In Address-Analysis (BIAA) mdule and a Multipleer (MUX) mdule. The BISR is designed fleible that it can prvide fur peratin mdes t SRAM users. Each fault address can be saved nly nce is the feature f the prpsed BISR strategy. In BIAA mdule, fault addresses and redundant nes frm a ne-t-ne mapping t achieve a high repair speed. Besides, instead f adding spare wrds, rws, clumns r blcks in the SRAMs, users can select nrmal wrds as redundancy. The selectable redundancy brings n penalty f area and cmpleity and is suitable fr cmpiler design. A practical 4K 32 SRAM IP with BISR circuitry is designed and implemented based n a 55nm CMOS prcess. Eperimental results shw that the BISR ccupies 20% area and can wrk at up t 150MHz. Keywrds: SRAM; Built-In Self-Repair (BISR); Built-In Self- Test (BIST); Built-In Address-Analysis (BIAA). 1. INTRODUCTION Nwadays, the area ccupied by embedded memries insystem-n-chip (SC) is ver 90%, and epected t rise up t94% by 2014 [1]. Thus, the perfrmance and yield f embedded memries will dminate that f SCs. Hwever, memry fabricatin yield is limited largely by randm defects, randm ide pinhles, randm leakage defects, grss prcessing and assembly faults, specific prcessing faults, misalignments, grss pht defects and ther faults and defects [2]. T increase the reliability and yield f embedded memries, many redundancy mechanisms have been prpsed [3-6]. In [3-5] bth redundant rws and clumns are incrprated int the memry array. In [6] spare wrds, rws, and clumns are added int the wrd-riented memry cres as redundancy. All these redundancy mechanisms bring penalty f area and cmpleity t embedded memries design. Cnsidered that cmpiler is used t cnfigure SRAM fr different needs, the BISR had better bring n change t ther mdules in SRAM. T slve the prblem, a new redundancy scheme is prpsed in this paper. Sme nrmal wrds in embedded memries can be selected as redundancy instead f adding spare wrds, spare rws, spare clumns r spare blcks. Memry test is necessary befre using redundancy t repair. Design fr test (DFT) techniques prpsed in 1970 imprve the testability by including additinal circuitry. The DFT circuitry cntrlled thrugh a BIST circuitry is mre timesaving and efficient cmpared t that cntrlled by the eternal tester (ATE) [7]. Hwever, memry BIST des nt address the lss f parts due t manufacturing defects but nly the screening aspects f the manufactured parts [8]. BISR techniques aim at testing embedded memries, saving the fault addresses and replacing them with redundancy. In [9], the authrs prpsed a new memry BISR strategy applying tw serial redundancy analysis (RA) stages. [10] presents an efficient repair algrithm fr embedded memry with multiple redundancies and a BISR circuit using the prpsed algrithm. All the previus BISR techniques can repair memries, but they didn t tell us hw t avid string fault address mre than nce. This paper prpses an efficient BISR strategy which can stre each fault address nly nce. The rest f this paper is rganized as fllws. Sectin II utlines SRAM fault mdels, test algrithms and BIST design. Sectin III intrduces the prpsed BISR strategy. We present the details f the prpsed BISR strategy including the *Crrespnding Authr 243

2 architectures, prcedures and the features. In sectin IV, the eperimental results are reprted. Finally, Sectin V cncludes this paper. 2. FAULT MODELS, TEST ALGORITHMS AND BIST A fault mdel is a systematic and precise representatin f physical faults in a frm suitable fr simulatin and test generatin [11]. Applying the reduced functinal mdel, SRAM faults can be classified as fllws in [12]: AF ---- Address Fault ADOF ---- Address Decder Open Faults CF ---- Cupling Faults CFin ---- Inversin Cupling Faults CFid ---- Idemptent Cupling Faults BF ---- Bridge Cupling Faults CFst ---- State Cupling Faults DRF ---- Data Retentin Faults SAF ---- Stuck-at Faults SOF ---- Stuck Open Faults TF ---- Transitin Faults The details f the fault mdels can be referred in [12]. They are the fundatins f the memry test. An Efficient and ecnmical memry test shuld prvide the best fault cverage in the shrtest test time[13]. BIST is used t test memries in the paper and its precisin is guaranteed by test algrithms. The algrithms in mst cmmn use are the March tests. March tests have the advantage f shrt test time but gd fault cverage. There are many March tests such as March C, March C-, March C+, March 3 and s n. TABLE I cmpares the test length, cmpleity and fault cverage f them. n stands fr the capacity f SRAM. Table 1: Cmparisin Of Different March Tests Algrithms Test Cmpleity Fault cverage March C 11n O(n) AF, SAF, TF, CFin, CFid, and CFst March C- 10n O(n) AF, SAF, TF, CFin, CFid, and CFst March C+ 14n O(n) AF, SAF, TF, SOF, CFin, and CFid March 3 10n O(n) AF, SAF, SOF, and TF As shwn in TABLE I, March C- has better fault cverage than March 3 and shrter test time than March C and March C+. S March C- has been chsen as BIST algrithm in this paper. Its algrithm steps are as fllws: 1 up - write 0 2 up - read 0, write 1 3 up - read 1, write 0 4 dwn - read 0, write 1 5 dwn - read 1, write 0 6 dwn - read 0 Cpyright 2013 Published by IJESR. All rights reserved 244

3 In abve steps, up represents eecuting SRAM addresses in ascending rder while dwn in descending rder. The BIST mdule in the paper refers t the MBISR design f Mentr Graphics. It mainly cnsists f a BIST cntrller, a test vectr generatr, an address generatr and a cmparatr. It can indicate when memry test is dne and weather there is fault in memry. 3. PROPOSED BISR STRATEGY 3.1 Redundancy Architecture The prpsed SRAM BISR strategy is fleible. The SRAM users can decide whether t use it by setting a signal. S the redundancy f the SRAM is designed t be selectable. In anther wrd, sme nrmal wrds in SRAM can be selected as redundancy if the SRAM needs t repair itself. We call these wrds Nrmal-Redundant wrds t distinguish them frm the real nrmal nes. We take a 64 4 SRAM fr eample, as shwn in Figure 1. There are 60 nrmal wrds and 4 Nrmal-Redundant wrds. When the BISR is used, the Nrmal-Redundant wrds are accessed as nrmal nes. Otherwise, the Nrmal-Redundant wrds can nly be accessed when there are faults in nrmal wrds. In this case, the SRAM This kind f selectable redundancy architecture can save area and increase efficiency. After BISR is applied, ther mdules in SRAM can remain unchanged. Thus the selectable redundancy wn t bring any prblem t SRAM cmpiler. This kind f selectable redundancy architecture can save area and increase efficiency. After BISR is applied, ther mdules in SRAM can remain unchanged. Thus the selectable redundancy wn t bring any prblem t SRAM cmpiler. 3.2 Overall BISR Architecture The architecture f the prpsed BISR strategy is shwn in Figure 2. It cnsists f three parts: BIST mdule, BIAA mdule and MUX mdule. We call the SRAM with BISR a system. The BIST mdule uses March C- t test the addresses f the nrmal wrds in SRAM. It detects SRAM failures with a cmparatr that cmpares actual memry data with epected data. If there is a failure (cmpare_q = 1), the current address is cnsidered as a faulty address. The BIAA mdule can stre faulty addresses in a memry named Fault_A_Mem. There is a cunter in BIAA that cunts the number f faulty addresses. When BISR is used (bisr_h = 1), the faulty addresses can be replaced with redundant addresses t repair the SRAM. The inputs f SRAM in different peratin mdes are cntrlled by the MUX mdule. In test mde (bist_h = 1), the inputs f SRAM are generated in BISR while they are equal t system inputs in access mde (bist_h = 0). Cpyright 2013 Published by IJESR. All rights reserved 245

4 3.3 BISR Prcedure Fig 2: Prpsed BISR Architecture Figure 3 shws the prpsed BISR blck diagram. The BISR starts by resetting the system (rst_l = 0). After that if the system wrk in test mde, it ges int TEST phase. During this phase, the BIST mdule and BIAA mdule wrk in parallel. The BIST use March C- t test the nrmal addresses f SRAM. As lng as any fault is detected by the BIST mdule, the faulty address will be sent t the BIAA mdule. Then the BIAA mdule checks whether the faulty address has been already stred in Fault-A-Mem. If the faulty address has nt been stred, the BIAA stres it and the faulty address cunter adds 1. Otherwise, the faulty address can be ignred. When the test is cmpleted, there will be tw cnditins. If there is n fault r there are t many faults that verflw the redundancy capacity, BISR ges int COMPLETE phase. If there are faults in SRAM but withut verflws, the system ges int REPAIR&TEST phase. The same as during TEST phase, the BIST mdule and BIAA mdule wrk at the same time in REPAIR&TEST phase. The BIAA mdule replaces the faulty addresses stred in Fault-A-Mem with redundant nes and the BIST mdule tests the SRAM again. There will be tw results: repair fail r repair pass. By using the BISR, the users can pick ut the SRAMs that can be repaired with redundancy r the nes with n fault. Cpyright 2013 Published by IJESR. All rights reserved 246

5 3.4 Features f the BISR Firstly, the BISR strategy is fleible. TABLE II lists the peratin mdes f SRAM. In access mde, SRAM users can decide whether the BISR is used base n their needs. If the BISR is needed, the Nrmal-Redundant wrds will be taken as redundancy t repair fault. If nt, they can be accessed as nrmal wrds. Table 2: Sram Operatin Mdes Mdes Repair selectin Operatin Default: repair Access nrmal wrds. (bisr_h=1) Repair faults and test. Test mde (test_h=1) Access mde (test_h=0) Dn t repair (bisr_h=0) Repair (bisr_h=1) Dn t repair (bisr_h=0) Access nrmal wrds. Test nly. Access nrmal wrds. Repair faults and write/read SRAM. Access Nrmal- Redundant and nrmal Wrds. Write/read SRAM nly. Secndly, the BISR strategy is efficient. On ne hand, the efficiency reflects n the selectable redundancy which is described as fleible abve. N matter the BISR is applied r nt, the Nrmal-Redundant wrds are used in the SRAM. It saves area and has high utilizatin. On the ther hand, each fault address can be stred nly nce int Fault- A-Mem. As said befre, March C- has 6 steps. In anther wrd, the addresses will be read 5 times in ne test. Sme faulty addresses can be detected in mre than ne step. Take Stuck- at-0 fault fr eample, it can be detected in bth 3 rd and 5 th steps. But the fault address shuldn t be stred twice. S we prpse an efficient methd t slve the prblem in BIAA mdule. Figure 4 shws the flws f string fault addresses. BIST detects whether the current address is faulty. If it is, BIAA checks whether the Fault-A-Mem verflws. If nt, the current fault address shuld be cmpared with thse already stred in Fault-A-Mem. Only if the faulty address isn t equal t any address in Fault-A- Mem, it can be stred. T simplify the cmparisn, write a redundant address int Fault-A-Mem as backgrund. In this case, the fault address can be cmpared with all the data stred in Fault-A-Mem n matter hw many fault addresses have been stred. At last, the BISR strategy is high-speed. As shwn in Figure 4, nce a fault address is stred in Fault-A-Mem, it pints t a certain redundant address. The fault addresses and redundant nes frm a ne-t-ne mapping. Using this methd, Cpyright 2013 Published by IJESR. All rights reserved 247

6 the BISR can quickly get the crrespnding redundant address t replace the faulty ne. 4. EXPERIMENTAL RESULTS The prpsed BISR was designed at RT level and it was synthesized t gate-level using Synpsys DC cmpiler. We use Cadence SOC Encunter t cmplete physical design f a 4K32 SRAM with BISR. The pst simulatin results shw that the frequency f SRAM with BISR is at least 150MHz. The SRAM was implemented based n a 55nm CMOS prcess. The 32 addresses frm H FE0 t H FFF were selected as Nrmal-Redundant addresses. T verify the functin f BISR, a Stuck-at-0 fault was set in the SRAM. Figure 5 shws the layut view f the SRAM with BISR circuitry. BISR brings abut 20% area penalties. 5. CONCLUSION An efficient BISR strategy fr SRAM IP with selectable redundancy has been presented in this paper. It is designed fleible that users can select peratin mdes f SRAM. The BIAA mdule can avid string fault addresses mre than nce and can repair fault address quickly. The functin f BISR has been verified by the pst simulatin. The BISR can wrk at up t 150MHz at the epense f 20% greater area. REFERENCES [1] Semicnductr Industry Assciatin. Internatinal technlgy radmap fr semicnductrs (ITRS), 2003 editin, Hsinchu, Taiwan, Dec [2] Stapper C, Mclaren A, Dreckman M. Yield mdel fr Prductivity Optimizatin f VLSI Memry Chips with redundancy and Partially gd Prduct. IBM Jurnal f Research and Develpment 1980; 24(3): [3] Huang WK, Shen YH, Lmbrardi F. New appraches fr repairs f memries with redundancy by rw/clumn deletin fr yield enhancement. IEEE Transactins n Cmputer-Aided Design 1990; 9(3): [4] Mazumder P, Jih YS. A new built-in self-repair apprach t VLSI memry yield enhancement by using neuraltype circuits. IEEE transactins n Cmputer Aided Design 1993; 12(1). Cpyright 2013 Published by IJESR. All rights reserved 248

7 [5] Kim HC, Yi DS, Park JY, Ch CH. A BISR (built-in self- repair) circuit fr embedded memry with multiple redundancies. VLSI and CAD 6 th Internatinal Cnference, Oct. 1999; [6] Lu S-K, Yang C-L, Lin H-W. Efficient BISR Techniques fr Wrd-Oriented Embedded Memries with Hierarchical Redundancy. IEEE ICIS-COMSAR 2006; [7] Strud C. A Designer s Guide t Built-In Self-Test, Kluwer Academic Publishers, [8] Karunaratne M, Omann B. Yield gain with memry BISR-A case study. IEEE MWSCAS 2009; [9] Kang I, Jeng W, Kang S. High-efficiency memry BISR with tw serial RA stages using spare memries. IET Electrn. Lett 2008; 44(8): [10] Kim H-C, Yi D-S, Park J-Y, Ch C-H. A BISR (Built-In Self-Repair) circuit fr embedded memry with multiple redundancies. Prc. Int. Cnf. VLSI CAD, Oct. 1999; [11] Sachdev M, Zieren V, Janssen P. Defect detectin with transient current testing and its ptential fr deep submicrn CMOS Ics. IEEE Internatinal Test Cnference, Oct. 1998; [12] Mentr Grahics, MBISTArchitect Prcess Guide, Sftware Versin _3, Aug 2009; [13] Andrei P, Sachdev M. CMOS SRAM Circuit Design and Parametric Test in Nan-Scaled Technlgies, CA: Springer, 2008; Cpyright 2013 Published by IJESR. All rights reserved 249

An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy

An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy A. Sharone Michael.1 #1, K.Sivanna.2 #2 #1. M.tech student Dept of Electronics and Communication,