Introduction. ENG2410 Digital Design Memory Systems. Resources. A Digital Computer System. Week #11 Topics. School of Engineering 1.

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1 ENG2410 Digital Design Memry Systems A Digital Cmputer System CPU Cntrl unit Memry Datapath Data/Instructins/cde clck Fall 2017 S Areibi Schl f Engineering University f Guelph Inputs: Keybard, muse, mdem, micrphne Input/Output Outputs: CRT, LCD, mdem, speakers 4 Week #11 Tpics Randm Access Memry Static RAM Array f RAM ICs Dynamic RAM Types f Dynamic RAM Cmparisn Larger Wider Memries Intrductin 2 5 Resurces Picture f Memry Chapter #9, Man Sectins 91 Memry Definitins 92 Randm Access Memry 93 SRAM Integrated Circuits 94 Array f SRAM ICs 95 DRAM ICs 96 DRAM Types Yu can think f memry as being ne big array f data The address serves as an array index Each address refers t ne wrd f data Yu can read r mdify the data at any given memry address, just like yu can read r mdify the cntents f an array at any given index Address FFFFFFFD FFFFFFFE FFFFFFFF Data 3 Wrd 6 Schl f Engineering 1

Memry Signal Types Memry signals fall int three grups Address bus - selects ne f memry lcatins Data bus Read: the selected lcatin s stred data is put n the data bus Write (RAM): The data n the data

2 Memry Signal Types Memry signals fall int three grups Address bus - selects ne f memry lcatins Data bus Read: the selected lcatin s stred data is put n the data bus Write (RAM): The data n the data bus is stred int selected lcatins Cntrl signals - specifies what the memry is t d Cntrl signals are usually active lw Mst cmmn signals are: CS: Chip Select; must be active t d anything OE: Output Enable; active t read data WR: Write; active t write data Classificatin 7 10 Prperties f Memry Classificatin f Memry 1 Vlatile: Memry cntents disappears if pwer turned ff, fund in: Typical cmputer systmes (laptps, desktps) PDA, Smart Phne, ipads, 2 Nnvlatile: Cntents f memry remain even if pwer turned ff, fund in: Smart Phnes, Hard Drives, Memry Sticks 8 11 RAM vs ROM Key Design Metrics 1 Vlatile Memry RAM (Randm Access Memry) Static RAM usually used fr Cache Dynamic RAM used fr Main Memry 2 Nn-Vlatile Memry ROM (Read Only Memry), FLASH Used t stre permanent prgrams in a cmputer system (bting) 9 12 Schl f Engineering 2

3 Memry Technlgies Memry The access time and price per bit vary widely amng these technlgies, as seen in the table belw Memry Technlgy Typical Access time $ per GIB in 2012 SRAM Semicnductr memry ns $500 - $1000 DRAM Semicnductr memry ns $10 - $20 Registers CPU Cache Cntrller Cache Memry Lcal CPU / Memry Bus PCI DRAM C-prcessr Cntrller Peripheral Cmpnent Intercnnect Bus Static RAM Dynamic RAM Flash Semicnductr memry 5,000 50,000 ns $075 - $100 Magnetic Disk 5,000,000 20,000, 000 ns $005 - $010 EISA/PCI Bridge Cntrller Hard Drive Cntrller EISA PC Bus PC Card 1 PC Card 2 Vide Adaptr PC Card 3 SCSI Adaptr SCSI Bus Memry Hierarchy RAM vs ROM The design cnstraints n a cmputer memry can be summed up by three questins (i) Hw Much (ii) Hw Fast (iii) Hw expensive There is a tradeff amng the three key characteristics A variety f technlgies are used t implement memry system Dilemma facing designer is clear large capacity, fast, lw cst!! Slutin Emply memry hierarchy Flip Flps Dynamic RAM registers Cache Main Memry Disk Cache Magnetic Disk Static RAM Cst Capacity Access Time RAM Read/write Vlatile Faster access time Variants SRAM DRAM Applicatin Variables Dynamic memry allcatin Heaps, stacks ROM Read nly Nn-Vlatile Slwer Variants PROM,EPROM EEPROM, FLASH Applicatin Prgrams Cnstants Cdes, etc Remvable Media Main Memry vs Cache Static RAM Dynamic RAM Registers Flipflps Randm Access Memry Static RAM Schl f Engineering 3

4 Randm Access Memries S called because it takes the same amunt f time t address any particular part Types f RAM 1 Static RAM (SRAM), fast, expensive 2 Dynamic RAM (DRAM), slw, cheap Hw is memry accessed? Address Lines, Data Lines Cntrl Signals (R/W, chip select, ) Chip Select and R/W Lines R/W Lines enable reading/writing Usually a chip select line is used Why? T enable RAM chip t be accessed Simple View f RAM Memry: Writing Of sme wrd size n=4,8,16 Sme capacity 2 k k bits f address line, k=10,11, Has a read line Has a write line Sequence f steps Setup address lines Setup data lines Activate write line (maybe a ps edge) The write cycle time is the maximum time frm the applicatin f the address t the cmpletin f all internal memry peratins required t stre a wrd K x 16 memry Writing: Timing Wavefrms Variety f sizes Frm 1-bit wide CPU perates at 50 MHz (20 ns) 4 clck cycles t perfrm a write Issue is n f pins Memry size specified in bytes 1K x 16 bit 2KB memry 10 address lines and 16 data lines Schl f Engineering 4

Memry Reading Steps Setup address lines Activate read line Data available after specified amunt f time Read cycle usually is shrter than write cycle MOSFET: Metal Oxide Semicnductr Field Effect

5 Memry Reading Steps Setup address lines Activate read line Data available after specified amunt f time Read cycle usually is shrter than write cycle MOSFET: Metal Oxide Semicnductr Field Effect Transistr A vltage cntrlled device Dissipates less pwer Achieves higher density n an IC Has full swing vltage 0 5V Memry Wavefrm: Reading nmos Transistr CPU perates at 50 MHz (20 ns) 65 ns required fr a read cycle An nmos Transistr I ds V GS V gs 26 Static RAM: 4T and 6T Static RAM Schl f Engineering 5

SRAM Cell Bit Slice can Becme Mdule VDD VDD VDD GND VDD Basically bit slice is a ne Dimensinal array f memry What type f hardware d we need t access ne rw at a time?

B and B The utputs are gated by the select line als 16 X 1 RAM 4 address lines required t access 16 lcatins A Decder is added t select the different wrds (each 1 bit wide) Fr 16 wrds we need a 4-t-16

6 SRAM Cell Bit Slice can Becme Mdule VDD VDD VDD GND VDD Basically bit slice is a ne Dimensinal array f memry What type f hardware d we need t access ne rw at a time? Simplify Mdeling using Latch Strage is mdeled by an SR latch Cntrl lgic One memry cell per bit Fr select = 0, the stred cntent is held Fr select = 1, the stred cntent is determined by values n B and B The utputs are gated by the select line als 16 X 1 RAM 4 address lines required t access 16 lcatins A Decder is added t select the different wrds (each 1 bit wide) Fr 16 wrds we need a 4-t-16 line Decder Cells cnnected t frm 1 bit psitin Wrd Select gates ne latch frm address lines Nte it selects Reads als B (and B ) set by R/W, Data In and BitSelect When R/W = 0 and BitSelect = 1, then if Data in = 1 the latch will be set (ie a 1 is written) Bit Slice Rw/Clumn Practical memries cntains thusands f wrds!! If RAM gets large, there is a huge decder Als run int chip layut issues Hw can we change the structure f Memry t slve this prblem? Rearrange the memry int 2D ie, matrix layut Schl f Engineering 6

7 16 X 1 as 4 X 4 Array Tw decders Rw Clumn Address just brken up Nt visible frm utside A Single Rw Decder Imagine 32k x 8 = (32 x 1024 x 8) = 262,144 bits 256K bit memry Hw many address lines required t lcate 32K lcatins? A 15 bit address line is required 262,144/8 = 32,768 chunks each 8-bits One clumn layut wuld need a decder with 32,768 utputs Fr a single decder that wuld mean 32,800 gates This is nt practical! Slutin? Cincident selectin 262,144 bits 15-t Address Lines 37 Decder X 1 as 4 X 4 Array Emplying 2 decders instead f 1 rw decder is called cincident selectin Rw Select and Clumn Select A 3 A 2 A 1 A 0 =0000 will attempt t chse RAM cell 0 Cincident Selectin A 32K X 8 cntains 256 Kbits (32 x 1024 x 8 = 262,144 bits) T make the number f rws and clumns equal we take the square rt f 256K, giving 512 = 2 9 A 9-t-512 decder is required fr the rws (9 address lines are fed t the Rw Decder) Remember we need 8 bits f utput!! (Clumn Decder?) Fr the clumns 512/8 = 64 = 2 6 A 6-t-64 line decder is required fr the clumns (6 address lines are fed t the Clumn Decder) Ttal number f gates is nw = 576 gates Thus reducing the ttal gate cunt by 50x 262,144 bits Address Lines 9-t t Address Lines Change frm 16x1 t 8 X 2 RAM Minr change in lgic Try addressing 011 n bard Cells 6,7 are chsen fr reading r writing SRAM Perfrmance Current SRAMs have cycle times in lw nansecnds (say 25ns) Used as cache (typically n-chip r ffchip secndary cache) Sizes up t 256 Mbit r s fr fast chips Schl f Engineering 7

8 Larger Capacity Memry Expansin Decder fr high-rder 2 bits Selects chip Check the address ranges Larger/Wider Memries Wider Memry 64K X 16 Made up frm sets f chips Cnsider a 64K by 8 RAM Nte new symbls fr sets f lines, 8 & 16 bits wide The Chip Select line will activate the memry chip Hw t increase capacity t 256K x 8? Larger: 256k x 8 Use 4 f these chips 256 K x8 Cnnect all utput data lines tgether (tristate) Cnnect all input data line tgether Cnnect all 16 address lines tgether (ie, 16 lines f address t fetch a wrd in any DRAM chip) But we need t activate nly ne chip at a time!! Hw many address lines fr 256K Memry? Hw t select the specific RAM chip? Dynamic RAM Schl f Engineering 8

Dynamic memry DRAM read Operatins Dynamic memry is built with capacitrs A stred charge n the capacitr represents a lgical 1 N charge represents a lgic 0 Hwever, capacitrs lse their charge after a few

with just ne capacitr and ne transistr, while static RAM cells typically require 4-6 transistrs This means dynamic RAM is cheaper and denser mre bits can be stred in the same physical area Precharge

9 Dynamic memry DRAM read Operatins Dynamic memry is built with capacitrs A stred charge n the capacitr represents a lgical 1 N charge represents a lgic 0 Hwever, capacitrs lse their charge after a few millisecnds The memry requires cnstant refreshing t recharge the capacitrs (That s what s dynamic abut it) Dynamic RAMs tend t be physically smaller than static RAMs A single bit f data can be stred with just ne capacitr and ne transistr, while static RAM cells typically require 4-6 transistrs This means dynamic RAM is cheaper and denser mre bits can be stred in the same physical area Precharge bit line t V DD /2 Take the wrd line HIGH Detect whether current flws int r ut f the cell Nte: cell cntents are destryed by the read! Must write the bit value back after reading 49 Dynamic RAM DRAM write Operatins Capacitr can hld charge Transistr acts as gate N charge is a 0 Can clse switch & add charge t stre a 1 Then pen switch (discnnect) Take the wrd line HIGH Set the bit line LOW r HIGH t stre 0 r 1 Take the wrd line LOW Nte: The stred charge fr a 1 will eventually leak ff 50 DRAM Cell Dynamic RAM ( cntinued) B Select T Pump T C DRAM cell (a) Stred 1 Stred 0 (b) (c) Write 1 Write 0 (d) (e) Read 1 Read 0 (f) (g) Schl f Engineering 9

DRAM Characteristics (Why Slw!) DRAM Write Timing Destructive Read When cell read, charge remved Charge must be restred after a read Refresh Capacitrs are nt perfect!

10 DRAM Characteristics (Why Slw!) DRAM Write Timing Destructive Read When cell read, charge remved Charge must be restred after a read Refresh Capacitrs are nt perfect! there s steady leakage Charge must be restred peridically DRAM are dense (lts f cells) s there are many address lines T reduce the physical size f DRAM we can reduce the number f pins by applying the address lines serially in tw parts: Rw Address, and then Clumn Address Hw DRAM Wrks DRAM-chip internal rganizatin A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 64K x 1 DRAM 56 DRAM Read Signaling DRAM Lgic Diagram DRAM has a lwer pin cunt by using same pins fr rw and clumn addresses Delay until data available Schl f Engineering 10

11 DRAM charge leakage DRAM Chip Types Typical devices require each cell t be refreshed nce every 4 t 64 ms DRAM - Dynamic RAM FPM RAM - Fast page-mde RAM EDO RAM - Extended Data Out RAM BEDO RAM - Burst Extended-data-ut RAM SDRAM - Synchrnus Dynamic RAM DDRRAM - Duble Data Rate RAM 64 DRAM Refresh Page Mde DRAM Many strategies Lgic n chip Refresh cunter and Refresh cntrller Refresh cunter is used t prvide the address f the rw f DRAM cell t be refreshed DRAMs made t read & write blcks Example Assert RAS, leave asserted Assert CAS multiple times t read sequence f data Similar fr writes CAS Befre RAS Set clumn address Apply CAS first (ppsite f RW) Then tggle RAS enugh times t cycle thrugh rw addresses On-bard refresh cunter applies the rw addresses CAS Synchrnus DRAM RAS Cl Add Rw Add Rw Add Rw Add Rw Add Schl f Engineering 11

Synchrnus DRAM (SDRAM) Memry Technlgies Duble Data Rate SDRAM Transfers data n bth edges f the clck DRAM: Dynamic Randm Access Memry upside: very dense (1 transistr per bit) and inexpensive dwnside:

caches 67 70 DRAM Evlutin There has been multiple imprvements t the DRAM design in the past 20 years SDRAM: A clck signal was added making the design synchrnus DDR SDRAM: The data bus transfers data

12 Synchrnus DRAM (SDRAM) Memry Technlgies Duble Data Rate SDRAM Transfers data n bth edges f the clck DRAM: Dynamic Randm Access Memry upside: very dense (1 transistr per bit) and inexpensive dwnside: requires refresh and ften nt the fastest access times ften used fr main memries SRAM: Static Randm Access Memry upside: fast and n refresh required dwnside: nt s dense and nt s cheap ften used fr caches DRAM Evlutin There has been multiple imprvements t the DRAM design in the past 20 years SDRAM: A clck signal was added making the design synchrnus DDR SDRAM: The data bus transfers data n bth rising and falling edge f the clck DDR2 SDRAM: Secnd generatin f DDR memry scales t higher clck frequencies DDR3 SDRAM: Third generatin has lwer pwer cnsumptin, higher clck frequency and denser mdules DDR4 SDRAM: Furth generatin, imprvement ver DDR3, high bandwidth, higher speed Hwever it is nt cmpatible with any earlier type f (RAM) due t different signaling vltages Summary RAMs with different characteristics Fr different purpses Static RAM Simple t use, small, expensive Fast, used fr cache Dynamic RAM Cmplex t interface, largest, cheap Needs peridic refresh Dense, slw, used in Main Memry DDR SDRAM Cmparisn Links Ram Guides (nt very technical) Schl f Engineering 12

13 Schl f Engineering 13

Memory Hierarchy. Goal of a memory hierarchy. Typical numbers. Processor-Memory Performance Gap. Principle of locality. Caches

Memory Hierarchy. Goal of a memory hierarchy. Typical numbers. Processor-Memory Performance Gap. Principle of locality. Caches Memry Hierarchy Gal f a memry hierarchy Memry: hierarchy f cmpnents f varius speeds and capacities Hierarchy driven by cst and perfrmance In early days Primary memry = main memry Secndary memry = disks