M68HC11K/D HC11M68HC 1M68HC11M. M68HC11K Family Technical Data. HCMOS Microcontroller Unit

Transcription

1 M68HC11K/D 68HC11M6 HC11M68HC 1M68HC11M HCMOS Microcontroller Unit

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3 nc. MC68HC11K Family Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. Motorola, Inc., 2001 MOTOROLA 3

4 Revision History nc. To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Date Revision Level Revision History Description Page Number(s) October, 2001 N/A Original release N/A 4 MOTOROLA

5 nc. List of Sections Section 1. General Description Section 2. Pin Description Section 3. Central Processor Unit (CPU) Section 4. Operating Modes and On-Chip Memory Section 5. Resets and Interrupts Section 6. Parallel Input/Output Section 7. Serial Communications Interface (SCI) Section 8. Serial Peripheral Interface (SPI) Section 9. Timing System Section 10. Analog-to-Digital (A/D) Converter Section 11. Memory Expansion and Chip Selects Section 12. Electrical Characteristics Section 13. Mechanical Data Section 14. Ordering Information Section 15. Development Support Index MOTOROLA List of Sections 5

6 List of Sections nc. 6 List of Sections MOTOROLA

7 nc. Table of Contents Section 1. General Description 1.1 Contents Introduction Members Features Structure Section 2. Pin Description 2.1 Contents Introduction Power Supply (V DD, V SS, AV DD, and AV SS ) Reset (RESET) Crystal Driver and External Clock Input (XTAL and EXTAL) XOUT E-Clock Output (E) Interrupt Request (IRQ) and Non-Maskable Interrupt (XIRQ) Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/V STBY ) V RH and V RL Port Signals MOTOROLA Table of Contents 7

8 Table of Contents nc. Section 3. Central Processor Unit (CPU) 3.1 Contents Introduction CPU Registers Accumulators A, B, and D (ACCA, ACCB, and ACCD) Index Register X (IX) Index Register Y (IY) Stack Pointer (SP) Program Counter (PC) Condition Code Register (CCR) Carry/Borrow (C) Overflow (V) Zero (Z) Negative (N) Interrupt Mask (I) Half Carry (H) Non-Maskable Interrupt (X) Stop Disable (S) Data Types Opcodes and Operands Addressing Modes Immediate Direct Extended Indexed Inherent Relative Instruction Set Table of Contents MOTOROLA

9 nc. Table of Contents Section 4. Operating Modes and On-Chip Memory 4.1 Contents Introduction Control Registers System Initialization Operating Modes Single-Chip Mode Expanded Mode Bootstrap Mode Special Test Mode Mode Selection Memory Map Control Registers and RAM ROM or EPROM EEPROM Bootloader ROM EPROM/OTPROM (M68HC711K4 and M68HC711KS2) Programming the EPROM with Downloaded Data Programming the EPROM from Memory EEPROM and the CONFIG Register EEPROM Registers EEPROM Programming Control Register Block Protect Register System Configuration Options Register EEPROM Programming EEPROM Programming EEPROM Bulk Erase EEPROM Row Erase EEPROM Byte Erase CONFIG Register Programming RAM and EEPROM Security MOTOROLA Table of Contents 9

10 Table of Contents nc. 4.9 XOUT Pin Control System Configuration Register System Configuration Options 2 Register Section 5. Resets and Interrupts 5.1 Contents Introduction Sources of Resets Power-On Reset (POR) External Reset (RESET) Computer Operating Properly (COP) System System Configuration Register System Configuration Options Register Arm/Reset COP Timer Circuitry Register Clock Monitor Reset System Configuration Options Register System Configuration Options Register Effects of Reset Interrupts Non-Maskable Interrupts Non-Maskable Interrupt Request (XIRQ) Illegal Opcode Trap Software Interrupt (SWI) Maskable Interrupts Reset and Interrupt Priority Reset and Interrupt Processing Low-Power Operation Wait Mode Stop Mode Slow Mode Table of Contents MOTOROLA

11 nc. Table of Contents Section 6. Parallel Input/Output 6.1 Contents Introduction Port A Port B Port C Port D Port E Port F Port G Port H Internal Pullup Resistors Section 7. Serial Communications Interface (SCI) 7.1 Contents Introduction Data Format Transmit Operation Receive Operation Wakeup Feature Short Mode Idle Line Detection Baud Rate Selection SCI Registers SCI Baud Rate Control Register Serial Communications Control Register Serial Communications Control Register Serial Communication Status Register Serial Communication Status Register Serial Communications Data Register MOTOROLA Table of Contents 11

12 Table of Contents nc. Section 8. Serial Peripheral Interface (SPI) 8.1 Contents Introduction SPI Functional Description SPI Signal Descriptions Master In Slave Out (MISO) Master Out Slave In (MOSI) Serial Clock (SCK) Slave Select (SS) SPI Timing SPI System Errors Mode Fault Error Write Collision Error SPI Registers Serial Peripheral Control Register Serial Peripheral Status Register Serial Peripheral Data Register Port D Data Direction Register System Configuration Options Section 9. Timing System 9.1 Contents Introduction Timer Structure Input Capture and Output Compare Overview Timer Counter Register Timer Interrupt Flag 2 Register Timer Interrupt Mask 2 Register Port A Data Direction Register Pulse Accumulator Control Register Table of Contents MOTOROLA

13 nc. Table of Contents 9.5 Input Capture (IC) Timer Input Capture Registers Timer Input Capture 4/Output Compare 5 Register Timer Interrupt Flag 1 Register Timer Interrupt Mask 1 Register Timer Control 2 Register Output Compare (OC) Timer Output Compare Registers Timer Input Capture 4/Output Compare 5 Register Timer Interrupt Flag 1 Register Timer Interrupt Mask 1 Register Timer Control 1 Register Timer Compare Force Register Output Compare 1 Mask Register Output Compare 1 Data Register Pulse Accumulator (PA) Port A Data Direction Register Pulse Accumulator Control Register Timer Interrupt Flag 2 Register Timer Interrupt Mask 2 Register Pulse Accumulator Count Register Real-Time Interrupt (RTI) Timer Interrupt Flag 2 Register Timer Interrupt Mask 2 Register Pulse Accumulator Control Register Pulse-Width Modulator (PWM) PWM System Description Pulse-Width Modulation Control Registers Pulse-Width Modulation Timer Clock Select Register Pulse-Width Modulation Timer Polarity Register Pulse-Width Modulation Timer Prescaler Register Pulse-Width Modulation Timer Enable Register Pulse-Width Modulation Timer Counters 1 to 4 Registers MOTOROLA Table of Contents 13

14 Table of Contents nc Pulse-Width Modulation Timer Periods 1 to 4 Registers Pulse-Width Modulation Timer Duty Cycle 1 to 4 Registers Section 10. Analog-to-Digital (A/D) Converter 10.1 Contents Introduction Functional Description Multiplexer Analog Converter Result Registers Digital Control A/D Control/Status Registers System Configuration Options Register A/D Control/Status Register Analog-to-Digital Converter Result Registers Design Considerations A/D Input Pins Operation in Stop and Wait Modes Section 11. Memory Expansion and Chip Selects 11.1 Contents Introduction Memory Expansion Memory Size and Address Line Allocation Control Registers Port G Assignment Register Memory Mapping Size Register Memory Mapping Window Base Register Memory Mapping Window Control Registers Table of Contents MOTOROLA

15 nc. Table of Contents 11.4 Chip Selects Program Chip Select Input/Output Chip Select General-Purpose Chip Selects Memory Mapping Size Register General-Purpose Chip Select 1 Address Register General-Purpose Chip Select 1 Control Register General-Purpose Chip Select 2 Address Register General-Purpose Chip Select 2 Control Register One Chip Select Driving Another General-Purpose Chip Select 1 Control Register General-Purpose Chip Select 2 Control Register Clock Stretching Memory Expansion Examples Section 12. Electrical Characteristics 12.1 Contents Introduction Maximum Ratings for Standard Devices Functional Operating Range Thermal Characteristics Electrical Characteristics Power Dissipation Characteristics Control Timing Peripheral Port Timing Analog-to-Digital Converter Characteristics Expansion Bus Timing Serial Peripheral Interface Timing EEPROM Characteristics MOTOROLA Table of Contents 15

16 Table of Contents nc. Section 13. Mechanical Data 13.1 Contents Introduction Pin Plastic-Leaded Chip Carrier (Case 780) Pin J-Cerquad (Case 780A) Pin Quad Flat Pack (Case 841B) Pin Low-Profile Quad Flat Pack (Case 917A) Pin Plastic Leaded Chip Carrier (Case 779) Pin J-Cerquad (Case 779A) Section 14. Ordering Information Section 15. Development Support Index 16 Table of Contents MOTOROLA

17 nc. List of Figures Figure Title Page 1-1 M68HC11K4 Family Block Diagram M68HC11KS Family Block Diagram Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad Pin Assignments for M6811K 80-Pin QFP Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad Pin Assignments for M6811KS 80-Pin LQFP External Reset Circuit Common Crystal Connections System Configuration Options 2 (OPT2) LIR Timing MODB/V STBY Connection Programming Model Stacking Operations Register and Control Bit Assignments Highest Priority I-Bit Interrupt and Miscellaneous Register (HPRIO) M68HC11K4 Family Memory Map M68HC11KS2 Family Memory Map RAM and I/O Mapping Register (INIT) System Configuration Register (CONFIG) EEPROM Mapping Register (INIT2) EPROM Programming Control Register (EPROG) EEPROM Programming Control Register (PPROG) Block Protect Register (BPROT) System Configuration Options Register (OPTION) Block Protect Register (BPROT) MOTOROLA List of Figures 17

18 List of Figures nc. Figure Title Page 4-13 System Configuration Register (CONFIG) System Configuration Register (CONFIG) System Configuration Options 2 Register (OPT2) System Configuration Register (CONFIG) System Configuration Options Register (OPTION) Arm/Reset COP Timer Circuitry Register (COPRST) System Configuration Options Register (OPTION) System Configuration Options Register 2 (OPT2) System Configuration Options Register (OPTION) Highest Priority I-Bit Interrupt and Miscellaneous Register (HPRIO) Processing Flow Out of Reset Interrupt Priority Resolution Interrupt Priority Resolution Within SCI System System Configuration Options Register (OPTION) System Configuration Options 3 Register (OPT3) Slow Mode Example for M68HC(7)11KS Devices Only Port A Data Register (PORTA) Port A Data Direction Register (DDRA) Port B Data Register (PORTB) Port B Data Direction Register (DDRB) Port C Data Register (PORTC) Port C Data Direction Register (DDRC) System Configuration Options 2 Register (OPT2) Port D Data Register (PORTD) Port D Data Direction Register (DDRD) Port E Data Register (PORTE) Port F Data Register (PORTF) Port F Data Direction Register (DDRF) Port G Data Register (PORTG) Port G Data Direction Register (DDRG) Port H Data Register (PORTH) Port H Data Direction Register (DDRH) List of Figures MOTOROLA

19 nc. List of Figures Figure Title Page 6-17 Port Pullup Assignment Register (PPAR) System Configuration Register (CONFIG) SCI Data Formats SCI Transmitter Block Diagram SCI Receiver Block Diagram SCI Baud Generator Circuit Diagram SCI Baud Rate Control Register High (SCBDH) SCI Baud Rate Control Register Low (SCBDL) SCI Control Register 1 (SCCR1) SCI Control Register 2 (SCCR2) SCI Status Register 1 (SCSR1) SCI Status Register 2 (SCSR2) SCI Data Register (SCDR) SPI Block Diagram Data Clock Timing Diagram Serial Peripheral Control Register (SPCR) Serial Peripheral Status Register (SPSR) Serial Peripheral Data Register (SPDR) Port D Data Direction Register (DDRD) System Configuration Options 2 Register (OPT2) Timer Clock Divider Chains Capture/Compare Block Diagram Timer Counter Register (TCNT) Timer Interrupt Flag 2 (TFLG2) Timer Interrupt Mask 2 (TMSK2) Port A Data Direction Register (DDRA) Pulse Accumulator Control Register (PACTL) Timer Input Capture Registers (TIC1 TIC3) Timer Input Capture 4/Output Compare 5 Register (TI4/O5) Timer Interrupt Flag 1 Register (TFLG1) Timer Interrupt Mask 1 Register (TMSK1) Timer Control 2 Register (TCTL2) MOTOROLA List of Figures 19

20 List of Figures nc. Figure Title Page 9-13 Timer Output Compare Registers (TOC1 TOC4) Timer Input Capture 4/Output Compare 5 Register (TI4/O5) Timer Interrupt Flag 1 Register (TFLG1) Timer Interrupt Mask 1 Register (TMSK1) Timer Control Register 1 (TCTL1) Timer Compare Force Register (CFORC) Output Compare 1 Mask Register (OC1M) Output Compare 1 Data Register (OC1D) Pulse Accumulator Port A Data Direction Register (DDRA) Pulse Accumulator Control Register (PACTL) Timer Interrupt Flag 2 (TFLG2) Timer Interrupt Mask 2 (TMSK2) Pulse Accumulator Count Register (PACNT) Timer Interrupt Flag 2 Register (TFLG2) Timer Interrupt Mask 2 Register (TMSK2) Pulse Accumulator Control Register (PACTL) Pulse-Width Modulation Timer Block Diagram Pulse-Width Modulation Timer Clock Select (PWCLK) Pulse-Width Modulation Timer Polarity Register (PWPOL) Pulse-Width Modulation Timer Prescaler Register (PWSCAL) Pulse-Width Modulation Timer Enable Register (PWEN) Pulse-Width Modulation Timer Counters 1 to 4 (PWCNT1 to PWCNT4) Pulse-Width Modulation Timer Periods 1 to 4 (PWPER1 to PWPER4) Pulse-Width Modulation Timer Duty Cycle 1 to 4 (PWDTY1 to PWDTY4) A/D Converter Block Diagram A/D Conversion Sequence List of Figures MOTOROLA

21 nc. List of Figures Figure Title Page 10-3 System Configuration Options Register (OPTION) Analog-to-Digital Control/Status Register (ADCTL) Analog-to-Digital Result Registers (ADR1 ADR4)) Electrical Model of an A/D Input Pin (Sample Mode) Port G Assignment Register (PGAR) Memory Mapping Size Register (MMSIZ) Memory Mapping Window Base Register (MMWBR) Memory Mapping Window Control Registers (MM1CR and MM2CR) Chip-Select Control Register (CSCTL) Chip-Select Control Register (CSCTL) Memory Mapping Size Register (MMSIZ) General-Purpose Chip Select 1 Address Register (GPCS1A) General-Purpose Chip Select 1 Control Register (GPCS1C) General-Purpose Chip Select 2 Address Register (GPCS2A) General-Purpose Chip Select 2 Control Register (GPCS2C) General-Purpose Chip Select 1 Control Register (GPCS1C) General-Purpose Chip Select 2 Control Register (GPCS2C) Chip Select Clock Stretch Register (CSCSTR) Memory Expansion Example 1 Memory Map for a Single 8-Kbyte Window with Eight Banks of External Memory Memory Expansion Example 2 Memory Map for One 8-Kbyte Window with Eight Banks and One 16-Kbyte Window with 16 Banks of External Memory Test Methods Timer Inputs MOTOROLA List of Figures 21

22 List of Figures nc. Figure Title Page 12-3 POR External Reset Timing Diagram STOP Recovery Timing Diagram WAIT Recovery from Inerrupt Timing Diagram Interrupt Timing Diagram Port Read Timing Diagram Port Write Timing Diagram Expansion Bus Timing SPI Timing Diagram List of Figures MOTOROLA

23 nc. List of Tables Table Title Page 1-1 Devices I/O Ports and Peripheral Functions Port Signal Summary Instruction Set Registers with Limited Write Access Synchronization Character Selection Hardware Mode Select Summary Default Memory Map Addresses RAM Mapping Register Mapping EEPROM Map Scope of EEPROM Erase EEPROM Block Protect XOUT Frequencies Reset Vectors COP Timeout IRVNE Operation After Reset XOUT Clock Divide Select Interrupt and Reset Vector Assignments Stacking Order on Entry to Interrupts Highest Priority Interrupt Selection Port Configuration MOTOROLA List of Tables 23

24 List of Tables nc. Table Title Page 7-1 SCI Receiver Flags SCI+ Baud Rates SPI+ Baud Rates Main Timer Rates Timer Prescale Input Capture Edge Selection Timer Output Compare Actions Pulse Accumulator Timing Pulse Accumulator Edge Control Real-Time Interrupt Rate versus RTR[1:0] Clock A Prescaler Clock B Prescaler A/D Converter Channel Selection CPU Address and Address Expansion Signals Window Size Select Memory Expansion Window Base Address Chip Select Control Parameter Summary Program Chip Select Size General-Purpose Chip Select 1 Size Control General-Purpose Chip Select 2 Size Control One Chip Select Driving Another CSCSTR Bits Versus Clock Cycles Devices List of Tables MOTOROLA

25 nc. Section 1. General Description 1.1 Contents 1.2 Introduction Introduction 1.3 Members Features Structure The of high-performance microcontroller units (MCUs) offers a non-multiplexed expanded bus, high speed and low power consumption. The fully static design allows operation at frequencies from dc to 4 MHz. This manual contains information concerning standard and custom-rom (read-only memory) devices. Standard devices include those replacing the ROM with: Disabled ROM Disabled EEPROM (electrically erasable, programmable read-only memory) EPROM (erasable, programmable read-only memory) OTPROM (one-time progammable read-only memory) Custom-ROM devices have a ROM array that is programmed at the factory to customer specifications. MOTOROLA General Description 25

26 General Description nc. 1.3 Members devices feature up to 62 input/output (I/O) lines distributed among eight ports, A through H. The KS Family removes seven pins from port G and four pins from port H for a total of 51 I/O lines. The KSx versions feature a slow mode for the clocks to allow power conservation. Table 1-1 lists devices currently available in the K Family along with their distinguishing features. Device Number MC68HC(L)11K0 MC68HC(L)11K1 MC68HC(L)11K4 NOTE: ROM or EPROM (Bytes) (1) K The KA2 and KA4 devices have been replaced by the pin-for-pin compatible KS2. Table 1-1. Devices RAM (Bytes) EEPROM (Bytes) I/O (Pins) Chip Select Yes Yes Yes Slow Mode MC68HC711K4 24 K Yes No No No No 84-pin PLCC (2) 80-pin QFP (3) Packages 84-pin J-cerquad (4) 84-pin PLCC 80-pin QFP MC68HC11KS2 32 K 1 K No Yes 68-pin PLCC and 80-pin LQFP (5) MC68HC711KS2 32 K 1 K No Yes 1. Where applicable, EPROM bytes appear in italics. 2. PLCC = Plastic leaded chip carrier 3. QFP = Quad flat pack 4. J-cerquad = Ceramic windowed version of PLCC 5. LQFP = Low-profile quad flat pack 68-pin J-cerquad, 68-pin PLCC, and 80-pin LQFP 26 General Description MOTOROLA

27 nc. General Description Features 1.4 Features features include: 8-bit opcodes and data 16-bit addressing Two 8-bit accumulators, which can be concatenated to form one 16-bit accumulator On-board memory: 24 Kbytes or 32 Kbytes of ROM, EPROM, or OTPROM 768 bytes or 1 Kbyte of static RAM (random-access memory) 640 bytes of EEPROM 128-byte register block Dual-function I/O lines Any pins used for the microcontroller s peripheral functions can be configured as general-purpose I/O lines. Non-multiplexed address and data buses 68HC11K4 offers: 1 Mbyte of address space, using on-chip memory mapping logic Four programmable chip selects (expanded modes) 16-bit timer system: Three input capture (IC) channels, record event timing by storing the value of the timing system s 16-bit free-running counter when an input signal transition occurs. Four output compare (OC) channels, provide timed outputs by signaling when the free-running counter reaches a predetermined number. One IC or OC channel (software selectable) 8-bit pulse accumulator Four 8-bit pulse-width modulation (PWM) outputs Enhanced asynchronous serial communications interface (SCI) MOTOROLA General Description 27

28 General Description nc. Enhanced synchronous serial peripheral interface (SPI) 8-channel, 8-bit, analog-to-digital (A/D) converter Computer operating properly (COP) watchdog system to guard against infinite loops and other system problems Real-time interrupt timer Power-saving modes: Slow mode reduces power consumption by slowing down internal operations. Wait mode shuts down various system features selected by the user with power consumption typically dropping to mw. Stop mode also shuts down system clocks, typically reducing power consumption to about 1.5 mw. Package availability for ROM devices: K versions: 84-pin plastic leaded chip carrier (PLCC) 80-pin quad flat pack (QFP) KS versions: 68-pin plastic leaded chip carrier (PLCC) 80-pin low-profile quad flat pack (LQFP) Package availability for EPROM devices: K versions: 80-pin quad flat pack (QFP) 84-pin J-cerquad (ceramic windowed version of PLCC) 84-pin plastic leaded chip carrier (PLCC) KS versions: 68-pin J-cerquad (ceramic windowed version of PLCC) 80-pin low-profile quad flat pack (LQFP) 68-pin plastic leaded chip carrier (PLCC) 28 General Description MOTOROLA

29 nc. General Description Structure 1.5 Structure Figure 1-1 is a block diagram of the MCU. Figure 1-2 is a block diagram of the M68HC11KS devices. RESET MODA/ LIR MODB/ V STBY EXTAL XTAL E XOUT (1) V RH V RL AV DD AV SS IRQ (2) XIRQ/V PP PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 V DD V SS INTERRUPT LOGIC PORT A DDRA MODE CONTROL PAI/OC1 CPU OSCILLATOR PULSE ACCUMULATOR CLOCK LOGIC DDRC COP PERIODIC INTERRUPT 24 KBYTES ROM/EPROM 768 BYTES RAM ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB OC2/OC1 OC3/OC1 OC4/OC1 IC4/OC5/OC1 IC1 IC2 IC3 ADDRESS BUS ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DDRF TIMER SYSTEM DATA BUS R/W DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 A/D CONVERTER SPI SCI DDRG SS SCK MOSI MISO TxD RxD MEMORY EXPANSION XA18 XA17 XA16 XA15 XA14 XA13 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DDRD 640 BYTES EEPROM CHIP SELECTS PORT D PORT E DDRH PWMs PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PD5 PD4 PD3 PD2 PD1 PD0 PORT B PORT F PORT C PORT G PORT H PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CSPROG CSGP2 CSGP1 CSIO PW4 PW3 PW2 PW1 Notes: 1. XOUT pin omitted on 80-pin QFP 2. V PP applies only to EPROM devices. Figure 1-1. M68HC11K4 Family Block Diagram MOTOROLA General Description 29

30 General Description nc. RESET MODA/ LIR MODB/ V STBY EXTAL XTAL E XOUT V RH V RL AV DD AV SS IRQ XIRQ/V PP (2) PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 V DD V SS PORT A INTERRUPT LOGIC DDRA MODE CONTROL PAI/OC1 OC2/OC1 OC3/OC1 OC4/OC1 IC4/OC5/OC1 IC1 IC2 IC3 MC68HC11KS2 32 KBYTES ROM/EPROM ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DDRB PORT B PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDRESS BUS OSCILLATOR WITH SLOW MODE CPU ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DDRF PORT F PULSE ACCUMULATOR TIMER SYSTEM PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 CLOCK LOGIC DDRC PORT C COP PERIODIC INTERRUPT MC68HC11KS2 1 KBYTES RAM DATA BUS R/W DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PG7 SPI SCI A/D CONVERTER DDRG PORT G SS SCK MOSI MISO TxD RxD AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DDRD PORT D PORT E 640 BYTES EEPROM PWMs DDRH PORT H PW4 PW3 PW2 PW1 PH3 PH2 PH1 PH0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PD5 PD4 PD3 PD2 PD1 PD0 Notes: 1. The configuration shown in this diagram is the MC68HC11KS2. 2. V PP applies only to EPROM devices. Figure 1-2. M68HC11KS Family Block Diagram 30 General Description MOTOROLA

31 nc. Section 2. Pin Description 2.1 Contents 2.2 Introduction Introduction 2.3 Power Supply (V DD, V SS, AV DD, and AV SS ) Reset (RESET) Crystal Driver and External Clock Input (XTAL and EXTAL) XOUT E-Clock Output (E) Interrupt Request (IRQ) and Non-Maskable Interrupt (XIRQ) Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/V STBY ) V RH and V RL Port Signals The is available in a variety of packages, as shown in Table 1-1. Devices. Most pins on this MCU serve two or more functions, as described in this section. Pin assignments for the various package types are shown in Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4. MOTOROLA Pin Description 31

32 Pin Description nc. PB0/ADDR8 PB1ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 V SS V DD PA0/IC3 PA1/IC2 PA2/IC1 PA3/IC4/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 PD5/SS PD4/SCK PD3/MOSI PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4 PH4/CSIO PH5/CSGP1 PH6/CSGP2 PH7/CSPROG TEST16 (1) (2) XIRQ/V PP TEST15 (1) V DD V SS TEST14 (1) PG7/R/W PG6 PG5/XA18 PG4/XA17 PG3/XA16 PG2/XA15 PG1/XA PD2/MISO Figure 2-1. Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad PG0/XA13 AV DD PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 V RL V RH AV SS PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 PF1/ADDR1 PF0/ADDR PD1/T X D PD0/R X D MODA/LIR MODB/V STBY RESET XTAL EXTAL XOUT E V DD V SS PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 Notes: 1. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry. 2. V PP applies only to EPROM devices. IRQ 32 Pin Description MOTOROLA

33 nc. Pin Description Introduction PD2/MISO PD1/TXD PD0/RXD MODA/LIR MODB/V STBY RESET XTAL EXTAL E V DD V SS PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 IRQ PD3/MOSI 1 PD4/SCK 2 PD5/SS 3 PA7/PAI/OC1 4 PA6/OC2/OC1 5 PA5/OC3/OC1 6 PA4/OC4/OC1 7 PA3/IC4/OC5/OC1 8 PA2/IC1 9 PA1/IC2 10 PA0/IC3 11 V DD 12 V SS 13 PB7/ADDR15 14 PB6/ADDR14 15 PB5/ADDR13 16 PB4/ADDR12 17 PB3/ADDR11 18 PB2/ADDR10 19 PB1/ADDR PB0/ADDR8 21 PH0/PW1 22 PH1/PW2 23 PH2/PW3 24 PH3/PW4 25 PH4/CSIO 26 PH5/CSGP1 27 PH6/CSGP2 28 PH7/CSPROG 29 * XIRQ/V PP 30 V DD 31 V SS 32 PG7/R/W 33 PG6 34 PG5/XA18 35 PG4/XA17 36 PG3/XA16 37 PG2/XA15 38 PG1/XA14 39 PG0/XA13 40 * V PP applies only to EPROM devices. Figure 2-2. Pin Assignments for M6811K 80-Pin QFP PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 AV SS V RH V RL PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 AV DD MOTOROLA Pin Description 33

34 Pin Description nc. PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4 XIRQ/V PP * PG7/R/W IRQ AV DD PE7/AN PA0/IC3 9 PA1/IC2 8 PA2/IC1 7 PA3/IC4/OC5/OC1 6 PA4/OC4/OC1 5 PA5/OC3/OC1 4 PA6/OC2/OC1 3 PA7/PAI/OC1 2 V DD 1 68 V DD 67 V SS PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 V RL V RH AV SS V SS PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 * V PP applies only to EPROM devices. MODA/LIR MODB/V STBY RESET XTAL Figure 2-3. Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad PD5/SS 66 PD4/SCK 65 PD3/MOSI 64 PD2/MISO 63 PD1/TXD 62 PD0/RXD EXTAL XOUT E PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1 34 Pin Description MOTOROLA

35 nc. Pin Description Introduction NC NC MODA/LIR MODB/V STBY RESET XTAL EXTAL XOUT E NC PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1 PD0/RXD 1 80 PD1/TXD 2 PD2/MISO 3 PD3/MOSI 4 PD4/SCK 5 PD5/SS 6 NC 7 V SS 8 NC 9 V DD 10 NC 11 V DD 12 PA7/PAI/OC1 13 PA6/OC2/OC1 14 PA5/OC3/OC1 15 PA4/OC4/OC1 16 PA3/IC4/OC5/OC1 17 PA2/IC1 18 PA1/IC2 19 PA0/IC3 20 PB7/ADDR * V PP applies only to EPROM devices PB6/ADDR14 22 PB5/ADDR13 23 PB4/ADDR12 24 PB3/ADDR11 25 PB2/ADDR10 26 PB1/ADDR9 27 PB0/ADDR8 28 PH0/PW1 29 PH1/PW2 30 PH2/PW3 31 PH3/PW4 32 XIRQ/V PP * 33 NC 34 NC 35 PG7/R/W 36 IRQ 37 AV DD 38 PE7/AN7 39 NC 40 Figure 2-4. Pin Assignments for M6811KS 80-Pin LQFP PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 V SS AV SS V RH NC V RL NC PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 NC MOTOROLA Pin Description 35

36 Pin Description nc. 2.3 Power Supply (V DD, V SS, AV DD, and AV SS ) The MCU operates from a single 5-volt (nominal) power supply. V DD is the positive power input and V SS is ground. There are three V DD /V SS pairs of pins on the K series devices and two sets on the KS devices. All devices contain a separate pair of power inputs, AV DD and AV SS, for the analog-to-digital (A/D) converter, so that the A/D circuitry can be bypassed independently. 2.4 Reset (RESET) Very fast signal transitions occur on the MCU pins. The short rise and fall times place high, short duration current demands on the power supply. To prevent noise problems, provide good power supply bypassing at the MCU. Also, use bypass capacitors that have good high-frequency characteristics and situate them as close to the MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. This active-low, bidirectional control signal acts as an input to initialize the MCU to a known start-up state. It also serves as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit. The CPU distinguishes between internal and external reset conditions by counting the number of E-clock cycles that occur between the start of reset and the presence of a logic 1 voltage level on the reset pin. Less than two cycles indicates an internal reset; greater than two, an external reset. To prevent the device from misinterpreting the kind of reset that occurs, do not connect an external resistor-capacitor (RC) power-up delay circuit directly to the reset pin. 36 Pin Description MOTOROLA

37 nc. Pin Description Crystal Driver and External Clock Input (XTAL and EXTAL) V DD V DD V DD IN 4.7 kω MANUAL RESET SWITCH 4.7 kω 4.7 kω MC34064 RESET GND TO RESET OF M68HC µω IN MC34164 RESET Figure 2-5. External Reset Circuit It is important to protect the MCU against corruption of RAM and EEPROM during power transitions. This can be done with a low-voltage interrupt (LVI) circuit which holds the RESET pin low when V DD drops below the minimum operating level. Figure 2-5 shows a suggested reset circuit that incorporates two LVI devices and an external switch. 2.5 Crystal Driver and External Clock Input (XTAL and EXTAL) GND OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH These two pins provide the interface for either a crystal or a CMOS-compatible clock to control the internal clock generator circuitry. The frequency applied to these pins is four times higher than the desired E-clock rate. When an external CMOS-compatible clock input is connected to the EXTAL pin, the XTAL pin must be left unterminated. CAUTION: In all cases, use caution around the oscillator pins. Load capacitances shown in Figure 2-6 are specified by the crystal manufacturer and should include all stray layout capacitances. MOTOROLA Pin Description 37

38 Pin Description nc. C L * EXTAL MCU 10 MΩ 4 x E CRYSTAL C L * XTAL * This value includes all stray capacitances. Figure 2-6. Common Crystal Connections 2.6 XOUT NOTE: 2.7 E-Clock Output (E) The XOUT pin provides a buffered clock signal if enabled to synchronize external devices with the MCU. See 4.9 XOUT Pin Control. This signal is not present on the 80-pin M68HC(7)11K device QFP package. The internally generated instruction cycle clock, or E clock, is available on the E pin as a timing reference. Its frequency is one fourth the input frequency at the XTAL and EXTAL pins. The E clock is low during the address portion of a bus cycle and high during the data access portion of the bus cycle. All clocks, including the E clock, are halted when the MCU is in stop mode. The E-pin driver can be turned off in single-chip modes to reduce radio frequency interference (RFI) and current consumption. 2.8 Interrupt Request (IRQ) and Non-Maskable Interrupt (XIRQ) The MCU provides two pins for applying asynchronous interrupt requests. Interrupts applied to the IRQ pin can be masked by setting the I bit in the condition code register (CCR), which can be set or cleared by software at any time. Triggering is level sensitive by default, which is 38 Pin Description MOTOROLA

39 nc. Pin Description Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/VSTBY) required for wire-or configuration. Software can change the triggering to edge sensitive. XIRQ interrupts can be non-maskable after reset initialization. Out of reset, the X bit in the CCR is set, masking XIRQ interrupts. Once software clears the X bit, it cannot be reset, and the XIRQ interrupts become non-maskable. The XIRQ input is level sensitive only. XIRQ is often used as a power-loss detect interrupt. CAUTION: Whenever IRQ or XIRQ is used with multiple interrupt sources, each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. There should be a single pullup resistor near the MCU interrupt pin (typically 4.7 kω). There must also be an interlock mechanism at each interrupt source which holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If any interrupt sources are still pending after the MCU services a request, the interrupt line will remain low, interrupting the MCU again as soon as the I bit in the MCU is cleared (normally upon return from an interrupt). Interrupt mechanisms are explained further in Section 5. Resets and Interrupts. On EPROM devices, the XIRQ pin also functions as the high-voltage supply, V PP, during EPROM or OTPROM programming. Ensure that the voltage level at this pin is equal to V DD during normal operation to avoid programming accidents. 2.9 Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/V STBY ) During reset, MODA and MODB select one of four operating modes: 1. Single-chip 2. Expanded 3. Bootstrap 4. Special test For full descriptions of these modes, refer to 4.5 Operating Modes. MOTOROLA Pin Description 39