Programmable Logic Devices

Transcription

1 EG igital Logic Fundamentals /4/6 EG igital Logic Fundamentals Programmable Logic evices aback Izadi ivision of Engineering Programs Introduction Fuse Link E = blown fuse link E = F = + esign of ombinational Logic

2 EG igital Logic Fundamentals /4/6 asic PLs Programmable N block followed by a programmable OR block Programmable rray lock iagram for Sum of Products Form Inputs ense array of N gates Product terms ense array of OR gates Outputs asic PLs ll possible connections are available before programming esign of ombinational Logic

3 EG igital Logic Fundamentals /4/6 Programming a PL Unwanted connections are "blown" Short-hand notation so we don't have to draw all the wires! 3 = (, ) Y = (3) Z = (, 3) W = (,, ) Y Z W Y Z W Programmable onnection Fixed onnection lternative representation of PLs: PLE Fixed N array Programmable OR array What if you have lots of inputs? Programmable onnection Fixed onnection Y Z W esign of ombinational Logic 3

4 EG igital Logic Fundamentals /4/6 lternative representation of PLs: PL Programmable N array Fixed OR array given column of the OR array has access to only a subset of the possible product terms Programmable onnection Fixed onnection F = + F = + F F PLs with Four Product terms omplete the following: F = F = F3 = F4 = F F F3 F4 esign of ombinational Logic 4

5 EG igital Logic Fundamentals /4/6 lternative representation of PLs: PL Programmable N array Programmable OR array Programmable onnection Fixed onnection F = + ' ' F = ' + ' F F esign Example using PL Multiple functions of,, F = F = + + F3 = F4 = + + F5 = F6 = What is difference between Programmable rray Logic (PL) and Programmable Logic rray (PL)? F F F3 F4 F5 F6 esign of ombinational Logic 5

6 EG igital Logic Fundamentals /4/6 esign Example: to Gray ode onverter Truth Table W Minimized Functions: Y Z K-map for W K-maps K-map for W = + + = ' Y = + Z = ''' + + ' + ' ' K-map for Y K-map for Z ode onverter iscrete Gate Implementation Using SSI \ \ 3 W \ \ \ 3 5 \ \ 3 \ Z \ Y : 744 hex inverters,5: 74 quad -input NN 3: 74 t ri 3-input NN 4: 74 dual 4-input NN 4 SSI Packages vs. PL/PL Package! esign of ombinational Logic 6

7 EG igital Logic Fundamentals /4/6 nother Example: Magnitude omparator K-map for EQ K-map for NE K-map for L T K-map for GT EQ NE LT GT Key dvantage of PL: Shared Product Terms Example: F = + ' ' F = ' + F = ' ' + F3 = ' + Product t erm Personality Matrix Inputs Outputs F F F F 3 Reuse of t erms Input Side: = asserted in term = negated in term - = does not participate Output Side: = term connected to output = no connection to output Finding shared product term not that easy for large design. esign of ombinational Logic 7

8 EG igital Logic Fundamentals /4/6 ombinational Logic to 7 Segment isplay ontroller Problems PL Implementation ctual PL evice 6H8PL: 6 inputs 8 outputs First fuse numbers Increment Note: Fuse number = first fuse number + increment esign of ombinational Logic 8

9 EG igital Logic Fundamentals /4/6 to 7 Segment isplay ontroller on 6H8PL Increment First fuse numbers Note: Fuse number = first fuse number + increment What about FPG? Has millions of programmable gates organized into Logic locks Logic locks are interconnected using programmable switches. esign of ombinational Logic 9

10 EG igital Logic Fundamentals /4/6 What about FPG? Programmable interconnects using switch matrixes Several types of interconnects: short distance (local), long distances across chip, FPG s provide enormous design capabilities. esign of ombinational Logic