The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules.

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1 Page 1 of 5 CADENCE TUTORIAL Creating Layout of an inverter: click on File->library->new a Create Library form appears, fill it as follows: in the name field enter: inverter select "Attach to existing tech library." chose the library from the list. It should be: TSMC 0.4u CMOS035 (4M, sblock, HV FET) click on OK You should see this new library being added to the Library Manager window. click on File->new->cellview a Create New File form appears, handle it as follows: for library name select inverter, the library you just created in the cell name field type: my_inv for view name select Virtuoso, the last item in pulldown menu below the text field. click OK The Virtuoso Layout Editing window comes up The first thing to do is to click on the Technology File item on the icfb - Log window. Technology File->Attach To... a Attach Design Library to Tech File form appears. Handle it as follows; In the Design Library field select inverter. This is the library you created click on Browse and a Library Browser form appears, highlight the word inverter in the leftmost field under the Library heading. Under the Cell and View headings highlight my_inv and layout. close the browser window and return to the Attach Design Library to Tech File form. Corresponding to the Cell and View fields you should now see the text my_inv and layout respectively. Include check marks against both the Cell and View labels. Against the Technology Library field select: TSMC 0.4u CMOS035 (4M, sblock, HV FET) click OK and the icfb - Log window should have: Attach successfully completed. Now we can start the layout of our inverter. The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules. *****WARNING***** save your work after every outlined step The Virtuoso Layout window is accompanied by the LSW window (contains the material layers). In the Virtuoso Layout window pull down the options menu and select Display... e The Display Options form appears fill it out as follows:

2 Page 2 of 5 Minor Spacing 1 Major Spacing 5 X Snap Spacing 0.1 Y Snap Spacing 0.1 click OK You will have to make sure that these settings are like this every time you run Virtuoso. This is true only for TSMC s 0.35 micron Technology. Again pulldown the options munu and select Layout Editor... E The Layout Editor Options form appears, deselect the Gravity On option and click OK. This will allow you to select any co-ordinates on your layout without gravitating to specific co-ordinates. Drawing the principal layers: select the pactive dg layer in the LSW window with the cursor in the Virtuoso Layout window type the letter r and move the cursor to any where in the first quadrant. (see Table 1 for coodinates) Left click at the chosen position to mark the lower left corner of you pactive rectangle. Draw a rectangle that is 2.6 X 2.0 lambda (the first value being dx and the second value being dy) Watch the values dx and dy at the top of the window to monitor the size of your rectangles. select the pselect dg layer in the LSW window type r in the layout window and draw a rectange that is 3.4 X 2.8 lambda. Move the pactive rectangle, (the 2.6 X 2.0 rectangle) inside this pselect rectangle such that its edges are 0.4 lambda from the edges of the pselect. (refer to Table 1) select the nwell dg layer from the LSW window. type r and then draw a rectangle that is 5.0 X 6.0 lambda. Move this layer over the first two layers such that it overlaps the outermost layer (pselect) by 0.8 lambda from the bottom and sides. It must overlap the top edge of the pselect by 2.4 lambda. select the nactive layer (nactive dg in LSW window). In Virtuoso Layout window, draw a 2.6 X 1.0 lambda rectangle. Move it to a location 1.2 lambda below the nwell rectangle and Align it with the pactive rectangle (the very first rectangle you made, refer to Table 1). select the nselect dg layer in LSW window. make a 3.4 X 1.8 rectangle that overlaps the nactive layer by 0.4 lambda on all sides/edges. This layer must be 0.8 lambda from the nwell layer. Drawing contacts: select the cc dg layer from the LSW window. make a 0.4 X 0.4 lambda rectangle and place it on the pactive layer, 0.3 lambda from its lower and left edges. make another 0.4 X 0.4 lambda rectangle and place it 0.6 lambda above the first one. This one will be 0.3 lambda from the left and upper edges. REPEAT THIS PROCESS ON THE RIGHT END OF THE pactive. select the cc dg layer from the LSW window. make a 0.4 X 0.4 lambda rectangle and place it on the nactive layer, 0.3 lambda from its lower and left edges. REPEAT THIS PROCESS ON THE RIGHT END OF THE nactive. Drawing Poly: select poly dg from the LSW window. make a 0.4 X 6.20 lambda rectangle and place it 0.4 lambda from the left and right hand side contacts you placed on the nactive and pactive layers. Make sure the poly layer overlaps the nactive and pactive layers by 0.4 lambda. Connecting the Drains on the p- and n- transistors:

3 Page 3 of 5 select metal1 dg from the LSW window. make a 0.9 X 5.4 lambda rectangle and place it over the contacts of both the n- and p-transistors. The contacts in question are those to the right of the poly layer. Creating contacts to the wells (nwell and pwell) select nactive dg from LSW window. Draw a 0.8 X 0.8 lambda rectangle and place it 0.8 lambda above the pactive layer, make sure that its lower left corner is aligned with the top left corner of the pactive layer. select cc dg from the LSW window. draw a 0.4 X 0.4 lambda rectangle inside the nactive layer you just completed and make sure that the nactive layer overlaps this contact by 0.2 lambda on all edges. select the nselect dg layer from the LSW window. Draw a 1.6 X 1.6 lambda rectangle and place it over the nactive layer you just completed. Align this layer (nselect) such that its lower left corner is at the same point as the upper left corner of the pselect of the p- transistor. When you are done this nselect layer must overlap the nactive layer by 0.4 lambda on all edges. select pactive dg from LSW window. make a 0.8 X 0.8 lambda rectangle and place it 0.8 lambda below the nactive layer of the n-transitor, such that its top left corner is aligned with the lower left corner of the nactive of the n-transistor. select cc dg from the LSW window make a 0.4 X 0.4 lambda rectangle and place it inside the pactive layer you just made. The pactive layer must overlap this contact by 0.2 lambda on all edges. select the pselect dg layer from the LSW window. Draw a 1.6 X 1.6 lambda rectangle and place it over the pactive layer you just completed. Align this layer (pselect) such that its upper left corner is at the same point as the lower left corner of the nselect of the n- transistor. When you are done this pselect layer must overlap the pactive layer by 0.4 lambda on all edges. Connect the well contacts to the Sources of the transistors: select metal1 dg from LSW window Draw a 0.9 X 3.20 lambda rectangle and place it over the contacts of the p-transistor such that its lower edge is aligned to the lower edge of the p-transistor, while its upper edge is aligned with the top edge of the nactive layer of the nwell contact. Draw a 3.4 X 0.8 lambda metal1 layer and place it such that it extends 0.4 lambda to the left of the 0.8 X 0.8 nactive placed above the p-transistor. Draw a 0.9 X 1.8 rectangle and place it over the left contact of the n-transistor and the pwell (implied) contact. Draw a 3.4 X 0.8 lambda metal1 layer and place it such that it extends 0.4 lambda to the left of the 0.8 X 0.8 pactive material placed below the n-transistor. You must now have a structure that looks like this: Labeling inputs, outputs and other signals of interest: From the Virtuoso editing window: select create from the menu. from the list of items select pin a create symbolic pin form appears. In the Terminal Names field enter the following labels: in out Vdd gnd for Mode select sym pin (if it is not already selected). select Display Pin Name, for I/O Type select input and chose poly for Pin Type. Now move the cursor to the Virtuoso window, you will find that it now carries a 0.4 X 0.4 lambda poly layer. Place it at the mid point of the 0.4 X 6.20 lambda poly material of the inverter. Click once places the poly layer and a second click of the left mouse button ensures that the label is attached to the layer. Go to the Create Symbolic Pin form and change I/O Type to output and the Pin Type to metal1.

4 Page 4 of 5 Move the cursor back to the Virtuoso editor and place this layer at the center of the metal1 layer that connects the transistor Drains (the layer measuring 0.9 X 5.4 lambda). Click once to place the layer and one more time to attach the label. Go to the Create Symbolic Pin form and change I/O Type to input. Back on the Virtuoso editing window place this layer at the center of the 3.4 X 0.8 lambda metal1 layer above the p-type transistor. Click once to place the layer and for the second time to attach the Vdd label. Repeat the above procedure to attach the gnd label on the 3.4 X 0.8 metal1 layer below the n-type tansistor. The layout is now complete, but we have to make sure that it has no design rule errors. From the Virtuoso pulldown menu select Verify->DRC... A DRC form appears, make sure Checking Method is flat and Checking Limit is full, with the Machine being local. Click on OK and watch the icfb - Log window for messages. If design rule checking occurs successfully you will get a message indicating thus otherwise you will get error messages stating what design rules you violated. If there are errors in the layout go back to the Virtuoso editor to correct them and run DRC again. If DRC successfully executes, go to Verify->extract The Extractor form appears, set Extract Method to flat, click on the Set Switches button and select Extract_psitic_caps, click OK. The rest of the information in this window should be correct by default. Click OK This will produce skeletal layout showing electrical connectivity and it is on this skeletal layout that we will perform simulations. Save your layout and close the window. Table 1 Layer Dimensions (x,y values) Lower corner cordinates pactive 2.60 X 2.0 (3.2,5.0) pselect 3.40 X 2.80 (2.8,4.6) nwell 5.00 X 6.00 (2.0,3.8) contact (cc dg) 0.40 X 0.40 (3.4, 8.0) nactive 0.80 X 0.80 (3.2,7.8) nselect 1.60 X 1.60 (2.8,7.4) nactive X 1.00 (3.2,1.6) nselect X 1.80 (2.8,1.2) contact (cc dg) 0.40 X 0.40 (3.4,0.2) pactive 0.80 X 0.80 (3.2,0.0) pselect 1.60 X 1.60 (2.8,-0.4) metal X 0.80 (2.8,0.0) metal X 1.80 (3.2,0.8) metal1 0.9 X 5.40 (4.9,1.6) metal1 0.9 X 2.80 (3.2,5.0) metal1 3.4 X 0.80 (2.8,7.8) contact (cc dg) 0.40 X 0.40 (3.5,1.9) contact (cc dg) 0.40 X 0.40 (5.1,1.9) contact (cc dg) 0.40 X 0.40 (3.5,5.3) contact (cc dg) 0.40 X 0.40 (5.1,5.3) contact (cc dg) 0.40 X 0.40 (3.5,6.3)

5 Page 5 of 5 contact (cc dg) 0.40 X 0.40 (5.1,6.3) poly 0.40 X 6.20 (4.3,1.2) From the icfb - Log window click on File->Open... and the Open File form appears. Fill it out as follows: For Library Name select inverter Under Cell Names select the cell name, for this tutorial it is my_inv this name should appear in the field against the Cell Name label. In the View Name field select extracted if this is not already set by default. select edit for Mode and click OK. A Virtuoso Layout Editing window should appear loaded with the extracted version of the design (inverter). Follow the simulation instructions to perform simulations on the inverter. The End.