TRANSISTOR-LEVEL ROUTING WITH IC CRAFTSMAN & VIRTUOSO USING A LOCAL INTERCONNECT

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1 TRANSISTOR-LEVEL ROUTING WITH IC CRAFTSMAN & VIRTUOSO USING A LOCAL INTERCONNECT TONY LAUNDRIE IC DESIGN ENGINEER P.O. BOX 4000 CHIPPEWA FALLS, WI atl@sgi.com INTERNATIONAL CADENCE USER GROUP CONFERENCE SEPTEMBER 12-16, 1999 ORLANDO, FLORIDA

2 1. Introduction A recent SGI project involved laying out dozens of custom standard cells. To simplify building the cell library, Cadence IC Craftsman was considered for automatic transistor-level routing within each cell. The IC fab technology chosen for the project has a local interconnect or METAL-0 layer which can be drawn to connect diffusion and polysilicon shapes without the need for additional contacts or METAL-1. As a result, most of the routing in a cell is done on METAL-0 and POLY, leaving METAL-1 free except for cell I/O pins. Most transistors in our standard cells are relatively large and often consist of multiple devices wired in parallel. IC Craftsman typically expects transistor devices to have metal pins, and any parallel source/drain pieces are expected to be connected ahead of time. This would have been too restrictive for our cells, causing unnecessary blockages. Our goal was to let the router decide for itself where to place contacts along wide transistors, and how to connect parallel pieces in order to minimize the amount of METAL-1 wiring. We encountered some difficulties along the way, especially concerning the mixture of strong connect and must connect pin shapes on a single device, but eventually we got IC Craftsman close to our goal. This paper describes how we set up our various parameterized cells and contacts in Virtuoso, and our rule deck and initial icc.do file in IC Craftsman to accomplish the task of routing with a local interconnect layer. 2. Technology A simplified cross-section of the technology looks like this: MET1 MET1 SIDE VIEW CONT CONT CONT POLY SUBSTRATE When (metal 0) touches (diffusion) or POLY (polysilicon), a connection is made. CONT (contact) shapes are used to connect MET1 down to. A transistor is formed when POLY crosses. is not allowed over transistors. CONT shapes are a fixed square size. must be a path with a fixed width. The connection from a path to a POLY or shape can be made in a variety of legal ways. If there is plenty of overlap, a smaller common area is needed than if there is no overlap, as seen above and below. W W TOP VIEW Y Y X X The legal connections are defined by a table of allowable combinations of the dimensions X, Y, and W shown above. Writing DRC (Design Rule Check) rules for all these combinations is challenging. IC Craftsman provides a pseudo-contact ability to recognize connections involving a local interconnect, but it is not able to generate connections like this during automatic routing by merely overlapping paths. IC Craftsman must be given a set of predrawn contacts. Instead of drawing numerous combinations of all the XYW possibilities, we found that IC Craftsman was less confused and produced better results when given a limited subset. The contacts we used with IC Craftsman for connections are shown below. For IC Craftsman alone, it is

3 sufficient to simply draw layout views of these contacts. If these contacts were needed as symbolic views for some other Cadence tool, they could also be defined in the rulecontactdevice() section of a technology file, using any unused Cadence layer for the middle connecting layer. For both the _ and POLY_ contact, two identically-sized rectangles were drawn, overlapping each other. The dimensions were chosen to be the minimum _ POLY MET1 M0 underneath exactly M0 POLY underneath exactly CONT M1 sizes that satisfy most DRC rules. The exception is that the minimum area requirement of each layer is not necessarily satisfied by each contact. This is usually no problem after the contacts are connected to other shapes. In the few places where DRC showed minimum area violations after running IC Craftsman, it was painless in our cells to extend the contact shapes within Virtuoso to remove the errors. IC Craftsman is able to rotate contacts, so it is not necessary to define both vertical and horizontal orientations. An additional style of contact that might be suitable to define in other local interconnect technologies are ones with a plus shape, like the one below. This kind of symbolic contact works OK for Virtuoso path stitching, and the overall height can be made less than the corresponding rectangular contact, but IC Craftsman wasn t able to use this type of contact in our cells effectively. 3. Example A schematic for a typical NAND2 cell is shown below on the left. The initial layout is shown on the right. The VDD! M0 B A Z A N1 VDD CELLBOX height = 1 width = 5 GND GND! schematic includes a device called CELLBOX, which is used in the layout view to provide a standard cell frame around the final design, and to establish connectivity between the CELLBOX s MET1/ power bus pins and the VDD/GND nets inside the cell. The dashed squares inside the CELLBOX are used to visually align I/O pins on the routing grid.

The initial layout could have been created with Cadence DLE, but we use Skill routines instead.

4 The transistors and the CELLBOX are instances of Pcells (parameterized cells). For the CELLBOX, the height parameter indicates the number of standard cell rows and the width is the number of routing tracks. The initial layout could have been created with Cadence DLE, but we use Skill routines instead. One of the functions of our initializing routine is to automatically set the number of parallel fingers for wide transistors so that they fit within the predefined NWELL and PWELL regions of the CELLBOX. In this example, the larger transistors have two fingers each. By default, the separate gates and source/drain regions of multi-finger transistors are not connected together with shapes in the Pcell Skill code. As can be seen in the layout, the transistor Pcells draw shapes on short devices, but not on long ones. The technology rulebook advises users not to run along the full width of wide transistors, as it decreases yield and is unnecessary, so is drawn only on the smaller transistors. A parameter can turn off the where necessary, like when abutting separate transistors, but is drawn by default because the somewhat complicated XYW DRC rules come into play, and it is easier for most layout designers and IC Craftsman to have those connection rules satisfied automatically. Before showing the steps involved in sending the layout to IC Craftsman, a manually-routed layout of the complete cell is shown below. The first step is to place the transistor devices in the cellbox, using previous experience and MANUAL PLACEMENT MANUAL ROUTING DLE guides or other netlist flight lines if desired. Next, POLY and paths are drawn to connect the devices. Notice how the only connects to the ends of the wide transistors, using the - contact defined earlier. Finally, MET1 I/O pins are added on the routing grid. 4. More Pcell Details A simple transistor Pcell contains three terminals named G, S, and D. POLY shapes are connected to the G net with dbcreatepin(). One large shape is drawn underneath the whole device, not attached to any pin. D D G Separate smaller shapes are drawn over each source or drain region and tied to the appropriate terminal. Short devices also include shapes like the ones above. The pins are separated from the POLY pins by S S

5 the minimum DRC separation. The Cadence drawing purpose is used for each shape in the Pcell. To keep IC Craftsman from thinking that the D and S pins are connected by the underlying nonpin, the FULL_CONNECTIVITY option on the IC Craftsman export form should be turned off and the CONDUCTOR DEPTH set to zero. Alternatively, different Cadence layers or purposes could have been used for pin vs. nonpin diffusion shapes. When making a transistor with multiple fingers, our first attempt just defined more S and D shapes, electrically (but not physically) tied to one of the existing S and D nets. For wide transistors with no, the MUSTJOIN option on the IC Craftsman export menu properly instructed ICC to make sure the separate gate, source, and drain shapes got physically wired together during routing. However, with short transistors that had included on the device, the MUSTJOIN option made ICC add extra wiring and contacts to connect the and pin at the same location to each other, creating an undesirable mess and DRC errors. We basically wanted to tell ICC that some pins on a device are STRONG_CONNECTS (the and pins at the same location), but that these strongly connected pin groups should be considered MUST_CONNECTS to each other. A document on SourceLink called Implementing External Connections (Must Connects) in Parameterized Cells was followed to create nets and subnets in the transistor Pcells. Unfortunately, the Cadenceto-ICC translator did not pay attention the pin groupings. Although the latest version of ICC might allow for different kinds of pin groups like this, in the end our multiple-finger transistors are drawn having independent terminals for each source/drain region: D S D1 S1 D2 G G1 G2 G3 Just before exporting a design to IC Craftsman, a short piece of Skill code processes the layout s underlying netlist to connect the net on the D pin to any other Dn pins (D1, D2, etc.). The same is done for S and G pins. The transistor Pcells have a FLIP parameter that changes all S-pins to D-pins and vice-versa. A transistor with an odd number of fingers can simply be mirrored to do this, but with a device having an even number of fingers like the one above, the FLIP parameter is needed if a layout designer wants to swap the location of the source/drain regions to simplify routing or reduce parasitics. 5. Exporting to ICC The CDS-to-ICC translator menu provided by Cadence converts a layout design to ICC format and starts the IC Craftsman program. The ICC translator form refers to an icc.do file. For us, it looks something like this: grid wire ROUTING_PITCH MET1 (direction x) (offset 0.0) grid wire ROUTING_PITCH MET1 (direction y) (offset 0.0) cost layer MET1 high (type way) cost layer MET1 high (type length) cost layer CONT high (type length) cost layer CONT high (type way) cost layer free (type way) cost layer free (type length) cost layer POLY low (type way) cost layer POLY low (type length) cost layer forbidden (type length) cost layer forbidden (type way) unselect all vias select via _ POLY MET1 This sets up the routing grid so that any MET1 added by ICC tends to go on grid. The layer is needed to establish connectivity to transistor devices, but its cost is set to forbidden so no actual routing is done with it. Another file referenced by the ICC translator form is icc.rules, which contains most of the required DRC rules. This

file was initially created with the Cadence Rules Editor GUI interface, but editing the ASCII file with a text editor is easier for tweaking. It is shown here: ; DFII-IC Craftsman Translation Rules 1.

6 file was initially created with the Cadence Rules Editor GUI interface, but editing the ASCII file with a text editor is easier for tweaking. It is shown here: ; DFII-IC Craftsman Translation Rules 1.0 ; Title: icc.rules ; Technology File: proj_tech ; Creator: DFII-IC Craftsman Rules Editor ; Creation Date: Aug 21 14:46: ; From: layoutplus version Fri Jun 12 17:50:03 PDT 1998 (cds10067) ; User: atl iccrevision = 1.0 icctechnologyfile = proj_tech icclayers = list( list( ( MET1 drawing ) none horizontal WIDTH SEP nil t) list( ( CONT drawing ) cut off nil t) list( ( drawing ) local_interconnect orthogonal WIDTH SEP nil t) list( ( POLY drawing ) polysilicon orthogonal WIDTH SEP nil t) list( ( drawing ) n_diffusion orthogonal WIDTH SEP nil t) ) iccvias = list( list( ( proj_tech _ layout ) t) list( ( proj_tech POLY_ layout ) t) list( ( proj_tech _MET1 layout ) t) list( P list( ( drawing ) ( drawing )) nil) list( POLY P list( ( POLY drawing ) ( drawing )) nil) ) iccequivalentlayers = list() iccboundarylayers = list( list( ( MET1 drawing ) ( prboundary drawing ) SEP/2) list( ( CONT drawing ) ( prboundary drawing ) SEP/2) list( ( drawing ) ( prboundary drawing ) SEP/2) list( ( POLY drawing ) ( prboundary drawing ) SEP/2) list( ( drawing ) ( prboundary drawing ) SEP/2) ) icckeepouts = list( list(nil list())) The export form is then filled out as shown below. On the right are lines that can be placed in a.cdsenv file to automatically fill in these form values by default. ; cdsenv Variables to fill out ICC Export Form: ; icctranslator iccdirectory string /icc/4.0/tools/ iccraft/bin icctranslator exportdirectory string./icc_work icctranslator.exporteditor starticc boolean t icctranslator.exporteditor netlistfile string icctranslator.exporteditor netlistlibrary string icctranslator.exporteditor pinconnection string strong icctranslator.exporteditor interlayer boolean t icctranslator.exporteditor netlistsource string layoutcellview icctranslator.exporteditor usealternateviews boolean nil icctranslator.exporteditor netlistcell string icctranslator.exporteditor rulesfile string icc.rules icctranslator.exporteditor conductordepth int 0 icctranslator.exporteditor fullconnectivity boolean nil icctranslator.exporteditor userulesfile boolean t icctranslator.exporteditor netlistview string icctranslator.exporteditor iccoptions string -do icc.do icctranslator.exporteditor alternateviews string icctranslator.exporteditor cuttoedge boolean nil icctranslator.exporteditor keepoutdepth int 20

Interlayer rules are needed to keep, POLY, and separated from each other. These should be present in a Cadence technology file under physicalrules(spacingrules()).

The interlayer clearance rules confuse ICC around contacts involving local interconnect, making manual routing within ICC impossible without turning off rule checking.

Running ICC The picture on the left below is what appears in the IC Craftsman window after a design is successfully converted and the ICC application starts.

7 Interlayer rules are needed to keep, POLY, and separated from each other. These should be present in a Cadence technology file under physicalrules(spacingrules()). The ICC translator converts them to ICC format and merges them in the ICC working directory s design.str file. The interlayer clearance rules confuse ICC around contacts involving local interconnect, making manual routing within ICC impossible without turning off rule checking. However, automatic routing is still possible; just ignore the false error markers in the ICC tool. 6. Running ICC The picture on the left below is what appears in the IC Craftsman window after a design is successfully converted and the ICC application starts. It is apparent here that the underlying of the transistors is not present. The picture in the middle is the result of running route 5 in ICC, and the picture on the right is the result of running clean 5 after that. The final drawing might be considered clean enough to export back into Cadence. It was puzzling that for connections to VDD and GND, ICC chose to use _MET1 contacts instead of routing straight up or down to the horizontal busses, even though the MET1 routing cost was set to high. More tweaking of various routing options and costs could probably prevent this. To see if ICC could do better, route 25 was run next. The result is shown at the top of the next page on the left. This routing looked worse; more is not always better. It was decided that the internal N1 net should be routed without using any MET1. A blockage was drawn in the lower right corner to keep ICC from blocking access to the center of that lower right transistor. The result of routing with that blockage in place is shown at the top of the next page in the center. It appeared that the layout still used more MET1 than desired, so to force ICC to use less MET1, blockages were drawn on the MET1 layer at the top and bottom of the cell.

8 Routing and cleaning again resulted in the layout shown on the right below: Satisfied with this result, ICC was finally exited. After a few moments, the initial unrouted layout was replaced in Cadence with the drawing shown on the left below. MET1 pins and text were added, and some routes were cleaned up to create the final Cadence drawing shown on the right.

9 7. Summary This paper explained one way to define contacts, parameterized cells, and technology files to make IC Craftsman successfully route using a local interconnect. Other technologies or standard cell methodologies may have similar solutions. The local interconnect abilities of IC Craftsman could use further development, but considering that ICC evolved from a printed circuit board product, this is understandable. At this time, hand routing and polygon pushing by an experienced layout designer will no doubt produce smaller layouts for a local interconnect technology than any automatic solution. However, when a layout is in the early relative placement stage, automatic routing with IC Craftsman can be a powerful tool to let a designer quickly explore the routability of various placement options before choosing and compacting the final layout. As Cadence works to integrate ICC and Virtuoso into a more consistent and seamless user interface, adding features such as automatic placement and automatic Pcell configuration, the layout designer s task should become less tedious and overall productivity should increase. Thanks to SGI circuits and ECAD teams, application engineers at Cadence, members of the cct_ug_icc mailing list, and posters to the comp.cad.cadence newsgroup for their help with this issue. Color PDF versions of this document and presentation slides are available at Summarized notes from a Cadence R&D employee, September, 1999: Pseudo-contacts are generated and removed by the DFII translator; they are not part of IC Craftsman, which needs contacts to recognize connections. The Sourcelink document titled Implementing External Connections (Must Connects) in Parameterized Cells is wrong. There is supposedly a way to define Complex Pin Models so that the translator can get that information from CBDA, but there is no clear user documentation for it yet. Use tax commands instead of cost commands. Try this icc.do file: grid wire ROUTING_PITCH MET1 (direction x) (offset 0.0) grid wire ROUTING_PITCH MET1 (direction y) (offset 0.0) tax layer MET1 9 tax layer POLY 2 tax way 7 unselect layer change escape_distance 0 (layer ) rule layer (single_via_on_pin on) rule ic (via_on_pin on (grid off) (fit on)) rule ic (rotate_via on) To avoid false error markers, put interlayer rules in the icc.do file instead of translating them from the technology file, and try setting same-net rules, too.

Design rule illustrations for the AMI C5N process can be found at:

Design rule illustrations for the AMI C5N process can be found at: Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revised by C Young & Waqar A Qureshi -FS08 Document Contents Introduction