Tutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof.
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1 Tutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim I. Setup for Cadence Virtuoso 1. Copy the following files into your working directory. cds.lib display.drf lib.defs.cdsinit (Make sure that the file name is ".cdsinit". If you copy this file from a windows machine, the file name will be "cdsinit".) calibredrc.rul mydesign.tar.gz You will also need the "test.gds2" file you generated during Innovus lab. 2. Type the following commands to source the designated files. source /tools/cadence/ic616/cshrc.64ggbit source /tools/mentor/calibre/meta.cshrc 3. Open cds.lib and replace 'your_working_directory' by your working directory as follows. (Type the FULL directory name. Leave mydesign untouched at the end.) DEFINE mydesign /your_working_directory/mydesign 4. Open lib.defs and replace 'your_working_directory' by your working directory as follows. (Type the FULL directory name. Leave mydesign untouched at the end.) DEFINE mydesign /your_working_directory/mydesign 5. Uncompress mydesign.tar.gz in your working directory. tar xvfz mydesign.tar.gz 6. Run Cadence Virtuoso by typing 'virtuoso'. Page 1 of 12
2 II. Generation of Final Layouts 1. Import Your Design A. Virtuoso main window looks as follows. B. Choose 'File' -> 'Import' -> 'Stream...', then 'Virtuoso(R) XStream In' window will appear as follows. C. Choose a GDS2 file in 'Stream File'. (test.gds2 from Innovus lab) D. Choose mydesign in 'Library'. E. Choose your design name in 'Top Level Cell'. The design name is what you typed in 'GDS Structure Name' in Innovus. (In Innovus lab, it was test ) Page 2 of 12
3 F. The window should look like the following. G. Click 'Translate'. There must not be any error during translation. H. If you meet warning messages as above, just click No. (you should have only 1 warning, no error) Page 3 of 12
4 I. Choose 'Tools' -> 'Library Manager...' in Virtuoso main window then Library Manager window will appear as follows. J. Choose 'mydesign' in Library column. K. Choose your design in Cell column. L. Double-click 'layout' in View column. Page 4 of 12
5 M. Then a layout window will be shown as follows. N. Maximize the window and click 'Zoom to Fit' button in the toolbar. O. The current window shows standard cells and routed metals but you cannot see the details of standard cells. These abstract cells are called standard cell instances. To get a final layout, we need to load standard cells and replace standard cell instances by standard cell layouts. This is called 'flattening'. P. Choose 'Edit' -> 'Select' -> 'Select All' then all instances will be selected. Page 5 of 12
6 Q. Choose 'Edit' -> 'Hierarchy' -> 'Flatten...' and click 'ok' in 'Flatten' window with the default settings. Clicking empty space in the design will cancel the selection. R. The above snapshot was captured after flattening. S. Choose 'File' -> 'Save' to save your flattened design. T. Compare this layout with your encounter layout. Do those look similar? 2. How to Capture Screenshots Choose 'File' -> 'Export Image...' in the layout editor. Supported formats are bmp, jpg, png, and so on. 3. How to View Specific Metal Layers and Via A. On the left of your screen, there is Layers tab. In here you can control visibility of each layers. a) If you click 'NV', only the selected layer will be shown. b) If you click 'AV', all layers will be shown. c) Click a specific layer with your center mouse button. This will toggle the visibility of the layer. Page 6 of 12
7 d) After you toggle visibilities, you have to re-draw the layout to apply the changed visibilities. (Choose 'View' -> 'Redraw', or click 'Zoom to Fit' button in the toolbar) e) Choose 'Tools' -> 'Display Resource Manager' in Virtuoso window. When 'Display Resource Tool Box appears, click Edit, and Display Resource Editor windows appears. Choose any metal layer, change 'Fill Color' and 'Outline Color', and click 'Apply'. Redraw the layout to see if the new color was applied well. Page 7 of 12
8 B. Here is the metal layer mapping. You will need this in 'Lab Problem : Generation of final layouts and DRC' section. L49 - metal 1 L51 - metal 2 L62 - metal 3 L31 - metal 4 L33 - metal 5 L37 - metal 6 L39 - metal 7 L41 - metal 8 L43 - metal 9 L45 - metal 10 Actually each metal layer has two different names. For example, metal 1 layer has two names - 'metal 1' and 'L49'. Page 8 of 12
9 III. Design Rule Checking (DRC) 1. After flattening, choose 'Calibre' -> 'Run DRC'. Click 'Cancel' in 'Load Runset File' window. Just click Cancel. Page 9 of 12
10 2. Click 'Rules' tab, and choose 'calibredrc.rul' for DRC Rules File Field in the 'Calibre Interactive' box. Page 10 of 12
11 3. Click Inputs tab, and choose test.gds2 file for File field in Layout sub-tab. 4. Run DRC by clicking 'Run DRC' button. And two pop-up windows will be appear immediately. Click OK and Yes, and DRC will take a few minutes. Page 11 of 12
12 5. When DRC is finished, look at the following window to check the number of DRC violations. 6. A check box will be red if it has any DRC violation. 7. Summary of DRC would be stored in *.drc.results and *.drc.summary in your working directory. Page 12 of 12
Tutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim
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