Verification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems
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1 Verification Futures 2016 Nick Heaton, Distinguished Engineer, Cadence Systems
2 Agenda Update on Challenges presented in 2015, namely Scalability of the verification engines The rise of Use-Case Driven Verification SW as part of SoC Verification Cadence Systems, Inc. All rights reserved.
3 Bare metal software DSP software Init Software for boot, power, security Challenges today s SoC developers face Many IPs Standard I/O WiFi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, UART, timers Differentiators Custom accelerators, modem Many cores Both symmetric and asymmetric Both homogeneous and heterogeneous Lots of software Part of core functionality Communication stack, DSP software, GPU microcode User application software infrastructure Android, Linux Applications Middleware Operating Systems (OS) Drivers Firmware / HAL ARM V8 CPUSubsystem Application Specific Components Cortex Cortex -A53 -A53 Cortex Cortex -A57 A57 Processor Subsystem L2 cache L2 cache Cache coherent fabric 3D GFX Software DSP A/V SoC interconnect fabric ARM or ithers DDR PCIe HDMI USB3. Eth 3 Gen SAT 0 er High Speed, 2,3 net General- A MIPI Wired 0 0 Interface PH Purpose WLA PHY P P PHY N Peripherals Y H H Peripherals LTE Y Y High speed, wired interface peripherals Other peripherals SoC Boot process or ARM M0 Customer s Modem Application-Specific Components GPI O Display UAR INT T C PM Low-Speed I2C U MIPI SPI Peripherals JTA Tim Low-speed G er peripheral Low speed subsystem peripherals Communications L3 Communications L2 Communications L1 RTOS Drivers Firmware / HAL Cadence Systems, Inc. All rights reserved.
4 Common Customer Use Models Leveraging Integrated Suite Enables optimized verification and SW development flows VSP/IES Mixed VP Acceleration Workstation Workstation Palladium XP VSP/Palladium Hybrid Workstation Palladium XP TLM TLM Perspec vmanager Indago, SimVision TB System-level Use-Case Verification Plan & Management Debug & Analysis Palladium/Protium Hybrid FPGA Prototype Palladium XP Verification IP Verification IP Incisive VSP SystemC / Virtual Prototyping Cadence Systems, Inc. All rights reserved. Stratus High-level Synthesis JasperGold Formal Verification Incisive Simulation Palladium Acceleration & Emulation Solutions: Metric Driven Verification, ARM-based Development (Server, Emulation Mobile, IoT), C/C++/FPGA Hybrid Low Power & Mixed Signal, Functional Simulation Safety, TLM Palladium & Verification XP Workstation C/C++ FPGA Prototype TLM/ TLM / TB TLM / Workstation TB/ Palladium XP TB / Protium FPGA Based Prototyping FPGA Based Prototyping FPGA Prototype
5 Connection Points within the suite of engines Perspec vmanager Indago, SimVision Verification IP System-level Use-Case Verification Plan & Management Debug & Analysis Verification Acceleration with Hot Verification Swap, IP Coverage Merge, UPF/CPF Incisive VSP Stratus JasperGold Incisive Palladium Protium Assertions, XProp, Super Linting Common front-end with Multi Fabric Compiler SystemC / Virtual Prototyping High-level Synthesis Formal Verification Simulation Acceleration & Emulation FPGA Based Prototyping Solutions: Metric Incisive-VSP Driven Hybrid Verification, with Palladium/Incisive ARM-based Development (Server, Mobile, IoT), Low Power & Mixed Signal, Functional Safety, TLM & Verification Assertion Based VIP Cadence Systems, Inc. All rights reserved.
6 Capabilities combining simulation and emulation Common Compile Ease of transition Acceleration Workstation Palladium XP TB Gate-level acceleration Validate gate-level synthesis with minimal capacity overhead Perspec vmanager System-level Use-Case Verification Plan & Management Hot-swap Verification IP Balance software and hardware based execution Incisive VSP Stratus Time to point of interest SystemC / Virtual Prototyping Coverage Merge Faster coverage closure Indago, SimVision High-level Synthesis JasperGold Formal Verification Debug & Analysis Verification IP Incisive Simulation TB/ Palladium Acceleration & Emulation Solutions: Metric Driven Verification, ARM-based Development (Server, Mobile, IoT), Low Power & Mixed Signal, Functional Safety, TLM & Verification Accelerated VIP Migrate from simulation with VIPs to Protium acceleration with AVIPs with common library (roadmap) FPGA Based Prototyping In-circuit acceleration Re-use Environment Mix abstractions Balance by model availability Cadence Systems, Inc. All rights reserved.
7 Palladium Z1 Announced Q Cadence Systems, Inc. All rights reserved.
8 Key characteristics Delivering up to 5X greater emulation throughput Unmatched engineering productivity Up to 5X greater emulation throughput Up to 2.5X greater workload efficiency Up to 2X faster compilation speed Up to 50% higher average performance Scalable datacenter-class emulation system IP to full SoC emulation: 4 to 576 million per rack Scales up to 9.2BG with up to 2,304 parallel jobs Rack-based form factor: setup in existing data center Redundancy: reliability and availability Virtualization Virtual target relocation Advanced job reshaping Emulation Development Kits (EDK) Virtual Verification Machine (VVM) Best in class total cost of ownership (TCO) 8X higher gate density 92% smaller footprint 44% better power density 22 use models Palladium Z1 Model S18L 24" (0.61m) 38" (0.97m) 4 to 576MG User capacity 1152 GBytes User memory 1152 GBytes Debug memory 56 Gbps Per ports Up to 4MHz Max perf. Up to 140MG per hour Compile perf Cadence Systems, Inc. All rights reserved.
9 JasperGold formal verification platform JasperGold Apps Visualize Interactive UI & Debug Formal Property Verification App Automatic Formal Linting App Coverage Verification App Sequential Equivalence Checking App X-Propagation Verification App Control/Status Register Verif. App Connectivity Verification App Coverage Unreachability App Clock Domain Crossing App Functional Safety Verification App Low Power Verification App Security Path Verification App JasperGold Platform Core Technologies Assertion Based Verification IPs for AMBA and other common protocols Programmable Interface via TCL Parallel & Multiple Engines with ProofGrid Manager Links to System Development Suite (Incisive, Palladium, Metric-Driven Verification, Debug ) Cadence Systems, Inc. All rights reserved.
10 Tight integration with System Development Suite Visualize features in Indago for simulation users ESWD SimVision IDA Formal Assisted Debug Visualize Formal Verification View Formal Assisted Verification Closure vmanager Measure/ Analyze Plan Execute Construct vmanager integration Coverage unreachability Indago Debug Infrastructure Incisive Metrics Center Cross-platform Infrastructure Verification IP Catalog Incisive front-end and irun integration Assertion export to Incisive Incisive Simulation Engines Formal Assisted Simulation JasperGold Formal Engines Formal Assisted Emulation Palladium Emulation & Acceleration Assertion-Based VIP support Assertion export to Palladium IEEE Standard Languages & Industry Standard APIs Cadence Systems, Inc. All rights reserved.
11 JasperGold apps: design scope = now = near future Scope AFL XPROP CSR FPV ABVIP UNR FSV SEC SPV LPV CDC CONN SoC (Multi-CPU) w/sim Sub- System (Single-CPU) w/sim Cluster (Peripherals on bus) Unit (Multiblocks) Block Cadence Systems, Inc. All rights reserved.
12 Vertical Reuse SoC verification needs to address: Perspec takes use cases defined by users Diverse Scopes (Integration) Architect HW Developer Use Case Reuse SW Developer Diverse Users Verification Engineer SW Test Engineer Post-silicon Validation Engineer Generates code that runs on embedded CPUs Middleware (Graphics, Audio, etc..) OS & Drivers ARM V8 CPUSubsystem Cortex -A53 Cortex -A53 L2 cache Cortex -A57 Cortex A57 L2 cache Cache coherent fabric Application Specific Components 3D GFX DSP A/V Boot processor ARM M0 Modem Exercising the system through diverse relevant scenarios Bare Metal SW System on Chip (HW + SW) Sub-System IP DDR3 PHY USB PHY 2.0 PHY PCIe Gen 2,3 PHY Ether net PHY High speed, wired interface peripherals SoC interconnect fabric HDMI SATA MIPI WLAN LTE Other peripherals GPIO UART Display INTC PMU I2C MIPI SPI JTAG Low-speed peripheral Timer subsystem Low speed peripherals Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Diverse Platforms Horizontal Reuse Cadence Systems, Inc. All rights reserved.
13 Vertical Reuse The Solution: Perspec System Verifier Use Case Reuse Diverse Users Diverse Scopes (Integration) Architect HW Developer SW Developer Verification Engineer SW Test Engineer Post-silicon Validation Engineer Middleware (Graphics, Audio, etc..) OS & Drivers Bare Metal SW System on Chip (HW + SW) Sub-System Reusable Use Cases Perspec System Verifier Generated code Abstract Model Powerful Solvers C test SV test C test Scripts Multi-core Verification OS Mapping to Targets Modeling: Library provides built in content (e.g. coherency stressing) Delivers 10x Productivity Gain Generation Automation: Tests capture user intent & use cases IP Multi-cluster Apps Processors 3D GFX DSP A/V Many cores Boot Proc Comm Procs Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Diverse Platforms Horizontal Reuse Cadence Systems, Inc. All rights reserved.
14 New Portable Stimulus Specification (PSS) Standard Accellera PSWG is working on developing this standard Cadence & Mentor Contribution Enabling industry alignment on a Portable Stimulus Specification Contribution will help accelerate development of a standard that meets both vertical and horizontal stimulus and test reuse requirements A constraint driven model-based approach aligned with Perspec semantics and supporting graph-based descriptions of stimulus and test scenarios To learn more about the portable stimulus working group, visit web site Cadence Systems, Inc. All rights reserved.
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