Enabling success from the center of technology. Xilinx Embedded Processing Solutions

Transcription

1 Xilinx Embedded Processing Solutions

2 Goals 2 Learn why FPGA embedded processors are seeing significant adoption in today s designs What options are available for Xilinx embedded solutions Understand how the latest Xilinx development tools simplify the embedded design process

3 Agenda 3 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

4 Agenda 4 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

5 Why Embedded Processors? 5 Typical embedded system FPGA with custom functions Stand-alone processor with peripherals and memory Opportunity Move processor system into FPGA fabric Upgrade functions to improve performance and optimize cost Advantages Any thoughts? FPGA FIFO Filter FIFO Processor Ethernet Processor Mem Cntrl PHY SDRAM DDR2

6 FPGA Advantage 6 Customization Risk mitigation Lower design cost and less inventory Hardware acceleration

7 Customization 7 Choose between hard or soft processors FPU ARB EMAC Large menu of peripherals to choose from and modify CPU PCI Create user-defined peripherals Create non-standard solutions unavailable in stand-alone packages CACHE INTC DMA CUSTOM DDR2 UART UART UART GPIO GPIO

8 Risk Mitigation 8 Allows system-level changes late in project Processor hardware is field-upgradeable Guarantees product lifespan Soft IP can easily be upgraded to use new silicon Hard-processors continue on Virtex roadmap Soft-processor code can be purchased Can freeze product to satisfy military requirements

9 Lower Design Cost and Less Inventory 9 Design consolidation Sweep external components into the FPGA Smaller form-factor, less real-estate Increased reliability Procurement consolidation Combine device(s) across product range Footprint compatibility Reduced inventory holding Use the same hardware for multiple products FPGA content controls functionality

10 Hardware Acceleration 10 Create custom co-processor hardware Connected via low latency dedicated channel Enables optimum system partitioning Performing some software tasks in hardware can be expensive Performing some hardware tasks in software can be slow Tune your system for the optimum hardware/software balance. Off-the-shelf processors can not deliver this!

11 Tailor the System to Achieve Performance 11 MP3 decoding with custom hardware logic XCELL magazine #58 Third Quarter 2006 Custom Hardware Logic 100MHz MicroBlaze, pure software 1X = 146 seconds 100MHz MicroBlaze +FSL + LL MAC = 9 seconds 100MHz MicroBlaze +FSL + DCT + IMDCT + LL MAC = 7 seconds 16X IMDCT DCT LL MAC 21X 1x 2x 8x 10x 20x 50x 100x Performance Improvement Note: MicroBlaze v4.00 core, ML40x board, 100MHz system clock, EDK8.1

12 What Do Embedded Designers Need? 12 Designers are saying that they Want to minimize inventory of off-the-shelf (OTS) parts or inventory of different OTS parts for each project Want processor/sub-system that s a fit to the target application Want a solution that will not become obsolete Want to spend less time creating and debugging custom IP blocks Want to use sw resources across different projects Solution Requirement Inventory one type of silicon part (e.g. FPGA) that can be used across many projects A processor with a custom mix of standard peripherals or mix of custom peripherals Maintain same processor code for software re-use A wide range of pre-verified intellectual property with complete support infrastructure Common software development tools

13 Agenda 13 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

14 Embedded Processor Design 14 Filter FPGA FIFO FIFO So how are we going to develop this embedded processor system block? Ethernet PHY Processor Mem Cntrl SDRAM DDR2 Ethernet Processor Mem Cntrl

15 Embedded Design Flow 15 Select Platform Components Build Hardware.bit File Build Software.elf File Download Hardware Download Software

16 Selecting Platform Components 16 Build Hardware Download Hardware Select Platform Components.bit File Build Software Download Software.elf File Inputs Processor system requirement Board description file* Builder wizard Basic selections Outputs Hardware specification file Software specification file Hardware constraints file* Application code * optional

17 Building the Hardware 17 Build Hardware Download Hardware Select Platform Components.bit File Build Software Download Software.elf File Inputs Hardware specification Constraints Platform generation Collect HDL for peripherals Synthesis Implementation Translate Map Place and route Outputs Configuration file (.bit)

18 Building the Software 18 Build Hardware Download Hardware Select Platform Components.bit File Build Software Download Software.elf File Inputs Software specification Hardware specification Application code Generate Board Support Package (BSP) Peripheral drivers Standard libraries boot code Compile & link Outputs Executable file (.elf)

19 Downloading Hardware and Software 19 Build Hardware Download Hardware Select Platform Components.bit File Build Software Download Software.elf File Inputs Configuration file (.bit) Executable file (.elf) Configure the FPGA Initialize processor memory Run Outputs Flawless execution Award winning Best in class

20 Agenda 20 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

21 Block Diagram 21 FPGA ILMB Controller ILMB Debug Port IOPB MDM SDRAM Controller External Devices JTAG Header 32MB SDRAM Dual-port BRAM MicroBlaze OPB GPIO GPIO User LEDs DIP Switches DOPB DLMB Controller DLMB GPIO Push Switches UART RS232 Port

22 Tool Summary 22 Xilinx Platform Studio (XPS) Base System Builder (BSB) Wizard Generate Bitstream Build All User Applications.bit File.elf File Download Bitstream Launch XMD

23 Agenda 23 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

24 24 Range of FPGA Embedded Processor Solutions From space efficient to high performance processors Flexible integration PowerPC Variable resources Scalable cost points Features PicoBlaze MicroBlaze 32-bit General Purpose Architecture Soft Core with Acceleration Highest Performance 32-bit General Purpose Architecture With Acceleration Only Dual PowerPC core architecture Space Efficient 8-bit Architecture Soft Core Performance Extensive offering of common peripherals and IP

25 PicoBlaze for Simple Processing Solutions 25 Free PicoBlaze 8-bit microcontroller reference design macro for use in Xilinx FPGAs Xilinx CPLDs Benefits Predictable performance Minimal logic size Easy-to-use assembler Many examples Can be reconfigured On the Fly (OTF) Available at

26 MicroBlaze Overview 26 MicroBlaze processor core features 32-bit soft processor core Flexible architecture - customizable, automatically optimized to the FPGA target architecture RISC, Harvard architecture As small as 900 logic cells (basic CPU) 32 x 32 bit general purpose registers Fully synchronous Customize the processor functionality through parameters Multiple instantiations are possible High-speed Local Memory Bus (LMB) On-Chip Peripheral Bus (OPB) Supported FPGA (all architectures) Spartan-3 Virtex-4 Virtex-5

27 MicroBlaze Core 27 ILMB IXCL IOPB Cache Bus I/F PROGRAM COUNTER INSTRUCTION BUFFER INSTRUCTION DECODE SHIFT ALU MULTIPLIER DIVIDER BARREL FPU REGISTER FILE 32x32b Bus I/F Cache DLMB FSL DXCL DOPB Instruction Fetch Bus Interface ILMB - Instruction Local Memory Bus IOPB - Instruction On-Chip Peripheral Bus IXCL - Instruction Xilinx Cache-Link Data Bus Interface DLMB - Data Local Memory Bus DOPB - Data On-Chip Peripheral Bus DXCL - Data Xilinx Cache-Link MFSL - Master Fast Simplex Link SFSL - Slave Fast Simplex Link

28 FSL Advantages 28 No need to learn new bus architectures to build a hardware interface Saves clock cycles faster than a bus interface Eliminates bus signaling overhead No arbitration No address decode No acknowledge cycles Decoupled data clock from CPU allows for asynchronous operation Control bits limit need for a complex interrupt structure FSL port standard promotes design reuse

29 Fast Simplex Link (FSL) 29 FSL is a point-to-point unidirectional bus that can be used to connect input/output IP cores to the MicroBlaze processor core. FSL FSLn_M_Clk FSLn_S_Clk FSLn_M_Write FSLn_S_Read MFSL0 FSLn_M_Data FSLn_M_Control FSLn_M_Full FIFO FSLn_S_Data FSLn_S_Control FSLn_S_Exists User Output IP Core MicroBlaze FSL FSLn_S_Clk FSLn_M_Clk FSLn_S_Read FSLn_M_Write SFSL0 FSLn_S_Data FSLn_S_Control FSLn_S_Exists FIFO FSLn_M_Data FSLn_M_Control FSLn_M_Full User Input IP Core FSL consists of a Master Bus (writes to FIFO), a Slave Bus (reads from FIFO). The FIFO can be up to 8K deep and 8/16/32-bits wide.

30 PowerPC Overview 30 PowerPC Processor Core Features PowerPC 405 core 32-bit RISC architecture 5-stage data-path pipeline 16KB instruction and data caches 64-bit high-speed Processor Local Bus (PLB) Device Control Register Bus (DCR) Timers: PIT, FIT, Watchdog Dedicated On-Chip Memory (OCM) interface for instruction and data JTAG Debug and Instruction Trace Support Built-in Memory Management Unit (MMU) 600 DMIPS at 400 MHz 0.9mW/MHz typical power Supported FPGA Architectures Virtex-II Pro Virtex-4 FX

31 PowerPC 405 Core 31 PLB IOCM I-Cache Array I-Cache Controller Instruction-Cache Unit 16KB MMU Instruction Shadow-TLB (4-Entry) Fetch and Decode Logic CPU 3-Element Fetch Queue Timers D-Cache Array Cache Units Data-Cache Unit 16KB D-Cache Controller Unified TLB (64-Entry) Data Shadow-TLB (8-Entry) 32x32 GPR Execution Unit ALU APU MAC Timers and Debug Ports Debug Logic PLB DOCM APU JTAG I-Trace

32 CoreConnect Bus Architecture 32 DCR DCR Interface Processor On-Chip Device Control Peripheral Local Register Bus Bus (PLB) (OPB) Bus (DCR) 32-bit address, 64-bit 32-bit data PPC 405 CoreConnect Separate Single-cycle 10-bit address, consists read data and 32-bit of transfers three write data Core buses Maximum Directly distinct for accessible buses overlapped peripherals by / PPC transfers high Interface loadto register-based PLB Interface High I/O devices performance PLB Arbiter Instruction PLB Data PLB-OPB Bridge OPB OPB Arbiter High-speed Peripheral Memory Controller I/O Device Interface Memory Controller FPGA High-performance devices are connected to the PLB Memory and I/O devices with lower-performance requirements are connected to the OPB

33 Auxiliary Processor Unit (APU) 33 Accelerate performance beyond the core Offloads CPU intensive operations Extends PowerPC instruction set Provides direct interface from CPU instruction pipeline to FPGA logic Enables integration of coprocessor and hardware accelerators Flexible high bandwidth interfaces to and from fabric Increase performance by over 20X

34 Agenda 34 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

35 FPGA System Design 35 FPGA Filter FIFO FIFO Ethernet Processor Mem Cntrl

36 Embedded Development Kit 36 Xilinx Platform Studio (XPS) The hardware tool Xilinx peripheral IP library Includes MicroBlaze soft core Software Development Kit (SDK) Embedded debug

37 Xilinx Platform Studio (XPS) 37 Base System Builder (BSB) Enables the creation of a custom PowerPC TM or MicroBlaze based computing platform with just a few mouse clicks All detailed connections and a default memory map are generated automatically Integrated Development Environment (IDE) and tool suite used to define, configure, and generate a hardware/software design Programming environment for either a stand-alone or real-time operating system Software development tools GNU C/C++ Compiler (gcc) GNU Debugger (gdb) Xilinx Microprocessor Debug Engine (XMD) Host-based target control using command line tools for complex regression testing

38 Growing Suite of Peripheral IP 38 Memory Interface Cores External Memory Controller (SRAM/Flash) SDRAM Memory Controller DDR SDRAM Memory Controller DDR2 SDRAM Memory Controller System ACE Interface Controller BRAM Interface Controller Peripherals PCI Arbiter External Peripheral Controller CAN Controller HDLC Interface Chipscope Integrated Controller Chipscope Integrated Logic Analyzer Chipscope OPB Integrated Bus Analyzer Peripherals (continued) Interrupt Controller 16450/16550 UART UART Lite IIC SPI Ethernet (EMAC) Ethernet Lite (EMAC Lite) ATMC (Trace Core) Timer/Counter Fixed Interval Timer Watchdog Timer GPIO Central DMA Controller And More! Pre-designed, verified and validated for Xilinx Solutions Customers want to spend less time creating and debugging custom IP blocks

39 Xilinx Platform Studio SDK 39 The software tool Can be launched from XPS or independently Software application hand-off from XPS to SDK Software platform generation Linker script generation Software interface document generation Download FPGA bitstream Flash programmer Improved ease-of-use Project setup wizard Enhanced C/C++ editor support includes Code folding of functions Methods Classes, structures, and macros Eclipse based platform version v3.1

40 XPS to SDK Software Development Flow 40 XPS SDK Generate Hardware Platform Generate Software Platform Libraries and Drivers Create Software Application Project Add Sources and Edit Generate Software Platform New for 9.1i Compile and Link Debug And Profile Done? No Yes Download to Board

41 SDK Profiling 41 Determine the how percentage many times of a of time each specific function function took was called All All fully fully integrated into into the the Platform Studio Studio SDK SDK environment

42 Platform Debug 42 The ability to debug and analyze both the hardware and software platforms simultaneously Software debug via integrated GNU debugger Differentiate critical versus typical accesses using software breakpoints Hardware debug using ChipScope Pro Capture unexpected system issues and exceptions using hardware triggers Synchronous cross triggering between the hardware and software

43 Cross Triggering 43 ChipScope Pro triggering debugger example Complex trigger condition detects address and data value simultaneously Suspends software routine within a few clock cycles Enabling better insight into the HW / SW code dynamics

44 Xilinx Compatible OS and RTOS 44 Operating System Vendor MicroBlaze PowerPC VxWorks Wind River Linux μclinux Nucleus Plus ThreadX μc/os-ii OSE Integrity Neutrino ecos LynuxWorks MontaVista Wind River LynuxWorks Petalogix Mentor/ATI Express Logic Micrium ENEA Green Hills QNX Mind

45 To Find Out More. 45 MicroBlaze Processing Solutions Visit for more information Xilinx Embedded Magazine Latest Issue Endless Possibilities (April 2006) On the web at Xilinx.com Xilinx Processor Central site Xilinx Embedded Development Kit, Platform Studio Tools xilinx.com/xps Xilinx Design Services Xilinx and Partner Boards (Reference, Development, Eval) Xilinx Online Store ww.xilinx.com/xlnx/xebiz/onlinestore.jsp?sglobalnavpick=purchase Comprehensive Embedded Services Embedded Systems Development Course (2-Day Course) Effectively develop, debug, and simulate an embedded system On-Site Xilinx Embedded Design Specialist Award-Winning Technical Support Customer Hotline Support MySupport.xilinx.com Embedded Processor Forum and Tech Tips

46 Agenda 46 Advantages of using Xilinx embedded processors Design flow overview Demo 1 Creating a design Processor options Understanding the development environment Demo 2 Running the design

47 Tool Summary 47 Xilinx Platform Studio (XPS) Base System Builder (BSB) Wizard Generate Bitstream Build All User Applications.bit File.elf File Download Bitstream Launch XMD

48 What s Next? 48 Contact your local FAE for more information Get Xilinx tools ISE WebPack can be downloaded free EDK is often bundled with Avnet development boards during Avnet Speedway promotion Get a development board Create your own embedded processor design! Attend Avnet Speedway workshop for a quick start

49 Appendix 49

50 UltraController-II 50 Easy to use HDL module sys_clk Interrupt sys_rst_out sys_rst JTAG Code Loaded and stored in Cache RR ee ss ee t t J T A G ISOCM PowerPC 405 I-Cache D-Cache DSOCM FPGA Fabric FPGA Fabric Simple processor/fabric interface uses minimal FPGA resources gpio_in gpio_out Up to: 450 MHz 700+ DMIPS Only 0.29 mw/mhz 10 Logic Cells High Performance Small Footprint Controller

51 UltraController-II Module 51 PowerPC 405 core and Tri-mode Ethernet MAC (XAPP 807) Virtex-4 FX Reference Design Utilizes Integrated PPC Integrated EMAC Advantages Low resource utilization <1% of Virtex-4 FX12 Supports up to 90Mb/s (non TCP/IP) Applications Lightweight web server Monitor and/or influence the system status Replace legacy RS-232 serial interface

52 Customer Success Stories 52 Competition: NIOS, Motorola Needs: Reduce cost Integrate custom mix of standard peripherals and own IP/logic Initial Concerns: Performance of Xilinx SDRAM controller No wake and sleep features in Xilinx solution. Solution: Worked with field to find cost point- XC3S400 Built FSL-based SDRAM controller XDS Dublin built wake and sleep func. OPB used to connect mix of standard IPs XC3S400 MicroBlaze core at about 65MHz OPB ILMB UART Microblaze 2X Timers Int. Ctl DLMB BRAM SDRAM Mem. Ctl FLASH Mem. Ctl MicroBlaze processor sub-system HDLCU BSII CRCU Ethernet Lite DSP MUX LCU User Logic GPIO XC3S400 CPLD FLASH SDRAM DSP Application: GSM/G3 Base Station

53 Customer Success Stories 53 Application: Home/Enterprise Security Systems Competition: Freescale Needs: Replace off-the-shelf DragonBall processor (at end-of-life stage) After this win, replaced perfectly good (shipping) Coldfire too! Moderate CPU performance Flexibility to integrate custom and standard IPs per project Re-use peripherals for other projects uclinux Initial Concerns: No FPGA experience Un-familiar with soft-processor solution Solution: Deciding factor: OTS fixed processors is an in-exact fit to the target application OTS processors can become obsolete Configurable soft processor, flexibility to tailor mix of IPs RTOS XC3S400 and XC3S1000 RTOS: uclinux Prototype: Q platforms for 3 year production OPB ILMB UART Lite Custom IP Custom IP XC3S400 Microblaze UART UART Lite DLMB SDRAM BRAM FLASH MicroBlaze processor sub-system Custom IP 10/100 Ethernet User Logic GPIO 32 Bit Check out and Embedded Magazine for ESC April/06