Managing Clock Distribution and Optimizing Clock Skew in Networking Applications

Transcription

1 Application te Managing Clock itribution and Optimizing Clock Skew in Networking Application by Cameron Katrai Abtract Today high performance ytem need low kew clock generation and ditribution. Clock kew i defined a the difference in time between imultaneou clock tranition within a ytem. The kew ha become the major part of contraint that form the upper boundary for the ytem clock frequency. eduction in ytem clock kew reduce cot by avoiding complicated architecture or fater logic. Phae Lock Loop-baed clock ditribution i becoming one of the mot ought after olution for creating low kew ytem deign. Pericom ha developed the following et of low-kew PLL Clock river: PI6C2501(3V), (3V), PI6C2509A (3V), PI6C2510 (3V), PI6C5932 (5V), PI6C9910 (5V), and PI6C9930 (3V). They provide zero input-to-output delay uing high-peed proce and phae lock loop technology. In a 24-pin TSSOP package, the PI6C2509A upport Spread Spectrum modulation of timing ignal and operate fater and conume le pace than alternative device, providing ignificant improvement in performance and cot. PI6C2501(3V), (3V), PI6C2509A/2510A(3V), PI6C5932(5V), PI6C9910(5V), and PI6C9930(3V), provide the lowet phae error over all frequencie and introduce no additional jitter a a reult of Spread Spectrum modulated input clock ignal. It i thee feature that allow Pericom PLL clock driver to upport tringent input-to-output delay (150p) and output-to-output kew le than 200p. Introduction Better Clock ditribution trategie uing PLL clock driver have made a ignificant contribution to high-performance ytem deign. If clock ditribution network are not properly contructed, they may detract from ytem-level performance. Thi application note define the kew in a ytem, decribing it effect on performance. ecommendation and upporting analyi are given for deigning near optimal clock network. Thi note alo illutrate that clock network deign can be a urpriingly complex tak involving many tradeoff. Clock network mut be deigned to minimize kew or the difference in delay throughout a clocking network. It i ideal that every component, uch a equential element, i.e. flipflop and latche, that need clocking, hould receive the edge of the clock at the ame time within each clock period. Fully ynchronou deign require thi methodology. Synchronou deign are highly recommended ince they can tolerate higher clock rate and are eaier to perform timing analyi. To enure that the network operate a cloely to the ideal a poible, the kew mut be minimized along the entire clocking network. Thi enure that all equential element ee a common clock edge. For any deign with more than 100 flop and latche, Pericom trongly ugget ome form of clock tree tructure for clocking. delay and wiring delay are the two mot ignificant factor contributing to kew. The clock topology can ignificantly contribute to kew. A will be dicued, a good clock network mut balance factor uch a kew and clock tree delay. In the next ection a real clock deign i examined for analyi of clock kew. eign Example Both the delay in the data path and the clock kew affect data tranfer from one ection of the deign to the other ection. The data path delay i defined a the delay from a regiter (F1) in a ection to the input of another regiter (F2). Figure 1 depict thi delay. The delay include CLKA to and et up hold time at point B. The clock kew or Tkew i the difference between a riing edge on CLKA in F1 and CLKB in F2. The Tkew define both the poitive and negative kew. Poitive kew affect data tranfer from a hold time tandpoint. Negative kew affect data tranfer from a et up time tandpoint. If the data path from F1 to F2 i too long, a et up time violation i realized on F2. Clock kew alo affect the et up and hold time. A more practical and realitic clock ditribution i hown in Figure /29/98

2 Application te Figure 1. ata Path elay are ued a Clock Tree to ditribute the clock throughout the ytem. Clock tree introduce a third delay into the deign that can caue problem. PLL clock buffer are included to eliminate thi additional delay a hown in Figure PLL, which can provide kew management to help compenate for clock tree delay, can alo be added to each ection to reduce Figure 2. Practical and ealitic Clock itribution the effect of Tree delay difference and help manage kew from chip-to-chip. The PLL ynchronize the riing edge on SYSCK o that it will be imultaneou with a riing edge on flop ck (Figure 3). If the PLL i ued on each ection, all flop ck ignal on each ection will be imultaneou within the error of the PLL. The PLL will compenate for difference in delay from ection to ection. Figure Synchronize the iing Edge on SYSCK 72 12/29/98

3 Application te PI6C2501 Clock river The PI6C2501 feature a low-kew, low-jitter, phae-lock loop (PLL) clock driver (ee Figure 4). By connecting the CLKOUT output to the feedback FBIN input, the propagation delay from the CLKIN input to any clock output will be nearly zero. Product Feature Allow Clock Input to have Spread Spectrum modulation for EMI reduction Zero Input-to-Output delay Low jitter: Cycle-to-Cycle jitter ±100p max. On-chip erie damping reitor at clock output driver for low noie and EMI reduction Operate at 3V Vcc Packaged in Platic 8-pin SOIC Package (W8) Wide range of Clock Frequencie S2 S1 2 PLL Extra ivider -3, -4 Select Input ecoding MUX 2 CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 Extra ivider -2, -3 CLKB3. CLKB4 Figure 4. PI6C2501 Block iagram Figure 5. Block iagram Product Feature Zero input-output propagation delay Input-to-output kew le than 150p (Cypre i 250p) Output-output kew le than 200p evice-device kew le than 300p (Cypre i 700p) Two bank of four output (Three-Stateable) 10 MHz to 134 MHz operating range Low jitter, le than 100p cycle-cycle (-1, -1H, -4) Space-aving 16-pin TSSOP (-1H only) & 150-mil SOIC pkg. Providing two bank of four output, the and PI6C2308 are 3V zero-delay buffer deigned to ditribute clock ignal in application uch a PC, worktation, datacom, telecom, and high performance ytem. Each bank of four output can be controlled by the elect input. With much better electrical characteritic, the provide 8 copie of a clock ignal that ha 150p phae error compared to a reference clock. The kew between the output clock ignal for i le than 200 p. When there i no riing edge on the input, the PI6C2308/A enter a power-down tate. In thi mode, the PLL i off and all output are three-tated reulting in le than 50µA of current draw. Bae part, PI6C2308/A-1, provide output clock in ync with a reference clock. For deign requiring fater rie and fall time, PI6C2308/A-1H i the high-drive verion of the PI6C2308/A-1. epending on which output drive the feedback pin, PI6C2308/A-2 provide 2X & 1X clock ignal on each output bank. PI6C2308/A-3 provide 4x and 2X clock ignal on the output. PI6C2308/A-4 provide 2X clock ignal on all output. PI6C2308/A allow bank B to be Three-tated if all output clock are not required. For teting purpoe, the elect input connect the input clock directly to output. For zero delay operation, ha an open feedback path that i eaily cloed (by driving any output into the pin, ee Figure 5). By adjuting the feedback path, other intereting application can be achieved 73 12/29/98

4 Application te elay CPU Clock Generator K IN Zero elay /N Zero elay CLK1 Early CPU Clock CLK2 CLK3 CLK4 CLK5 CLK6 CLK1 NX CLK IN CLK2 CLK3 CLK4 CLK5 CLK6 Chipet Figure 6. Zero elay Operation Of interet i the generation of Early Clock uing a dicrete delay element in the feedback path. Output can then lead the input ignal. Thee output are Early compared to the input clock. Certain chipet require ome copie of the hot clock, which are early compared to the ret of the hot clock copie. Figure 6 how uch application. By placing an N divider in the feedback path (ee Figure 7), a deigner can adjut all output to run at a frequency that i XN time in the input frequency. Whatever the multiplication factor, input and output frequencie mut be in the MHz range, which mean the divider cannot be larger than 1 Zero elay CLK1 Figure 8. Zero elay CLK2 CLK3 CLK4 CLK5 CLK6 Figure 9 how a ituation where output clock 1 ha a larger load. Becaue the PLL adjut itelf to poition the zero kew between the and the feedback pin, and CLK1 both cro Vdd/2 at the ame time. But, ince the other output clock are le loaded, their rie time i fater than CLK1. Conequently, they advance the by a certain amount that can be controlled by the amount of the load. Figure 7. N ivider in Feedback Path The PLL compare the phae of two ignal: phae of pin at a threhold of vdd/2 with that of the pin at the ame vdd/2 threhold. Tranition of all the output are at the ame time. Thi alo include the output driving. By changing the load on a pecific output, the deigner i able to change the rie time of that output and therefore change the time it take for that output to get to vdd/2 threhold relative to when input reache the vdd/2 threhold. tice that the zero-delay buffer will alway adjut itelf to keep the vdd/2 point of the output at zero delay from the vdd/2 point of reference. The reult i that output can be advanced by loading thi output more heavily than the other or output can be lagged by loading thi output le heavily than the other (ee Figure 8). Figure 9. Output Clock 74 12/29/98

5 Application te The timing diagram (ee Figure 10) how a ituation where the other output clock are loaded heavier. tice that the PLL adjut itelf o that both and the feedback clock cro the V/2 at the ame time. However, ince the ret of the clock have heavier load, they are delayed by a certain amount that i controllable by the load. 3V Vcc 5V Clock Signal = Zero elay CLK1 CLK2 CLK3 CLK4 CLK5 3V Signal CLK6 Figure 11. 5V Input Tolerant By ganging multiple output together, the output kew can be dramatically reduced. Thi method can alo increae the drive, a illutrated in Figure 12. Figure 10. Timing iagram Many ytem ue both 5V and 3V upplie. Figure 11 how how to make a 3V clock out of a 5V clock uing a zero-delay clock. High-energy Electromagnetic Field (EMF), caued by highfrequency witching ignal travelling around the ytem, caue Electromagnetic Interference (EMI) and Electromagnetic Coupling (EMC). Long tranmiion line ditributing thee high-frequency ignal are an automatic caue of EMC and EMI. A good technique to control EMI and EMC i to reduce the actual energy of the high frequency ignal. can be ued to accomplih thi. A hown, it i ued to convert 5V clock ignal into 3V clock ignal on the output. Intead of 5V ignal, thee 3V ignal are ditributed over long tranmiion line. Hence the energy in the generated EMF i ubtantially reduced. The output of the i 3V, winging rail to rail, making it 5V TTL compliant. Hence at the load, it can be driven into a 5V device. The only requirement here i the preence of a 3V upply. Figure 12. Ganging Output 75 12/29/98

6 Application te G PI6C2509A, 24 Pin 5 1Y[0:4] difference created by the PLL can alo be analyzed by enabling and diabling the PLL and by comparing the characteritic. The PI6C2509A can generate an early clock. Thi allow the clock edge to arrive at the load at the ame time the clock arrive at the clock buffer input. Thi i achieved by matching propagation delay of the feedback line with the propagation delay of output to load. 2G CLKIN FBIN AVcc PLL 4 2Y[0:3] FBOUT PI6C9930 Product Feature Seven Copie of Input Plu One x 2 or Seven Copie of Input ivided by 2 SAM Timing Compatible with PCI 3V Interface Skew Le than 0.25n 50 Percent Output uty Cycle Low ie Balanced rive Output Better than 1V/n lew rate Figure 1 3V Zero elay, PLL Clock river PI6C2509A Product Feature Meet Intel Spec for PC100 Input to Output kew le than 150p Skew le than 200p Jitter le than 100p For 100 MHz SAM IMM module Operating Frequency up to 134 MHz eference Clock Input tolerate evere underhoot/overhoot Multiple Vdd and V pin for noie reduction The PI6C2509A/2510A allow zero phae and frequency clock ditribution for PC100, and are the ame PC SAM egitered IMM Specification with PC bu peed of up to 100 MHz. Zero elay ditribute multiple clock ignal with very low kew between output and zero delay. The PLL i fed a reference input and a feedback input that i actually one of the output (ee Figure 13). The phae detector in the PLL circuit adjut the output frequency of the VCO o that the two input have no phae difference. Pericom PI6C2509A ha many mode of operation, that aid the deigner to achieve power conumption reduction, to minimize EMI, and for troublehooting. By diabling a bank, the output clock i pulled down to a low tate. The enable diable feature allow a method of diabling all or part of the clock output without PLL retoration. Thi feature allow preervation of ignal integrity and allow reducing power conumption and radiate emiion. Additionally, the PLL can be diabled to place the chip in a bypa tet mode in which the input clock i buffered directly to the output and the output clock i only delayed by the output buffer. Jitter characteritic and phae PI6C9930 i a 3V, Low-Skew Clock providing low-kew ytem clock ditribution. Thi multiple-output clock driver optimize the timing of high-performance computer ytem. The completely integrated PLL allow zero delay capability. External divide capability, combined with the internal PLL, allow ditribution of a low-frequency clock that can be multiplied by virtually any factor at the clock detination (ee Figure 14). FS Tet Phae et PI6C9930 Filter 2 VCO Q0 Q2 Q3 Q4 Q6 Q7 Figure 14. 3V Zero elay, PLL Clock river Compatible with PCI 3V Interface 76 12/29/98

7 Application te The PI6C9910 provide 8 zero-delay with kew le than 250p for clock output to a reference clock input (ee Figure 15). Operating in the range of 15 to 80 MHz, the PI6C9910 i an excellent clock driver for high-performance computing and networking ytem. At the heart of PI6C9910 i a tate-of-the-art PLL that generate a clock that i completely in phae with the reference input clock. There are two device in PI6C9910 family: the PI6C and the PI6C9910A. The PI6C ha high-drive output deigned to drive 30pF capacitance. Since the typical input capacitance of a CMOS device i 7pF, PI6C i capable of driving 4 CMOS device. The PI6C9910A balanced drive output ignificantly reduce output drive current that reult in a reduction in underhoot and overhoot. In ituation where the driver output ha to drive more than one receiver, the balanced drive can help. In thee example, the line are high impedance; however they are poorly terminated. Balanced drive output alo help in ituation where the line are properly terminated and the output drive only one receiver. The PI6C9910 device i available in pace-aving 24-pin SOIC and SSOP package. PI6C9910 The PI6C5932 provide ix low-kew (<250p) clock output (5Q and Q/2) to a reference clock input (ee Figure 16). The PI6C5932 i an excellent clock driver for high-performance computing and networking ytem. It provide feature uch a +24mA Balanced rive Output, a PLL bypa feature for low frequency teting, an Internal VCO/2 option for wider frequency range, and output for Tri-tate and reet while OE LOW. The PI6C5932 extend Pericom popular SiliconClock product line of PLL-baed zerodelay clock generator to 100 MHz. PI6C5932 i pinout compatible with QS5930 deign. Both clock, PI6C5932 and PI6C5930, accept a le than perfect clock ignal, clean it and buffer it via ix balanced driver for ditribution to multiple load. They can alo be configured a a frequency doubler to boot clock peed. Clock kew between any two output driver for both device i < 250p. PI6C5932 Product Feature 100 MHz operation Low kew (<250p) Small Footprint QSOP-20 Package Balanced drive output (+24mA) Phae et Filter VCO FEQ_SEL PLL_EN Sync FS Tet Q0 Phae et Filter VCO 2 CLK Figure 15. PI6C9910 Block iagram Q2 Q3 Q4 Q6 Q7 OE Q6 Q/2 PI6C5932 Q2 Q3 Q4 Q6 Q2 Q3 Q4 Q/2 PI6C9910 Product Feature Eight zero-delay, low-kew copie of input PCI Application, PCI-to-PCI bridge timing Skew Le than 0.25n 50 Percent Output uty Cycle Low-ie Balanced-rive Output (PI6C9910A) and High-rive Output (PI6C9910-5) Better than 1V/n lew rate Figure 16. PI6C5932 Block iagram 77 12/29/98

8 Application te V Pericom Clock river, and PLL 5V river 3V Pericom Clock river, and PLL 3V river Input Output per Inpu t PC/te Inv PI49FCT PI49FCT PI49FCT Ye PI49FCT3807 PI6B PI6C3818A 1 18 PC PI6C3810A te PI6C3813A 1 13 PC PI6C3807A 1 7 te PI6C3805A 1 5 te 3V Zero elay PI6C9930 Input Output per Inpu t Q0 & (-Q7)/ 2 Inv PI49FCT804T 2 4 PI49FCT805T 2 5 PI49FCT2805T 2 5 PI49FCT806T 2 5 Ye PI49FCT807T PI49FCT2807T PI49FCT811T Prog 5V Zero elay PI6C Q0-Q8 PI6C Q/2 & (Q0-Q4) Skew Summary The topology of a clock net can ignificantly contribute to kew if it become long and convoluted. Even after conidering and balancing the effect of buffer delay, fanout, wire length, and topology, mall amount of delay variation are poible. PLL clock driver are the bet way to eliminate kew and provide ynchronou deign. The PI6C2501(3V), (3V), PI6C2509A/ 2510A(3V), PI6C5932(5V), PI6C9910(5V), and PI6C9930(3V) have many mode of operation that aid the deigner to reduce power conumption, minimize EMI, and for troublehooting. The enable diable feature permit diabling of all or part of the clock output without PLL retoration. Skew PI6C :09 PI6C :10 PI6C :09 1 2x(1:4) Ye PI6C2501/2 1 1: 1 PI6C : 4 I2C. 8n. 5n. 5n. 5n. 35n. 35n. 5n 0.25n 0.25n SAM CLK 3/5V 5V In Tol # PLL Package/Pi n. 8n. 5n. 5n. 35n. 35n. 25n 3. 25n 3. 25n 3. 25n 3. 25n 3 3/5V 5V In Tol # PLL Package/Pi n P16/S16 P20/S20/Q20/H20 P20/S20/Q20/H20 P24/Q24/S24 Ye 5 1 S24/H24 Ye 5 1 Q20 S16 P20/S20/Q20/H20 P20/S20/Q20/H20 N A V48 (SSOP) N A H28(SSOP) N A H28(SSOP) Q n 3 1 S24/H24 0.2n TSSOP 0.2n TSSOP 0.2n TSSOP 0.2n 1 16 TSSOP and SOIC 0.2n SOIC 0.2n SOIC Operating in the range of 10 to 100 MHz, the PI6C180 i a high fanout Clock with 18 output, I 2 C for diabling individual clock, and EMI reduction upport. Pericom i the leading provider of advanced interface olution for peronal computer including Bu Switche, Analog Switche, and Logic evice. A ytem performance continue to expand to ever increaing frequencie and beyond, high-performance clock driver and generator are eential to utain improved ytem performance. Pericom clock technology provide new level of price performance for PC clock ytem. Pericom Semiconductor Corporation 2380 Bering rive San Joe, CA Fax (408) /29/98