ECE 552 / CPS 550 Advanced Computer Architecture I. Lecture 4 Reduced Instruction Set Computers

Transcription

1 ECE 552 / CPS 550 Advanced Computer Architecture I Lecture 4 Reduced Instruction Set Computers Benjamin Lee Electrical and Computer Engineering Duke University

2 Microprogramming in 1970 s Technology Instructions - ROMs re faster than DRAMs - For complex instruction sets (CISC), datapath and controller re cheaper and simpler - New instructions (e.g., floating point) supported without datapath modifications Compatibility - ISA compatibility across machine models re cheaper and simpler - Fixing bugs in the controller was easier In the 1970s, except for cheapest and fastest machines, all computers re microprogrammed ECE 552 / CPS 550 2

3 Microprogramming in 1980 s Increasing Complexity Technology Instructions - CISC ISAs led to subroutine and call stacks in microcode - Fixing bugs in control conflicts with read-only nature of ROMs - Advent of VLSI technology - Assumptions about ROM vs RAM speed became invalid - Better compilers made complex instructions less important - Compilers had difficulty using complex instructions Microarchitecture - Microarchitectural innovations: pipelining, caches and buffers, etc. - Make multiple-cycle execution of reg-reg instructions unattractive ECE 552 / CPS 550 3

4 Modern Microprogramming Microprogramming is far from extinct - Played crucial role in microprocessors of 1980 s (e.g., Intel 386, 486) - Plays assisting role in modern microprocessors Assisting role in modern microprocessors - Example: AMD Athlon, Intel Core 2 Duo, IBM Por PC - Most instructions executed directly (hardwired control) - Infrequently-used, complicated instructions invoke microcode engine Assisting role in modern microprocessors - Patchable microcode common for post-fabrication bug fixes - Example: Intel Pentiums load microcode patches at bootup ECE 552 / CPS 550 4

5 CISC to RISC Instruction Management - Shift away from fixed hardware microcode, microroutines - Exploit fast RAM to build instruction cache of user-visible instructions - Adapt contents of fast instruction memory to fit what application needs at the moment. Simple Instruction Set - Shift away from complex CISC instructions, which are rarely used - Enable hardwired, pipelined implementation Greater Integration - In early 1980s, able to fit 32-bit datapath and small cache on die - Allow faster operation by avoiding chip crossings in common case ECE 552 / CPS 550 5

6 CDC 6600 Seymore Cray, 1964 Control - Fast, pipelined machine with 60-bit words - Ten functional units (floating-point, integer, etc.) - Hardwired control, no microcoding - Dynamic instruction scheduling with a scoreboard System Organization - Ten peripheral processors for input/output - Fast time-shared 12-bit integer - Very fast clock, 10MHz - Novel Freon-based technology for cooling ECE 552 / CPS 550 6

7 CDC 6600: Load/Store Architecture Separate instructions manipulate three register types - 8, 60-bit data registers - 8, 18-bit ess registers - 8, 18-bit index registers Arithmetic and logic instructions are reg-to-reg - Hardwired control, no microcoding - Dynamic instruction scheduling with a scoreboard opcode i j k Ri (Rj) op (Rk) Only load and store instructions refer to memory opcode i j disp Ri M[(Rj) + disp] ECE 552 / CPS 550 8

8 Performance Factors Latency = (Instructions / Program) x (Cycles / Instruction) x (Seconds / Cycle) - Instructions per program depends on source code, compiler technology, ISA - Cycles per instruction (CPI) depends on the ISA and the microarchitecture - Time per cycle depends on the microarchitecture, underlying technology Microarchitecture Cycles/Instruction Seconds/Cycle Microcoded >1 short Single-cycle unpipelined 1 long Pipelined 1 short - This lecture presents single-cycle unpipelined microarchitecture ECE 552 / CPS

9 Decoder Hardware Elements Combinational Circuits - Mux, Decoder,,... Sel OpSelect - Add, Sub,... - And, Or, Xor, Not,... - GT, LT, EQ, Zero,... A 0 A 1 A n-1. Mux lg(n) O A lg(n). O 0 O 1 O n-1 A B Result Comp? Synchronous State Elements - Flipflop, Register, Register file, SRAM, DRAM - Edge-triggered elements where data is sampled on rising edge D Clk En Clk ff En D Q Q ECE 552 / CPS

10 Register Files Register D 0 D 1 D 2... D n-1 En Clk ff ff ff... ff Q 0 Q 1 Q 2... Q n-1 Register File 2R+1W Clock WE ReadSel1 ReadSel2 rs1 rs2 rd1 rd2 ReadData1 ReadData2 WriteSel WriteData ws wd ECE 552 / CPS

11 Register Files ws wd rd1 rd reg 0 rs1 5 rs2 5 reg 1 reg 31 Highly ported register files difficult to design - Almost all MIPS instructions have exactly 2 register source operands - Intel s Itanium, GPR File has 128 registers with 8 read ports, 4 write ports!!! ECE 552 / CPS

12 Simple Model WriteEnable Clock Address WriteData MAGIC RAM ReadData Reads, Writes complete in one cycle - Read can be done any time (i.e. combinational) - Write is performed at the rising clock edge if it is enabled - Write ess and data must be stable at the clock edge ECE 552 / CPS

13 MIPS Instruction Set Architecture Processor State bit GPRs, R0 always contains a 0-32 single precision FPRs, may also be vied as16 double precision FPRs - FP status register, used for FP compares & exceptions - PC, the program counter - some other special registers Data types - 8-bit byte, 16-bit half word - 32-bit word for integers - 32-bit word for single precision floating point - 64-bit word for double precision floating point Load/Store style instruction set - data essing modes- immediate & indexed - branch essing modes- PC relative & register indirect - byte essable memory- big endian mode All instructions are 32 bits ECE 552 / CPS

14 Instruction Execution 1. Instruction Fetch 2. Decode and register access 3. operation 4. operation (optional) 5. Write back And the computation of the ess of the next instruction ECE 552 / CPS

15 Reg-Reg Instructions 0x4 Add RegWrite PC inst Inst. inst<25:21> inst<20:16> inst<15:11> rs1 rs2 rd1 ws wd rd2 GPRs z inst<5:0> Control OpCode rs rt rd 0 func rd (rs) func (rt) ECE 552 / CPS

16 Reg-Imm Instructions 0x4 Add RegWrite PC inst Inst. inst<25:21> inst<20:16> inst<15:0> inst<31:26> rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z OpCode ExtSel opcode rs rt immediate rt (rs) op immediate ECE 552 / CPS

17 Conflicts in Merging Datapath PC 0x4 Add inst Inst. inst<25:21> inst<20:16> inst<15:11> inst<15:0> inst<31:26> inst<5:0> RegWrite rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z Introduce muxes OpCode ExtSel rs rt rd 0 func rd (rs) func (rt) opcode rs rt immediate rt (rs) op immediate ECE 552 / CPS

18 Instructions 0x4 Add RegWrite PC inst Inst. <25:21> <20:16> <15:11> <15:0> rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext z <31:26>, <5:0> Control rs rt rd 0 func rd (rs) func (rt) opcode rs rt immediate rt (rs) op immediate ECE 552 / CPS

19 Load/Store Instructions (Harvard) PC 0x4 Add inst Inst. base disp RegWrite rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z MemWrite rdata Data wdata WBSrc / Mem OpCode RegDst ExtSel OpSel BSrc essing mode opcode rs rt displacement (rs) + displacement rs is the base register rt is the destination of a Load or the source for a Store ECE 552 / CPS

20 MIPS Control Instructions Conditional PC-relative branch opcode rs offset BEQZ, BNEZ Unconditional register-indirect jumps opcode rs JR, JALR Unconditional absolute jumps 6 26 opcode target J, JAL PC-relative Branches (BEQZ, BNEZ) PC [offset 4] + [PC+4]; Range is 128 KB Absolute Jumps (J) PC concat(pc<31:28>, [targetx4]); Range is 256MB Jump-&-link (JAL) R31 PC+4; PC concat(pc<31:28>, [targetx4]); Range is 256MB ECE 552 / CPS

21 Conditional Branches (BEQZ, BNEZ) PCSrc br RegWrite MemWrite WBSrc pc+4 0x4 Add Add PC inst Inst. rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z rdata Data wdata OpCode RegDst ExtSel OpSel BSrc zero? ECE 552 / CPS

22 Register-Indirect Jumps (JR) PCSrc br rind RegWrite MemWrite WBSrc pc+4 0x4 Add Add PC inst Inst. rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z rdata Data wdata OpCode RegDst ExtSel OpSel BSrc zero? ECE 552 / CPS

23 Jump & Link (JALR) PCSrc br rind RegWrite MemWrite WBSrc pc+4 0x4 Add Add PC inst Inst. 31 rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z rdata Data wdata OpCode RegDst ExtSel OpSel BSrc zero? ECE 552 / CPS

24 Absolute Jumps (J, JAL) PCSrc br rind jabs pc+4 RegWrite MemWrite WBSrc 0x4 Add Add PC inst Inst. 31 rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z rdata Data wdata OpCode RegDst ExtSel OpSel BSrc zero? ECE 552 / CPS

25 Harvard Datapath for MIPS PCSrc br rind jabs pc+4 RegWrite MemWrite WBSrc 0x4 Add Add PC inst Inst. 31 rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext Control z rdata Data wdata OpCode RegDst ExtSel OpSel BSrc zero? ECE 552 / CPS

26 Hardwired Control op code zero? combinational logic ExtSel BSrc OpSel MemWrite WBSrc RegDst RegWrite PCSrc Hardware control is pure combinational logic ECE 552 / CPS

27 Hardwired Control Table Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc i iu LW SW BEQZ z=0 BEQZ z=1 J JAL JR JALR * Reg Func no yes rd sext 16 Imm Op no yes rt pc+4 uext 16 Imm Op no yes rt pc+4 sext 16 Imm + no yes Mem rt pc+4 sext 16 Imm + yes no * * pc+4 sext 16 * 0? no no * * sext 16 * 0? no no * * * * * no no * * pc+4 pc+4 jabs * * * no yes PC R31 jabs * * * no no * * rind * * * no yes PC R31 rind br BSrc = Reg / Imm RegDst = rt / rd / R31 WBSrc = / Mem / PC PCSrc = pc+4 / br / rind / jabs ECE 552 / CPS

28 Harvard Control for MIPS Assumptions - Clock period is sufficiently long to complete: 1. instruction fetch 2. decode and register access 3. operation 4. data fetch if required 5. register write-back setup time - t C > t IFetch + t RFetch + t + t DMem + t RWB Update at end of Cycle - Updates occur on rising edge of following clock - Update architectural state - Program counter (PC), register file, memory ECE 552 / CPS

29 An Ideal Pipeline stage 1 stage 2 stage 3 stage 4 All objects go through the same stages No sharing of resources beten any two stages Propagation delay through all pipeline stages is equal Scheduling of an object entering the pipeline is not affected by objects in other stages These conditions hold for industrial assembly lines but do they hold for an instruction pipeline? ECE 552 / CPS

30 Pipelining for MIPS Strategy - First, build MIPS without pipelining, CPI = 1 - Then, add pipeline registers to reduce cycle time, maintaining CPI=1 - Clock period reduced by dividing the execution of an instruction into multiple cycles, t C > max {t IM, t RF, t, t DM, t RW } ( = t DM probably) - Hover, CPI will increase unless instructions are pipelined 0x4 PC Add rdata Inst. IR rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext rdata Data wdata fetch phase decode & Reg-fetch phase execute phase memory phase write -back phase ECE 552 / CPS

31 Dividing Datapath into Stages Suppose memory is slor than other stages. Since slost stage determines the clock, it may be possible to combine stages without loss of performance t IM t DM t t RF t RW = 10 units = 10 units = 5 units = 1 unit = 1 unit ECE 552 / CPS

32 Pipelining Example 0x4 PC Add rdata Inst. IR rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext rdata Data wdata fetch phase decode & Reg-fetch phase execute phase memory phase write -back phase - Write-back requires much less time, combine with memory access - t C > max {t IM, t RF + t, t DM + t RW } = t DM + t RW ECE 552 / CPS

33 Pipelining Speedup Assumptions Unpipelined t C Unpipelined t C Speedup t IM = t DM = 10; t = 5, t RF = t RW = 1 4-stage pipeline t IM = t DM = t = t RF = t RW = stage pipeline t IM = t DM = t = t RF = t RW = stage pipeline Higher speedup possible w/ more pipeline stages ECE 552 / CPS

34 Summary Microcoding became less attractive as gap beten RAM and ROM speeds Complex instruction sets difficult to pipeline, so it was difficult to increase performance as gate count grew Processor performance depends on (a) instructions per program, (b) cycles per instruction and (c) time per cycle Load/Store RISC instruction sets designed for efficient, pipelined implementations ECE 552 / CPS

35 Acknowledgements These slides contain material developed and copyright by - Arvind (MIT) - Krste Asanovic (MIT/UCB) - Joel Emer (Intel/MIT) - James Hoe (CMU) - John Kubiatowicz (UCB) - Alvin Lebeck (Duke) - David Patterson (UCB) - Daniel Sorin (Duke) ECE 552 / CPS