CPE 335 Computer Organization. Basic MIPS Architecture Part I

Transcription

1 CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides CPE232 Basic MIPS Architecture

2 The Processor: Datapath & Control Our implementation ti of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j Generic implementation ti use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) decode the instruction (and read registers) execute the instruction Execute Fetch PC = PC+4 Decode All instructions (except j) use the after reading the registers How? memory-reference? arithmetic? control flow? CPE232 Basic MIPS Architecture 2

3 Clocking Methodologies The clocking methodology defines when signals can be read and when they are written An edge-triggered methodology Typical execution read contents of state elements send values through combinational logic write results to one or more state elements State element Combinational logic State element 2 clock one clock cycle Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs CPE232 Basic MIPS Architecture 3

4 Fetching s Fetching instructions involves reading the instruction from the updating the PC to hold the address of the next instruction 4 PC ress PC is updated d every cycle, so it does not need an explicit it write control signal is read every cycle, so it doesn t need an explicit read control signal CPE232 Basic MIPS Architecture 4

5 Decoding s Decoding instructions involves sending the fetched instruction s opcode and function field bits to the control unit Control Unit r r 2 Register File Write r Data Data 2 reading two values from the Register File - Register File addresses are contained in the instruction CPE232 Basic MIPS Architecture 5

6 Register File CPE232 Basic MIPS Architecture 6

7 Register File Ports Use two multiplexers l whose control lines are the register numbers. CPE232 Basic MIPS Architecture 7

8 Register File Write Port We need 5-to-32 decoder in addition to the Write signal to generate actual write signal The register data is common to all registers CPE232 Basic MIPS Architecture 8

9 Executing R Format Operations Rf format operations (add, sub, slt, and, or) ) R-type: op rs rt rd shamt funct perform the (op and funct) operation on values in rs and rt store the result back into the Register File (into location rd) RegWrite control r dr 2 Register Write r File Data Data 2 overflow zero The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File CPE232 Basic MIPS Architecture 9

10 Executing Load and Store Operations Load and store operations involves compute memory address by adding the base register (read from the Register File during decode) to the 6-bit signed-extended offset field in the instruction store value (read from the Register File during decode) written to the Data load value, read from the Data, written to the Register File RegWrite control MemWrite r Register dr 2 Data File Write r Data 2 overflow zero ress Data Data Sign 6 Extend 32 Mem CPE232 Basic MIPS Architecture

11 Executing Branch Operations Branch operations involves compare the operands read from the Register File during decode for equality (zero output) compute the branch target address by adding the updated PC to the 6-bit signed-extended offset field in the instr 4 Shift left 2 Branch target address control PC r Register r 2 Data File Write r Data 2 zero (to branch control logic) Sign 6 Extend 32 CPE232 Basic MIPS Architecture

12 Executing Jump Operations Jump operation involves replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits PC 4 ress ti 26 Shift left Jump address CPE232 Basic MIPS Architecture 2

13 Creating a Single Datapath from the Parts Assemble the datapath segments and add control lines and multiplexors as needed Single cycle design fetch, decode and execute each instructions in one clock cycle no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate and Data, several adders) multiplexors needed at the input of shared elements with control lines to do the selection write signals to control writing to the Register File and Data Cycle time is determined by length of the longest path CPE232 Basic MIPS Architecture 3

14 Fetch, R, and Access Portions PC 4 ress RegWrite r Register r 2 Data File Write r Data 2 Src control ovf zero MemWrite MemtoReg ress Data Data Sign 6 Extend 32 Mem CPE232 Basic MIPS Architecture 4

15 ing the Control Selecting the operations to perform (, Register File and read/write) Controlling the flow of data (multiplexor inputs) R-type: op rs rt rd shamt funct Observations I-Type: op rs rt address offset op field always 3 25 in bits 3-26 J-type: op target address address of registers to be read are always specified by the rs field (bits 25-2) 2) and rt field (bits 2-6); for lw and sw rs is the base register addr. of register to be written is in one of two places in rt (bits 2-6) for lw; in rd (bits 5-) for R-type instructions offset for beq, lw, and sw always in bits 5- CPE232 Basic MIPS Architecture 5

16 Single Cycle Datapath with Control Unit 4 Shift left 2 Op Branch Instr[3-26] Control Unit Src PCSrc Mem MemtoReg MemWrite PC ress Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] RegWrite r Register r 2 Data File Write r Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CPE232 Basic MIPS Architecture 6

17 Signal Single NameCycle Effect when Datapath deassereted with () Control Effect when Unit asserted () RegDst The destination register is from rt The destination register is from rd field field RegWrite None Enable writing to the register selected by the Write register port Src The second operand comes The second operand is the sign from the second register file extended offset output PCSrc PC value is PC+4 PC is the branch address Mem None Contents of memory address are put on data output MemWrite None Data on the Write data input is placed in the specified address MemtoReg The data fed to the register file The data fed to the register file Write Write data input comes from data input comes from memory Op Used with the function field of the instruction to generate the Op signal that t specify the operation CPE232 Basic MIPS Architecture 7

18 R-type Data/Control Flow 4 Shift left 2 Op Branch Instr[3-26] Control Unit Src PCSrc Mem MemtoReg MemWrite PC ress Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] RegWrite r Register r 2 Data File Write r Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CPE232 Basic MIPS Architecture 8

19 Load Word Data/Control Flow 4 Shift left 2 Op Branch Instr[3-26] Control Unit Src PCSrc Mem MemtoReg MemWrite PC ress Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] RegWrite r Register r 2 Data File Write r Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CPE232 Basic MIPS Architecture 9

20 Branch Data/Control Flow 4 Shift left 2 Op Branch Instr[3-26] Control Unit Src PCSrc Mem MemtoReg MemWrite PC ress Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] RegWrite r Register r 2 Data File Write r Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CPE232 Basic MIPS Architecture 2

21 ing the Jump Operation 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Control Unit PC+4[3-28] Branch Jump Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC Instr[3-] ress RegDst Instr[25-2] Instr[2-6] Instr[5 -] RegWrite r Register r 2 Data File Write r Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CPE232 Basic MIPS Architecture 2

22 Control Unit The input is the Op field (6 bits) from the instruction register The output is 9 control signals CPE232 Basic MIPS Architecture 22

23 Control Unit - Implementation Implementation using PLA CPE232 Basic MIPS Architecture 23

24 Control The control has two inputs:. Op (2 bits) from the control unit 2. Funct field (6 bits) from the instruction register The control has a 3-bit output Function Bnegate Operation and or add sub slt CPE232 Basic MIPS Architecture 24

25 Control Inst Op Funct Bnegate Operation<> Operation<> and or add sub slt lw n/a sw n/a beq n/a CPE232 Basic MIPS Architecture 25

26 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instruction especially problematic for more complex instructions like floating point multiply Clk Cycle Cycle 2 lw sw Waste May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but Is simple and easy to understand CPE232 Basic MIPS Architecture 26

27 Single Cycle Machine Performance Example: consider the following two implementations single cycle machine: A : all instructions execute in one cycle of fixed length. B : clock cycle adapts to instruction type Compare the performance of the two implementations assuming operation times for the functional units and the instruction mix given below. Unit Time (ps) 2 and adders Register File 5 Percentage % type 45 Load 25 Store Branch 5 Jump 5 CPE232 Basic MIPS Architecture 27

28 Single Cycle Machine Performance CPU Execution Time = IC x CPI x Clock cycle time CPI A = CPI B = and IC A = IC B The only difference is in clock cycle time Type Functional Units Used R-type Register Register Load Register Register Store Register Branch Register Jump Type Inst. Register Data Register Write Total R-type Load Store Branch Jump 2 2 CPE232 Basic MIPS Architecture 28

29 Single Cycle Machine Performance The clock cycle time for implementation A is 6 ps The average clock cycle time for implementation B is 6 x x. + 4 x x x.5 = ps Performanc B / Performance A = 6 / =.34 So, adaptive clock cycle is faster; however it is hard to implement! Solution : use shorter clock cycle that does less work and then use different number of cycles for different instructions CPE232 Basic MIPS Architecture 29