CSCI-564 Advanced Computer Architecture

Transcription

1 CSCI-564 Advanced Computer Architecture Lecture 6: Pipelining Review Bo Wu Colorado School of Mines

2 Wake up! Time to do laundry!

3 The Laundry Analogy Place one dirty load of clothes in the washer When the washer is finished, place the t load in the dryer When the dryer is finished, take out the dry clothes and fold When folding is finished, ask your roommate (?) to put the clothes away

4 Pipelining Multiple Loads of Laundry

5 Question: We have a four-stage pipeline. Every stage takes 1 hour. How long does it take to finish 100 loads?

6 Question: We have a four-stage pipeline. Every stage takes 1 hour. How long does it take to finish 100 loads? Question: We have a four-stage pipeline. Every stage takes 1 hour. How long does it take to finish N loads?

7 In Reality, maybe

8 Pipelining is Everywhere Build frame Install parts Paint Build frame Install parts Paint Build frame Install parts Paint

9 Pipelining is Everywhere Build frame Install parts Paint Build frame Install parts Paint Build frame Install parts Paint Build frame Install parts Paint Build frame Install parts Paint Build frame Install parts Paint

10 An Ideal Pipeline stage 1 stage 2 stage 3 stage 4 All objects go through the same stages No sharing of resources beten any two stages Propagation delay through all pipeline stages is equal Scheduling of a transaction entering the pipeline is not affected by the transactions in other stages These conditions generally hold for industry assembly lines, but instructions depend on each other causing various hazards 10

11 The Instruction Execution Cycle

12 Unpipelined Datapath for MIPS 12 0x4 RegWrite Add Add clk WBSrc MemWrite wdata Data RegDst BSrc ExtSel OpCode z OpSel clk zero? clk inst Inst. PC rd1 GPRs rs1 rs2 ws wd rd2 Imm Ext ALU ALU Control 31 PCSrc br rind jabs pc+4

13 Simplified Unpipelined Datapath 0x4 PC Add Inst. rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Data wdata 13

14 Pipelined Datapath 0x4 PC Add Inst. IR rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Data wdata fetch decode & registerfetch execute memory Clock period can be reduced by dividing the execution of an instruction into multiple cycles t C > max {t IM, t RF, t ALU, t DM, t RW } ( = t DM probably) write -back 14

15 Pipelined Control PC 0x4 Add Inst. IR Hardwired Controller rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Data wdata fetch decode & registerfetch execute memory Clock period can be reduced by dividing the execution of an instruction into multiple cycles t C > max {t IM, t RF, t ALU, t DM, t RW } ( = t DM probably) Hover, CPI will increase unless instructions are pipelined write -back 16

16 Pipelined Control PC 0x4 Add Inst. IR Hardwired Controller rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Data wdata fetch decode & registerfetch execute memory Clock period can be reduced by dividing the execution of an instruction into multiple cycles t C > max {t IM, t RF, t ALU, t DM, t RW } ( = t DM probably) Hover, CPI will increase unless instructions are pipelined write -back 18

17 Technology Assumptions A small amount of very fast memory (caches) backed up by a large, slor memory Fast ALU (at least for integers) Multiported Register files (slor!) Thus, the following timing assumption is reasonable t IM t RF t ALU t DM t RW A 5-stage pipeline will be the focus of our detailed design - some commercial designs have over 30 pipeline stages to do an integer add! 23

18 Pipeline Diagrams PC 0x4 Add Inst. IR Hardwired Controller rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext ALU Data wdata fetch decode & registerfetch execute memory write -back We need some way to show multiple simultaneous transactions in both space and time 24

19 Pipeline Diagrams: Transactions vs. Time PC 0x4 Add Inst. fetch IR Hardwired Controller rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext decode & registerfetch ALU execute Data wdata memory time t0 t1 t2 t3 t4 t5 t6 t7.... instruction1 IF 1 ID 1 EX 1 MA 1 WB 1 instruction2 IF 2 ID 2 EX 2 MA 2 WB 2 instruction3 IF 3 ID 3 EX 3 MA 3 WB 3 instruction4 IF 4 ID 4 EX 4 MA 4 WB 4 instruction5 IF 5 ID 5 EX 5 MA 5 WB 5 write -back 25

20 Pipeline Diagrams: Space vs. Time PC 0x4 Add Inst. fetch Resources IR Hardwired Controller rs1 rs2 rd1 ws wd rd2 GPRs Imm Ext decode & registerfetch ALU execute Data wdata memory time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 I 2 I 3 I 4 I 5 ID I 1 I 2 I 3 I 4 I 5 EX I 1 I 2 I 3 I 4 I 5 MA I 1 I 2 I 3 I 4 I 5 WB I 1 I 2 I 3 I 4 I 5 write -back 26