Digital Integrated Circuits

Transcription

1 Digital Integrated Circuits Term Project v0.95 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University

2 Term Project Dealing with real-world designs/problems Analyze and learn well-designed systems and codes Point to what you should learn even after this course Make what you can show off (for your interview) Do not write from scratch Modify existing modules and integrate Taking advantage of open-source hardware Dealing with more real-world designs/problems Mix & Match Chung EPC6055 2

3 Term Projects A team consists of up to 3 people Choose one of the given topics Team s project should be standalone If done, move on Mix & Match phase Mix & Match phase More than two teams work together based on their individual projects, creating a more complex system A large, extra credit will be awarded Grading Projects will be ranked within the same topic Difference of difficulty between topics will be adjusted Chung EPC6055 3

4 Deliverables Deliverables Proposal Presentation Slides Source codes Final reports Chung EPC6055 4

5 Topics (difficult) RISC-V core & System bus (new in 2017) (difficult) Matrix Multiplication (new in 2017) (moderate) CIS Controller (FPGA needed, up to 10 teams) (moderate) VGA Controller (FPGA needed) (moderate) UART (FPGA needed) (easiest) LAVA2 Chung EPC6055 5

6 CIS Controller OmniVision OV7670 Camera Module Reading materials Reference code Camera/CameraSetup.v Camera/OV7670Init.v Camera/RGB565Receive.v Camera/SCCBCtrl.v Chung EPC6055 6

7 CIS Controller Examples FPGA Image Data Initialize via SCCB CIS ctrl fnd ctrl Chung EPC6055 7

8 OV7670 Pin Numbers ##### Camera ##### NET "ca_vdd" LOC = "C26" IOSTANDARD=LVCMOS33 ; NET "ca_sioc" LOC = "E23" IOSTANDARD=LVCMOS33; NET "ca_vsync" LOC = "D26" IOSTANDARD=LVCMOS33; NET "ca_pclk" LOC = "E26" IOSTANDARD=LVCMOS33 SLEW=SLOW CLOCK_DEDICATED_ROUTE = FALSE; NET "ca_data<7>" LOC = "G21" IOSTANDARD=LVCMOS33 ; NET "ca_data<5>" LOC = "F24" IOSTANDARD=LVCMOS33 ; NET "ca_data<3>" LOC = "G23" IOSTANDARD=LVCMOS33 ; NET "ca_data<1>" LOC = "G25" IOSTANDARD=LVCMOS33 ; #NET "ca_pwdn" LOC = H20" IOSTANDARD=LVCMOS33 ; ##### put 1'b0 to pwdn NET "ca_gnd" LOC = F22" IOSTANDARD=LVCMOS33 ; NET "ca_siod" LOC = "E24" IOSTANDARD=LVCMOS33 PULLUP ; NET "ca_href" LOC = "E25" IOSTANDARD=LVCMOS33; NET "ca_xclk" LOC = "G20" IOSTANDARD=LVCMOS33 ; NET "ca_data<6>" LOC = "F23" IOSTANDARD=LVCMOS33 ; NET "ca_data<4>" LOC = "G22" IOSTANDARD=LVCMOS33 ; NET "ca_data<2>" LOC = "F26" IOSTANDARD=LVCMOS33 ; NET "ca_data<0>" LOC = "G26" IOSTANDARD=LVCMOS33 ; #NET "ca_rst" LOC = H21" IOSTANDARD=LVCMOS33 ; #### The OV7670 which have 18 pins need to set "ca_pwdn" and "ca_rst" Chung EPC6055 8

9 To set OV7670 on Ext. port of FPGA Chung EPC6055 9

10 FND Pin Map Chung EPC

11 RISC-V Core RISC-V Recommended for who took computer architecture Reading Materials: Should be interested in computer architecture Should be familiar with Linux Chung EPC

12 RISC-V Core Things you can do 1) Generate your CPU cores with the tools provided 2) Write a simple test program in assembly or C 3) Run RTL Simulation 4) Try to synthesize verilog using vivado and run a program on FPGA Chung EPC

13 Matrix Multiplication Matrix Multiplication is a fundamental operation in artificial intelligence (AI) You are to design an efficient MM hardware unit = Chung EPC

14 Broadcast-based col vector 1 col vector 2 col vector n Row vector 1 Inner Product Row vector 2 Row vector n Chung EPC

15 Systolic Array col vector 1 col vector 2 col vector n Row vector 1 Row vector 2 Row vector n Chung EPC

16 Google s TPU Chung EPC

17 References Design and Analysis of a Hardware CNN Accelerator Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network Chung EPC

18 VGA Controller VGA controller Reading material and source codes: FPGA PROTOTYPING BY VERILOG EXAMPLES, Pong P. Chu (You can find PDF by googling) Chapter 13, VGA Controller I Chung EPC

19 VGA Controller Examples Chung EPC

20 VGA Pin Numbers ##### VGA ###### NET "B<0>" LOC = "G9"; NET "B<1>" LOC = "F9"; NET "B<2>" LOC = "E9"; NET "B<3>" LOC = "D9"; NET "B<4>" LOC = "F5"; NET "B<5>" LOC = "F6"; NET "B<6>" LOC = "E3"; NET "B<7>" LOC = "E4"; NET "G<0>" LOC = "D2"; NET "G<1>" LOC = "G6"; NET "G<2>" LOC = "G7"; NET "G<3>" LOC = "E1"; NET "G<4>" LOC = "E2"; NET "G<5>" LOC = "F3"; NET "G<6>" LOC = "F4"; NET "G<7>" LOC = "G4"; NET "R<0>" LOC = "G5"; NET "R<1>" LOC = "F1"; NET "R<2>" LOC = "F2"; NET "R<3>" LOC = "H6"; NET "R<4>" LOC = "G1"; NET "R<5>" LOC = "G2"; NET "R<6>" LOC = "J6"; NET "R<7>" LOC = "H3"; NET "VGA_PCLK" LOC = "R3"; NET "h_sync" LOC = "M6"; NET "v_sync" LOC = "M8"; NET "VGA_PWM" LOC ="H2"; ### put 1'b1 (like enable) NET "VGA_DEN" LOC ="K7"; #### put 1'b1 (like enable) Chung EPC

21 UART Universal Asynchronous Receiver Transmitter (UART) Common/simple way to communicate with CPUs Reading material and source codes: FPGA PROTOTYPING BY VERILOG EXAMPLES, Pong P. Chu (You can find PDF by googling) Chapter 8, UART Terminal Programs Chung EPC

22 UART Examples FPGA Terminal program keypad ctrl UART rs232 cable VGA ctrl UART B U S fnd ctrl PS2 ctrl CPU Chung EPC

23 UART Pin Numbers ##### UART ##### NET "UART_RX" LOC = "P2"; NET "UART_TX" LOC = "P3"; Chung EPC

24 ICE2 ICE2 Recommended for who took digital signal processing Not required to run it on FPGA Enhance ICE as you want Chung EPC

25 ICE2 Examples Detect a specific pattern and draw a box enclosing it as in face defectors (Study 2D Matched Filter) f Detect objects with a specific color and draw a box enclosing it as in face detectors Chung EPC

26 LAVA2 LAVA2 Recommended for who took computer architecture Not required to run it on FPGA Enhance LAVA to be more like a real-cpu Add new instructions such as branch Analyze Educational 16-bit MIPS Processor Reference Code: Chung EPC

27 Mix & match examples ARM core + UART LAVA2 + UART Camera Controller + UART VGA Controller + UART CIS Controller + VGA Controller CIS Controller + VGA Controller + ICE2 Chung EPC

28 Dual-Port Memory on FPGA To generate memory(block memory) right click menu Chung EPC

29 Dual-Port Memory on FPGA *You should remember your Location path. Chung EPC

30 Dual-Port Memory on FPGA Chung EPC

31 Dual-Port Memory on FPGA *For this example, depth is > address will be 8bits Chung EPC

32 Dual-Port Memory on FPGA * Page 2,3 and 4 are not important. Our memory is simple. * If you don t need to initialize the memory, click the Generate and pass the next two slides. * If not, refer to next slide. Chung EPC

33 Dual-Port Memory on FPGA To initialize memory * Make a file to initialize memory. File extension is coe * Refer the example file as pp_test_init.coe * Check the Load Init File and select made file. Chung EPC

34 Dual-Port Memory on FPGA You can check the initialized memory. Chung EPC

35 Dual-Port Memory on FPGA Chung EPC

36 Dual-Port Memory on FPGA Chung EPC

37 Dual-Port Memory on FPGA Open the your_memory.v Chung EPC

38 Dual-Port Memory on FPGA Refer this file, you can exactly instantiate your memory. You don t care after this line. Chung EPC

39 Dual-Port Memory on FPGA We made 2 ports memory. Lastly, fill the blank for your project. Chung EPC