A qualitative analysis of the benefits of LUTs, Processors, embedded memory and interconnect in MPSoC platforms. Kees Vissers.
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1 A qualitative analysis of the benefits of LUTs, Processors, embedded memory and interconnect in MPSoC platforms Xilinx Research
2 OUTLINE Historical Perspective Conventional FPGAs Applications and Programming Future Directions MPsoC, July 5-9, 200 2
3 FPGA, the last 10 years 1000 Memory Bandwidth Virtex-II Pro Price: 300x Speed: 20x 100 Capacity Speed Price Virtex-II Pro Capacity: 200x 10x 000x- 6000x customer value! Spartan-3 1x1 1/91 1/92 1/93 1/9 1/95 1/96 1/97 1/98 1/99 1/00 1/01 1/02 1/03 1/0 Year MPsoC, July 5-9, 200 3
4 The market 2007 ASIC/ASSP = 80 B$ NRE = 30M$ R&D = 20% revenue Revenue = 150M$ ~500 successful ASSP/ASIC $ Millions 70, 60, 50, 0, 30, 20, 10, 0 ASIC ASSP Design Starts Number of Designs (thousands) FPGA ASIC MPsoC, July 5-9, 200
5 The ultimate solution Glueless interfaces Can handle all external memory, e.g DDR RAM, QDR RAM, SRAM Can do all the processing Is fully programmable/reconfigurable in all aspects: I/O, function, memory architecture, signal level, etc ONLY Platform FPGAs can do this. MPsoC, July 5-9, 200 5
6 Processors: Itanium 2 6M 130 W (107 W typical) 3 Levels of Cache: 16k + 16k, 256K, 6M 130nm 1.5 GHz 95 percent of the 7,877 pins are for power 1,322 Specint base2000 for a single processor! Next generation: 1.7GHz and 9MByte cache! Ref: IEEE Micro April 200, vol. 2, Issue 2, pp : ITANIUM 2 PROCESSOR 6M: HIGHER FREQUENCY AND LARGER L3 CACHE, Rusu et. al, Intel. MPsoC, July 5-9, 200 6
7 Processors: DSP TI C61: 2 levels of cache Philips PNX1500 (Trimedia core): 2 levels of cache Often specific DMA, Bus architecture and optimized main memory architecture: does not easily fit the C programming paradigm. Conclusion: the memory model is a problem MPsoC, July 5-9, 200 7
8 A Von Neumann-style Computation Example 256 Tap FIR Filter Example Tap FIR Filter y n = Σ c k x K=0 n-k Register File r0 = #0 r1 = x0 r0 = r1*#c0 r1 = x1 r0 = r1*#c y0 = r1 y0 x0 x1 x2 x3... x253 x25 x255 Bottle-necks! ALU Instruction Decode MPsoC, July 5-9, 200 8
9 FIR Implementation in RC x n c c 25 c 1 Reg Reg... Reg For highest speed, use as many compute elements as problem allows. Capable of producing an output sample in one instruction cycle. Call this Spatial computing. (see DeHon) c 0 y n MPsoC, July 5-9, 200 9
10 Customizing Architecture in Full Parallel RC Tailor a solution to optimize throughput, precision and cost Semi-Parallel Serial Reg Reg MPsoC, July 5-9,
11 Architectural Efficiency Spatial vs. Temporal Computing FPGA (c=w=1) Processor (c=102, w=6) Figures courtesy of André DeHon, California Institute of Technology MPsoC, July 5-9,
12 OUTLINE Historical Perspective Conventional FPGAs Applications and Programming Technology Impact Financial Impact Future Directions MPsoC, July 5-9,
13 [A,B,C,D] Building an FPGA: Logic 16 words x 1 bit memory F First A -input lookup table (LUT) can implement any function of inputs. For example, a 1-bit adder needs 2 LUTs: B A A.B.C i A B C i Co S Ci MPsoC, July 5-9,
14 Add FF to make a Logic Cell In 16 words x 1 bit memory FF M M CE RST M Out Clk CE Rst MPsoC, July 5-9, 200 1
15 Arithmetic, Distributed RAM Cout Carry M Din WE Cin 16 words x 1 bit memory FF M M CE RST M Make LUT RAM a user resource. Fast carry ripple to neighbor. MPsoC, July 5-9,
16 Add Interconnect 0 Group logic cells to reduce overhead. Add H, V routing channels with switchboxes. Add input, output MUXing between logic and routing. MPsoC, July 5-9,
17 Build an Array MPsoC, July 5-9,
18 Putting the R in RC Fine-grained FPGAs are the platform of choice for Reconfigurable Computing. User Logic Configuration RAM State Configuration MPsoC, July 5-9,
19 Add Bells & Whistles Hard Processor Gigabit Serial 18 Bit I/O 36 Bit 18 Bit Multiplier VCCIO Z Programmable Termination MPsoC, July 5-9, 200 Z Z Impedance Control BRAM Clock Mgmt 19
20 Problem definition Perform processing on a stream of data Sampling rates in the order of 100KHz to 100MHz per sample ,000 operations Perform operations/sec, like add, multiply etc. Note: performance is a required part of the solution! MPsoC, July 5-9,
21 So when do I need what? Processor + Cache LUT Embedded Memory Bus Reconfigurable interconect Internal Memory External Memory I/O MPsoC, July 5-9,
22 OUTLINE Historical perspective Conventional FPGAs Applications and Programming Technology and Financial Impact Future Directions MPsoC, July 5-9,
23 JPEG2000 Encoder: Functional Block Diagram Tier-1 Coding Tier-2 Coding Inpu t data DC- Shift & Comp. Trans. 2-D DWT Quantize r Bit Modele r MQ Entrop y Coder Header/ Stream Creatio n Compressed data MQ Coder: Create codewords using arithmetic coding MPsoC, July 5-9,
24 JPEG2000: Run-Time Profiling 1.7%.0% 6.6% Interface 2-D DWT Tier-1 Coding Tier-2 Coding 87.8% * Run on XRL s JPEG2000 ANSI C code MPsoC, July 5-9, 200 2
25 JPEG2000 Encoder on Multimedia Board Buffer 1 Buffer 2 Buffer 3 YCrCb RGB Frame Capture ZBT Memor y 32 ZBT Memor y Multi-Memory / Multi-Port ZBT Interface 32 Multi-Pass DWT ZBT Memor y 32 Tier 1 Coder Tier 1 Tier-1 Coder Logic Coder DMA 32 bit Processo r Memory DATA Arbite r/ Bridge Processo r Memory INSTRU CT Interrupt request (IR) IR Data OPB Bus IR MicroBlaz e/ OPB Bus MPsoC, July 5-9,
26 From Off- Chip DWT Buffer Sign- Mag N Convert & Sticky Bits Tier-1 Coder: Block Diagram [Original Design] N BRAMs 096 x Nb [signmagnitud e] N-1 N Bit C ModelingX Flags D Tier-1 Coding Control FIFO 208 x 8b MQ Arithmet ic Coder 32 Memory FPGA Fabric FIFO 102 x 32b [bytestream ] To Off- Chip Comp. Buffer BRAMs 2 x 102 x b Magnitude Bit Planes BRAM 102 x b Sign Bit Plane BRAM 102 x 16b Significance/ Process Flags Dist. RAM 19 x 7b Dist. ROM 7 x 29b Index/MPS Probability/ Table Next State Table MPsoC, July 5-9,
27 JPEG2000 Example 2-D DWT Arithmetic Encoder Bit Modeler Technology Application Performance FPGA 1 60 x 30 fps DSP Processor x 8 fps ASIC x 30 fps Input Data Rate (Msamples/sec) Compression Ratio System Clock Rate (MHz) : : N/A 27 Sources: 1 Schumacher 2 Aware Inc. 3 Yamauchi MPsoC, July 5-9,
28 Power Efficiency Results Technology Power Dissipation (in Watts) Device External Memory Total Relative Power Efficiency (Relative MOPS/mW) FPGA DSP Processor ASIC FPGA has 8x efficiency of processor 1 x throughput 1/10 x system clock More on-board memory would help. Look for evolving memory hierarchies. MPsoC, July 5-9,
29 Job Farm w/ Eight MicroBlazes Block Ram Block Ram Block Ram Block Ram Block Ram Block Ram Block Ram Block Ram Micro Blaze 0 Micro Blaze 1 Micro Blaze 2 Micro Blaze 3 Micro Blaze Micro Blaze 5 Micro Blaze 6 Micro Blaze 7 OPB Timer UART HW Semaphore Job Farm Information Job 1 Job 2 Job 3 Job Job 5 Job 6 Job N Image Data ZBT Memory MPsoC, July 5-9,
30 Multiple MicroBlaze DWT Results Speedup Processors MPsoC, July 5-9,
31 Job Farm Make sure the bus or the internal network can handle the required bandwidth Make sure that the latency is under control: drive towards multi-threading/multi context The granularity of the communication matters MPsoC, July 5-9,
32 OUTLINE Historical perspective Conventional FPGAs Applications and Programming Future Directions MPsoC, July 5-9,
33 System Generator for DSP Library-based, visual data flow Polymorphic operators Arbitrary precision fixed-point Bit and cycle true modeling Seamlessly integrated with Simulink and MATLAB Test bench and data analysis Automatic code generation Synthesizable VHDL IP cores HDL test bench Project and constraint files MPsoC, July 5-9,
34 System Generator for DSP System Generator for DSP v3.1 Allows Systems Designers to target external simulation engines - Hardware in the loop - HDL co-simulation Hardware in the loop co-simulation Allows the user to simulate part of his system on actual hardware. This means acceleration & verification HDL co-simulation using ModelSim Allows the user automatically invoke ModelSim and simulate his Verilog/VHDL directly from Simulink. MPsoC, July 5-9, 200 3
35 Documented Reference Designs 16-QAM receiver, including LMS based equalizer and carrier recovery loop A/D and delta-sigma D/A conversion Concatenated FEC codec for DVB Custom FIR filter reference library Digital down converter for GSM 2D discrete wavelet transform (DWT) filter 2D filtering using a 5x5 operator Color space conversion CORDIC reference design Polyphase MAC-based FIR Streaming FFT/IFFT BER Tester using AWGN model MPsoC, July 5-9,
36 OUTLINE Historical Perspective Conventional FPGAs Applications and Programming Technology and Financial Impact Future Directions MPsoC, July 5-9,
37 The mix revisited Processor + Cache LUT Embedded Memory Bus Reconfigurable interconect Internal Memory External Memory I/O MPsoC, July 5-9,
38 The Future : Domain Optimized Programmable Platforms Programmable mass market of one Parallelism performance and power Scalable ride Moore s Law Distributed memory data transfer bottleneck Regular manufacturable Domain optimized cost Hyper-programming more degrees of freedom, spatial computing Virtex- LX Logic Platform Virtex- SX DSP Platform Virtex- FX Connectivity Platform Logic Domain Logic density DSP Domain DSP performance MPsoC, July 5-9, Processing Domain Compute and IO performance
39 The Characteristics 500MHz DCM Digital Clock Management 500MHz Flexible Logic Architecture 500MHz multi-port Distributed RAM 500MHz Programmable DSP Execution Units 50MHz PowerPC Processor With Auxiliary Processor Unit 1Gbps Differential I/O Gbps Serial Transceivers MPsoC, July 5-9,
40 The tool we need External SRAM Current Frame Display Controller Output Image Blocks Software Orchestrator Current Frame Memory Controller Input stream 8 FIFO 8 Decode Headers (VOL, VOP) 1 VLD DMUX MPEG- Decoder 1 1 Coeffs and DC Motion Decoder Texture VL Decoder Object FIFO Motion Vectors FIFO Inverse Scan Inverse AC DC Prediction Motion Motion Compensation Vectors 8 8 Block FIFO DCT Coeff Object FIFO 8 8 Block Not Coded Inverse Quantisation / IDCT 8x8 Block 8 8 Block Object FIFO 8 8 Block MPsoC, July 5-9, 200 0
41 Acknowledgements The author gratefully acknowledges the contributions of material, insight and feedback from: David Parlour, Steve Trimberger, Robert Turney, Paul Schumacher, Rick Ballantyne, Mark Paluszkiewicz- Xilinx Research Labs André DeHon - California Institute of Technology Kristof Denolf, Adrian Chirila-Rus, Bart Vanhoof, Jan Bormans - IMEC MPsoC, July 5-9, 200 1
42 University donations xup/ubroch/qform.htm ML310/ml310_mainpage. html MPsoC, July 5-9, 200 2
43 What is it? MPsoC, July 5-9, 200 3
44 Box MPsoC, July 5-9, 200
45 Board MPsoC, July 5-9, 200 5
46 Block Diagram MPsoC, July 5-9, 200 6
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