EMTECH_3P_A_1_v4. Descripción de la placa.
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1 EMTECH_3P_A_1_v4 Descripción de la placa. Autor Hidalgo Martin Versión 0.1 Ultima revisión Lunes, 04 de Abril de 2011
2 Contenido 1 Introducción Descripción de la placa Vista superior Vista Inferior Componentes en la placa Requerimientos Conexiones en la placa FPGA ProASIC3 Flash Family Fugas with Optional Soft ARM Support Dimensiones...10 Página 2 de 10
3 Revisiones Fecha Versión Modificaciones 0.1 Versión original Página 3 de 10
4 1 Introducción En este documento se describe las características de la placa, componentes existentes e interfaces entre ellos y el usuario. Con este documento podemos analizar el alcance y posibilidades de desarrollo utilizando a 3P_A_1_v4. Siguiendo con el propósito del proyecto original, para esta cuarta versión de la 3PA1 se realizo un nuevo mapeo de los pines libres para las FPGAs de encapsulado PQ208. Se agregaron 2 conectores más de 10 pines manteniendo la compatibilidad con los conectores originales de las versiones anteriores. Esta nueva disposición de pines permite colocar una nueva placa hija de memorias e implementar un núcleo Cortex-M3 sobre la FPGA. Página 4 de 10
5 2 Descripción de la placa 2.1 Vista superior 2.2 Vista Inferior 1-Vista superior 2-Vista inferior Página 5 de 10
6 2.3 Componentes en la placa Dadas las posibilidades de colocar un encapsulado PQ208 o VQ100, las variables de FPGA de ACTEL que pueden soldarse en la placa son los siguientes: Power DC-DC converter 5VDC to 3.3v and 1.5v. 2.4 Requerimientos AC/DC power adapter 5VDC 2Amp 2.1mm x 5.5mm Página 6 de 10
7 2.5 Conexiones en la placa 3- esquema de conexión Página 7 de 10
8 3 FPGA ProASIC3 Flash Family Fugas with Optional Soft ARM Support Features and Benefits High Capacity 15 k to 1 M System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os Reprogrammable Flash Technology 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance 350 MHz System Performance 3.3 V, 66 MHz 64-Bit PCI In-System Programming (ISP) and Security Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC 3 devices) via JTAG (IEEE 1532 compliant) FlashLock to Secure FPGA Contents Low Power Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash Switches High-Performance Routing Hierarchy Segmented, Hierarchical Routing and Clock Structure Advanced I/O 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V Bank-Selectable I/O Voltages up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os Programmable Output Slew Rate and Drive Strength Weak Pull-Up/-Down IEEE (JTAG) Boundary Scan Test Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL Six CCC Blocks, One with an Integrated PLL Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory 1 kbit of FlashROM User Nonvolatile Memory SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks ( 1, 2, 4, 9, and 18 organizations) True Dual-Port SRAM (except 18) ARM Processor Support in ProASIC3 FPGAs M1 and M7 ProASIC3 Devices Cortex-M1 and CoreMP7 Soft Página 8 de 10
9 Processor Available with or without Debug General Description ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do not support AES decryption. Página 9 de 10
10 4 Dimensiones Página 10 de 10
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