Agenda. Programming Qualification for Rad-Tolerant Antifuse FPGAs. RT FPGA Qualification Updates. Long Term Reliability Testing

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1 Power Matters Microsemi Space FPGAs Qualification and Reliability Update Solomon Wolday Product Engineering Manager Ken O Neill Director of Marketing Microsemi SoC Products Group 2012 Microsemi Corporation.

2 Agenda Programming Qualification for Rad-Tolerant Antifuse FPGAs Reliability Test Designs Reliability Experiments S/W Versions Summary RT FPGA Qualification Updates RTAX-S/DSP QML Class V RT ProASIC3 QML Class Q Long Term Reliability Testing Aerospace Corporation and NASA GSFC 2012 Microsemi Corporation. 2

3 Reliability Designs for Antifuse RT FPGAs Multiple design types are used to address different reliability tests and coverage Qualification Burn-In (QBI): Maximizes resource utilization Enhanced Antifuse Qualification (EAQ): Uses highly perceptive and stressful designs for antifuse evaluation High Single-S and Single-B (HSB): Targets special type of antifuses Larger devices also incorporate TID and SEE blocks RTAX4000S and RTAX4000D devices Different I/O standards are utilized in each design Single ended, differential, and voltage referenced I/O s are configured Design utilizations for each type of design shown in the following slide 2012 Microsemi Corporation. 3

4 Device Utilization Microsemi SoC requirement to have a minimum of 95% utilization for each reliability design Info Pins Utilization Clocks Cells Summary Design Type Device Package I/O RCLK HCLK RAM/FIFO Carry Chain R-Cell C-Cell seq + combo Total Modules QBI + EAQ + HSB + TID RTAX4000S CG ,155 40, % QBI RTAX2000S CQ ,965 21, % EAQ RTAX2000S CQ ,666 21, % QBI RTAX2000S CG ,965 21, % EAQ RTAX2000S CG ,652 21, % EAQ RTAX2000S CG ,632 21, % QBI RTAX1000S CQ ,768 12, % EAQ RTAX1000S CQ ,027 12, % EAQ RTAX1000S CG ,010 12, % EAQ RTAX250S CQ ,388 2, % 4186 EAQ RTAX250S CQ ,397 2, % Microsemi Corporation. 4

5 QBI Design Design Overview QBI (Qualification Burn In) design Goal of this design: Maximum utilization of logic cells (with different configurations) Test all IO standards Testing of all macros offered (like Carry chain, buffys etc) Test RAM feature (in RTAX-S) Test DSP feature (in RTAX-D) QBI block also used as Quality Control Monitor (QCMON) design in smaller devices 2012 Microsemi Corporation. 5

6 QBI Design Features Top level design includes different blocks to ensure testing of all device features with maximum utilization Combinatorial Block Combo Test OK This monitor signal used during ATE testing and burn-in monitoring FIFO Block FIFO Test OK Monitor Circuit Global Test Monitor RAM Block RAM Test OK ALU Block ALU Test OK 2012 Microsemi Corporation. 6

7 EAQ Design Overview Goal of Enhanced Antifuse Qualification (EAQ) design Design used for study of antifuse reliability experiment Design fully utilized smaller devices RTAX2000S, RTAX1000S, RTAX250S, RTSX-SU Design is highly perceptive of small delay measurement deltas Multiple delay lines of combinatorial modules I/O test block RAM test blocks EAQ design is used for Enhanced Lot Acceptance (ELA) testing Samples from every wafer lot are programmed and burned in Device RTSX32SU 100 (0) RTSX72SU 100 (0) RTAX250S 100 (0) RTAX1000S 24 (0) RTAX2000S, RTAX2000D RTAX4000S, RTAX4000D ELA Sample Size 14 (0) 8 (0) 2012 Microsemi Corporation. 7

8 Top Level EAQ Diagram Array Test Block (2106 bit SR) each in 4 rows of tiles Error Flags [3:0] 4 Array Monitor Array Monitor IO Test Block 138 I/Os (414 I/O Regs) Error Flag IO_pin[0] IO_pin[138] 21 Global Monitor Global Monitor RAM Test Block (sixteen 1x16384 ram) IO_Monitor Error Flag [15:0] 16 Ram Monitor Ram out [15:0] This monitor signal used during ATE testing and burn-in monitoring Delay Chain (15 X 1170 NAND) 15 Delay_out [5:0] 2012 Microsemi Corporation. 8

9 SRAM Block Overview Embedded SRAM Blocks Full test coverage on all SRAM cells Varying depth and width configurations Pattern / Address Generator RAM_Config1 OUT Control Signal Generator (WEN / BLK / CLK) Comparator monitor Pattern / Address Generator RAM_Config2 OUT Control Signal Generator (WEN / BLK / CLK) MONITOR Comparator monitor Pattern / Address Generator RAM_confign OUT Control Signal Generator (WEN / BLK / CLK) Comparator monitor 2012 Microsemi Corporation. 9

10 I/O Test Block Scalable block for maximizing I/O utilization Utilizes all possible I/O configurations Controlled simultaneous switching outputs Exercises both input and output buffer of each I/O Pattern In D SET Q S 1 0 S D SET Q S 1 0 S D SET Q S 1 0 S D SET Q Out CLR Q CLR Q CLR Q CLR Q Clock Reset Output Enable 2012 Microsemi Corporation. 10

11 HSB Design Overview Goal of High Single-S and Single-B antifuse design Increase the utilization of Single-S and Single-B antifuse Short delay lines of combinatorial and sequential logic Multiple delay lines per device compared against each other at every burn-in pull point Delay lines shown below (All delay lines exercised during burn-in) Rclk2 gnd PRE D Q CLK CLR gnd D Q CLK CLR 56 FF stages gnd D Q CLK CLR rcell_outz_hsb_0 Rclk1 112 inv stages ccell_outz_hsb[0] Repeated 108 times enable_hsb Repeated 107 times enable_hsb gnd D CLK PRE Q gnd D Q CLK CLR 56 FF stages CLR Sequential delay lines gnd D Q CLK CLR rcell_outz_hsb_ inv stages Combinatorial delay lines ccell_outz_hsb[106] 2012 Microsemi Corporation. 11

12 SEU Combinatorial Delay Block SEU delay lines have longer delays than EAQ and HSB designs The delay line could be exercised through an input pin or a clock divider block Each delay line can be cascaded to make up one long delay line zoom_sel_n[0] zoom_sel_n[1] Clock devider zoom 1170 NAND4 inv chain Delay_out_SEU[0] 1170 NAND4 inv chain Delay_out_SEU[1] 1170 NAND4 inv chain Delay_out_SEU[2] 1170 NAND4 inv chain Delay_out_SEU[3] SEU_sel 1170 NAND4 inv chain Delay_out_SEU[4] 2012 Microsemi Corporation. 12

13 Reliability Experiments Different types of experiments performed on Microsemi SoC RT products Enhanced Lot Acceptance (ELA) Performed on every RTAX-S, RTAX-DSP and RTSX-SU wafer lot Burn-in duration of 168hrs HTOL Group C lifetest Periodic lifetest performed on yearly basis per process technology Burn-in duration of 1000hrs HTOL Class-V Grp C Performed on every Class-V wafer lot Burn-in duration of 2000hrs HTOL 2012 Microsemi Corporation. 13

14 Reliability Experiments (cont d) Customer Lifetest Burn-in duration per request by customer Normally 1000hrs or 2000hrs HTOL QBI/EAQ For qualification of new product or process change Burn-in duration of 1000hrs HTOL for QML-Q products 4000hrs HTOL for QML-V products (SoC completed 6000hrs HTOL) All above experiments performed on programmed devices Latest Sculptor S/W version utilized to program devices at the time of the reliability experiment All burn-ins performed at maximum supply and temperature conditions 2012 Microsemi Corporation. 14

15 Data Analysis Methodology All reliability testing is performed on fully processed Mil Std 883 Class B devices Test devices have completed the Mil Std 883 Class B / QML class Q production flow All functional and parametric testing is performed after programming each device Time zero testing and post burn-in testing performed at every pull-point Delta analysis is completed on all parameters delay_test_hl ( Post1000hrs Delta) delay_test_lh ( Post1000hrs Delta) Delta RPt 3 (us) Device Delta RPt 3 (us) Device Microsemi Corporation. 15

16 Overall Accumulation of Life Test Data Tracking life test data by programming software version since 2007 Started tracking with V4.68 released late 2007 Microsemi recommends using the most recent software version 12 Most Recent Releases Top 12 by Device-Hours Silicon Sculptor Software Silicon Sculptor Software Version Device-Hours Version Device-Hours V ,608 V ,704 V ,856 V ,056 V ,464 V ,608 V ,080 V ,688 V ,536 V ,080 V ,384 V ,368 V ,000 V ,520 V ,520 V ,464 V ,056 V ,536 V ,848 V ,000 V ,688 V ,376 V ,368 V , Microsemi Corporation. 16

17 RT Qualification S/W Versions Top 12 Silicon Sculptor versions vs. type of reliability experiment Type of Reliability Test Silicon Sculptor S/W Version Lifetest ELA Grp C QML-V Grp C V ,000 4,704-48,000 V ,000 7,056-96,000 V ,000 34,608 80, ,000 V ,000 44,688 80,000 96,000 V ,000 10, ,000 V ,000 46,368-50,000 V ,000 23,520 79,000 - V ,464 66,000 - V ,000 6,384 80,000 - V ,000 25,536 44,000 V ,000 - V ,000 5,376 46,000 Grand Total 303, , , , Microsemi Corporation. 17

18 Prog Software Life Test by Product RTSX-SU Device-Hours Silicon Sculptor S/W Version RTSX32SU RTSX72SU V ,800 V ,600 V ,856 V ,800 64,800 V ,800 V ,800 V ,000 V ,800 Grand Total 81, , Microsemi Corporation. 18

19 Prog Software Life Test by Product RTAX-S Device Device-Hours Device Device-Hours Device Device-Hours Device Device-Hours RTAX250S 205,400 RTAX1000S 129,640 RTAX2000S 974,712 RTAX4000S 637,072 V ,800 V ,000 V ,704 V ,000 V3.93 6,000 V ,064 V ,352 V ,520 V ,800 V ,032 V ,856 V4.74 1,344 V ,000 V ,032 V ,352 V ,520 V ,000 V ,032 V ,000 V ,344 V ,000 V ,032 V ,000 V ,344 V ,800 V ,032 V ,704 V ,000 V ,000 V ,048 V ,000 V ,000 V ,000 V ,368 V ,352 Grand Total 637,072 Grand Total 205,400 Grand Total 129,640 V ,704 V ,352 V ,408 V ,056 V ,464 V ,056 V ,352 Grand Total 974, Microsemi Corporation. 19

20 Qualification Updates RT ProASIC3 Update Industry first Flash-based non-volatile reprogrammable FPGA in space Qualification completed per Mil-STD 883B QML class Q qualification in progress, expected completion mid 2013 RTAX-S/SL/DSP Class V Update High performance, high density antifuse-based rad-tolerant FPGAs RTAX-S/SL/DSP now qualified to QML class V Devices fully compliant to QML Class V requirements All process flows and requirements put in place for production 2000hrs HTOL Group C on each wafer lot 2012 Microsemi Corporation. 20

21 RTAX-S/SL Long Term Reliability Testing Aerospace Corporation (AX2000, I-temp) Identical antifuses, processing, programming to RTAX2000S Longest runners > 38,000 hours HTOL > 26 Million device hours accumulated! Testing complete, no antifuse anomalies observed Type Devices Dev. Hrs AX2000 HTOL ,894,309 AX2000 LTOL ,011,479 AX2000 Temp Cycle 182 5,586,874 Total 26,492,662 NASA GSFC (RTAX-S) Testing completed, no anomalies observed Type Devices Dev. Hrs RTAX250S HTOL ,000 RTAX250S LTOL ,000 RTAX2000S HTOL ,000 RTAX2000S LTOL ,000 Total 984, Microsemi Corporation. 21

22 Conclusion Life test samples programmed with highly utilized and perceptive designs Reliability testing completed on each wafer lot Programming S/W versions tracked by lifetest Microsemi recommends using the latest S/W version Programming S/W version to be available online: Microsemi Corporation. 22