6502 Microprocessor Kit User's Manual

Transcription

1 650 Microprocessor Kit User's Manual

2 650 MICROPROCESSOR KIT CONTENTS OVERVIEW... FUNCTIONAL BLOCK DIAGARM... HARDWARE LAYOUT...4 KEYBOARD LAYOUT...5 HARDWARE FEATURES...6 MEMORY AND I/O MAPS...6 GPIO LED...7 CONNECTING KIT TO TERMINAL...8 EXPANSION BUS HEADER...9 0ms TICK GENERATOR...0 RSC PORT... DATA FRAME for UART COMMUNICATION... CONNECTING LCD MODULE... LOGIC PROBE POWER SUPPLY...6 WRITE YOUR OWN MONITOR PROGRAM...7 HARDWARE SCHEMATIC, BOM...8 MONITOR PROGRAM LISTINGS...

3 OVERVIEW The 650 Microprocessor kit is a new design single board computer using the G65SC0 as a CPU. This single board computer is a basic learning tool for programming the 650 with low level instructions hex code. The board has hex keypad and 7-segment display for entering the instruction hex code and test it directly. Students will learn basic of the computer hardware and software of the 650 easily. The manual also provides monitor program listings, the method to modify or write your own monitor program. 650 KIT FUNCTIONAL BLOCK DIAGRAM Notes. UART is software control for low speed asynchronous communication.. The kit provides 8-bit LCD module interfacing bus.. 00Hz Tick generator is for interrupt experiment. 4. Ports for display and keypad interfacing were built with discrete logic IC chips. 5. Memory and Port decoders are made with Programmable Logic Device, PLD.

4 HARDWARE LAYOUT RSC connector, DB9 male DC jack, +9VDC GPIO LED, 8-bit binary display (address is 40H) LCD contrast adj. 0-pin Text LCD header. Important Notes Selector for 0ms tick or IRQ key. Plugging or removing the LCD module must be done when the kit is powered off!. AC adapter should provide approx. +9VDC, higher voltage will cause the voltage regulator chip becomes hot.. The kit has diode protection for wrong polarity of adapter jack. If the center pin is not the positive (+), the diode will be reverse bias, preventing wrong polarity to feed to voltage regulator. 4

5 KEYBOARD LAYOUT HEX keys Hexadecimal number 0 to F with associated user registers, flag bits and page zero memory $00 to $09 (use with key REG) CPU control keys RESET USER IRQ Reset the CPU, the 650 will get reset vector from location FFFC and FFFD User key for lab test, active low Make IRQ pin to logic low, used for experimenting with interrupt process Monitor function keys REP INS DEL STEP GO Repeat the key that pressed, must be pressed together with REP key. N/A. N/A Execute user code only single instruction and return to save CPU registers Jump from monitor program to user code - Decrement current display address by one + Increment current display address by one PC Set current display address with user Program Counter

6 REG Display user registers, flags or page zero $00 to $09 with HEX key. DATA Set entry mode of hex keys to Data field 6 ADDR COPY REL SEND LOAD Set entry mode of hex keys to Address field N/A Compute relative byte, used with key + for Start, Destination and key GO N/A Load Intel or MOS hex file at 400 bit/s using serial port Note, N/A=not available for the current version of monitor program The hardware features are as follows; HARDWARE FEATURES CPU: 65SC0, CMOS 8-bit clock Memory: kb RAM, 6kB EPROM Memory and I/O Decoder chip: Programmable Logic Device GAL6V8D Display: 6-digit 7-segment LED Keyboard: 6 keys RS port: software controlled UART 400 bit/s 8n Debugging LED: 8-bit GPIO LED at location $8000 Tick: 0ms tick produced by 89C05 Text LCD interface: direct CPU bus interface text LCD Expansion header: 40-pin header

7 MEMORY AND I/O MAPS The first kb is RAM space from FFFH. Zero page is location 00-FFH. Stack space is 00-FFH. User space is from 00H to 7FFFH. The 650 CPU uses memory space from 8000H-BFFFH for I/O port. The monitor ROM is located at C000H-FFFFH 64kB Memory Memory mapped I/O 0000H 7FFFH 8000H 9000H kb RAM 8000H 800H 800H 800H GPIO PORT0 PORT PORT C000H FFFFH 6kB Monitor ROM 9000H 900H 900H 900H LCD command WR LCD data WR LCD command RD LCD data RD GPIO LED The 650 kit provides a useful 8-bit binary display. It can be used to debug the program or code running demonstration. The I/O address is 8000H. U4 is 8-bit data latch. Logic at the output will make LED lit.

8 The GPIO LED can be used to display accumulator register easily. Let us take a look the sample code below. Address Hex code Label Instruction comment 000 A9 0 MAIN LDA # Load register A with 00 8D STA $8000 Write A to GPIO@ 8000H The test code has only two instructions. The first instruction has two bytes machine code, A9 and 0. The second instruction has three bytes, 8D, 00 and 80. Enter the hex code to memory from 000 to 00. Then press PC, and execute the instruction with single step by pressing key STEP. The nd press STEP key that executes instruction STA $8000 will make the GPIO LED showing the content of register A. Try change the load value to register A. Another sample is with JUMP instruction. The JUMP instruction will change the Program Counter to 000, to repeat program running. Now we use zero page at location 0 to be the byte to be incremented. After incrementing, we load it to register A then write to location of GPIO at 8000H. And with JMP LOOP instruction, the program will be repeated. Address Hex code Label Instruction comment 000 E6 00 LOOP INC $0 Increment location 0 00 A5 00 LDA $0 Load A with location D STA $8000 Write A to GPIO@ 8000H 007 4C 00 0 JMP LOOP Jump back to loop Again enter the hex code to memory and test it with single step. Now press key STEP and key REP together. Every time when instruction STA $8000 was executed, did you see the binary number counting? We will learn more the use of GPIO with 650 Programming Lab Book. 8

9 CONNECTING 650 KIT TO TERMINAL For LOAD key, we can connect the 650 kit to a terminal by RSC cross cable. You may download free terminal program, teraterm from this URL, RSC cross cable VT00 Terminal 650 Kit The example shows connecting laptop with COM port to the RSC port of the 650 kit. New laptop has no COM port, we may use the USB-RS adapter for converting the USB port to RS port. To download Intel or MOS hex file that generated from the assembler or c compiler, set serial port speed to 400 bit/s, 8-data bit, no parity, no flow control, one stop bit. 9

10 Press key LOAD, then key GO. The kit will wait for the data stream from terminal. On PC, Click file>send File>LED.HEX. The kit will read the hex file, write to memory, when completed the start message will be displayed. The kit accepts for both Intel or MOS hex files. EXPANSION BUS HEADER JP, 40-pin header provides CPU bus signals for expansion or I/O interfacing. Students may learn how to make the simple I/O port, interfacing to Analog-to-Digital Converter, interfacing to stepper motor or AC power circuits. 0

11 USER KEY User key, S9 is one bit active low key switch connected to bit 6 of Port 0. To test the logic of S9, we can use instruction LDA $800 and check bit 6 of the accumulator with test bit instruction. 0ms TICK GENERATOR SW is a selector for interrupt source between key IRQ or 0ms tick produced by 89C05 microcontroller. Tick generator is software controlled using timer0 interrupt in the 89C05 chip. The active low tick signal is sent to P.7. For tick running indicator, P.7 drives D LED.

12 Tick is a 0ms periodic signal for triggering the 650 IRQ pin. When select SW to Tick, the 650 CPU can be triggered by a maskable interrupt. The 00Hz tick or 0ms tick can be used to produce tasks that executed with multiple of tick. The 650 kit lab look will show how to use 0ms tick to make a digital timer. 0ms 0ms 0ms RSC PORT The RSC port is for serial communication. We can use a cross cable or null MODEM cable to connect between the kit and terminal, or kit # to kit # for sending or receiving hex file. The connector for both sides are DB9 female. We may build or buy it from computer stores. For new PC or laptop computer with USB port, we may have the RSC port by using the USB to RS converter.

13 DATA FRAME for UART COMMUNICATION Serial data that communicated between kit and terminal is asynchronous format. The 650 kit has no UART chip, instead it uses software controlled to produce bit rate of 400 bit/s. The data frame is composed of start bit, 8-data bit and stop bit. For our kit, period = /400 = 47 microseconds. Since bit period is provided by machine cycle delay. Thus to send/receive serial data correctly, all interrupts must be disabled. CONNECTING LCD MODULE JR is 0-pin header for connecting the LCD module. The example shows connecting the 6x lines text LCD module. R is a current limit resistor for back-light. R is trimmer POT for contrast adjustment. The LCD module is interfaced to the 650 bus directly. The command and data registers are located in I/O space having address from 9000H to 900H. Be advised that plugging or removing the LCD module must be done when the kit is powered off. Text LCD module accepts ASCII codes for displaying the message on screen. Without settings the LCD by software, no characters will be displayed. The first line will be black line by adjusting the R8 for contrast adjustment.

14 Here is the example program that prints text 650 Kit on the LCD screen ; LCD test program for 650 KIT BUSY.EQU 80H ; below LCD's registers are mapped into memory space command_write.equ 9000H data_write.equ 900H command_read.equ 900H data_read.equ 900H cseg org 00h C 5A 0 jmp main ; wait until LCD ready bit set LcdReady PHA AD 0 90 ready LDA command_read AND #BUSY D0 F9 BNE ready ; loop if busy flag = B 68 PLA C 60 RTS D 00 00D 00 00D LCD_command_write 00 00D JSR LcdReady D STA command_write RTS LCD_data_write JSR LcdReady D 0 90 STA data_write A 60 RTS 004 0B 004 0B 004 0B clr_screen JSR LcdReady E A9 0 LDA # D 0 JSR LCD_command_write RTS A9 8 InitLcd LDA #8H D 0 JSR LCD_command_write A9 0C LDA #0CH 005 0B 0 0D 0 JSR LCD_command_write 005 0E 0 B 0 JSR clr_screen A 00 LDX # A0 00 LDY # JSR goto_xy RTS ; goto_xy(x,y) ; entry: A = y position ; B = x position 4

15 A goto_xy TXA A C9 00 CMP # C D0 08 BNE case E 98 TYA F 8 CLC ADC #80H D 0 JSR LCD_command_write RTS C9 0 case CMP # D0 08 BNE case A 98 TYA B 8 CLC C 69 C0 ADC #0C0H E 0 0D 0 JSR LCD_command_write RTS case RTS ; write ASCII code to LCD at current position ; entry: A putch_lcd JSR LcdReady JSR LCD_data_write RTS A A A A main JSR InitLcd D A9 6 LDA #'6' F JSR putch_lcd A9 5 LDA #'5' JSR putch_lcd A9 0 LDA #'0' JSR putch_lcd C A9 LDA #'' 00 06E JSR putch_lcd A9 0 LDA #' ' JSR putch_lcd A9 4B LDA #'K' JSR putch_lcd B A9 69 LDA #'i' D JSR putch_lcd A9 74 LDA #'t' JSR putch_lcd brk END tasm: Number of errors = 0 5

16 LOGIC PROBE POWER SUPPLY The kit provides test points TP4(+5V) and TP5(GND) for using the logic probe. Students may learn digital logic signals with logic probe easily. The important signals are RESET (TP) and PHI clock (TP). Tick signal, however indicated by D LED blinking. Logic probe can test it at P.7 of the 89C05 microcontroller directly. Red clip is for +5V and Black clip for GND. + 5V at TP GND at TP 6

17 WRITE YOUR OWN MONITOR PROGRAM The monitor ROM is U, 7C56. Source code of the monitor program is available for download. Students can learn and modify the source code by adding more function keys, utility subroutines. The monitor program can be tested in RAM and the move to ROM chip by using the EPROM programmer. The procedure of modifying the monitor program is as follows.. Set the code segment to 000h, so the hex file can be tested in RAM.. Use TASM with command, d:\650\tasm -65 monitor.asm. The object file will be hex file, download to the kit and test run. 4. If it works fine then change code segment to 0c000h for ROM. 5. The physical address will occupy last block of 64kB space. 6. Our EPROM is kb, so we must move the hex code from nd block to the first block. Then program the EPROM. 7

18 HARDWARE SCHEMATIC and PARTS LIST

19 D D C C B B A A PLD decoder logic 0xC000-0xFFFF Monitor Program Programmable system tick CPU expansion connector 0x0000-0x7FFF kb SRAM, NVRAM Designed by Wichit Sirichote, kswichit@kmitl.ac.th, 04 0ms Tick IRQ test switch <Doc> 650 MICROPROCESSOR KIT B Saturday, January 0, 05 Title Size Document Number Rev Date: Sheet of A[0..7] A SYNC ROM_CE PHI D7 PHI A5 A[8..4] D A A8 A4 A0 A TICK D D5 A A5 A D4 A R/W RAM_WR A A6 NMI RDY A A4 D A A8 RAM_WR D RESET A6 A A0 D6 A A0 SYNC A9 MHz A9 D4 NMI A0 D0 A7 D D6 D7 A5 A R/W A A4 RAM_CE RAM_CE A4 A5 A A7 D ROM_CE A4 D MHz A A0 D A0 A A5 D6 A8 D7 VDD D4 A0 A D A A D0 A6 D5 A A D0 A4 A9 A0 A4 IRQ D5 A VSS A7 RESET RESET BE PHI RESET TICK IRQ D0 D7 D D6 D5 D4 D D A0 A A A A4 A5 A7 A6 A8 A9 A A0 A RESET MHz A RESET A5 NMI IRQ A4 R/W PHI RDY SYNC BE TICK/ PHI D7 D D6 D4 D5 D D0 D VCC D[0..7] PORT0 PORT A[0..7] PORT LCD_E GPIO BREAK TXD D4 D5 D0 D6 D D7 D D A0 A +5V +5V +5V +5V VCC +5V +5V +5V +5V +5V +5V VCC +5V SW RESET R k C5 0.uF C8 0.uF SW IRQ U7A 74LS4 JP HEADER 0X R5 k TP TEST POINT + C4 000uF5V U7C 74LS C 0uF TP5 GND TP4 +5V U AT89C RST/VPP P.0/AIN0 P./AIN P. P. P.4 P.5 P.6 P.7 VCC P.0/RXD P./TXD P./INTO P./INT P.4/T0 P.5/T P.7 XTAL XTAL R6 0k U 7C A0 A A A A4 A5 A6 A7 A8 A9 A0 A A A A4 CE OE VPP O0 O O O O4 O5 O6 O7 TP TEST POINT U HM656B A0 A A A A4 A5 A6 A7 A8 A9 A0 A A A A4 CE OE WE D0 D D D D4 D5 D6 D7 Y-OSC-M-MEC OSC4 8 OUT C9 0.uF U6 74HC A B CLK CLR QA QB QC QD QE QF QG QH J DC Input + C6 0uF + C uf SW4 user U7B 74LS4 4 + C 0uF 6V D TVS5V_SOD C6 0.uF U8 LM VIN GND VOUT C0 0.uF TP TEST POINT D N4007 C 0.uF R4 4.7k D LED U4 GAL6V8D I/CLK I/OE I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I I I I I I I R 680 U5 65C0 CMOS CPU VSS RDY CLK IRQ NC NMI SYNC VCC A0 A A A A4 A5 A6 A7 A8 A9 A0 A RES CLK S0 CLK0 BE NC R/W D0 D D D D4 D5 D6 D7 A5 A4 A A VSS SW ESP switch C7 0.uF R k

20 D D C C B B A A 7-segment test 0x0 Designed by Wichit Sirichote, kswichit@kmitl.ac.th, 04 <Doc> 650 MICROPROCESSOR KIT B Saturday, January 0, 05 Title Size Document Number Rev Date: Sheet of D7 D4 D D D7 PA4 PC0 PA E D7 PC F PC4 D7 G C D PC D PC4 PA5 DP D0 D PA D PC0 PA0 PA0 PC4 PC B C B DP D5 PC E D6 PA PC5 PC6 A D6 PA5 PA4 SPEAKER D4 D5 G SPEAKER PC7 D6 D0 PA6 A E PC PC G D0 D PA6 D4 C D D DP D5 D PA PA D D PC F F D6 D D5 D0 PC5 PC5 PA B D D PC PC0 A D4 PC D6 PORT D7 VCC TXD BREAK D0 D5 D D RESET D PORT PORT0 RXD D4 VCC VCC +5V VCC VCC VCC +5V VCC VCC C8 00nF S S4 S0 U0 LTC-477JR A B C D E F G DP DIGIT DIGIT DIGIT DIGIT4 LLL S5 S7 S6 S8 S9 S LS SPEAKER R0 0 U 74HC OE LE VCC Q Q Q 4Q 5Q 6Q 7Q 8Q D D D 4D 5D 6D 7D 8D S + C7 0uF S S S S4 S5 C R 0k RESISTOR SIP S6 D4 TONE C R7 0k RESISTOR SIP R8 4.7k S7 S8 S S9 S0 S R9 0 U 74HC OE LE VCC Q Q Q 4Q 5Q 6Q 7Q 8Q D D D 4D 5D 6D 7D 8D S U 74HC A A A A4 A5 A6 A7 A8 G G Y Y Y Y4 Y5 Y6 Y7 Y8 VCC S S4 S5 S6 S7 S8 S0 J CON Q BC7 S S9 U9 LTC-477JR A B C D E F G DP DIGIT DIGIT DIGIT DIGIT4 LLL S

21 RXD TXD Title Designed by Wichit Sirichote, MICROPROCESSOR KIT Size Document Number Rev B <Doc> <RevCode> Date: Saturday, January 0, 05 Sheet of D C B A 5 4 D D0 D D D D4 D5 D6 D7 RESET D0 D D D D4 D5 D6 D7 GPIO D0 D D D D4 D5 D6 D U4 D D D 4D 5D 6D 7D 8D LE VCC OE 0 VCC 74HC57 Q Q Q 4Q 5Q 6Q 7Q 8Q D5 D6 D7 LED D8 D9 D0 LED D D C 6x text LCD interface D N56A B JR CONN RECT 6 R 0 D7 D6 D5 D4 D D D D0 R/W RS +5V +5V A A0 LCD_E A A0 8-bit Binary display LED x8 VB V + + 0uF 0V C C4 0uF U5 V+ V- TOUT TOUT RIN RIN C+ C- C+ C- TIN TIN ROUT ROUT 4 5 0uF 0 9 C + + 0uF C5 R 0K SUB-D 9, Male (cross cable) MAXA +5V C9 00nF +5V VCC VCC +5V VCC A 5 4

22 PARTS LIST Semiconductors U 7C56, kb EPROM U HM656B, kb Static RAM U AT89C05, 0-pin DIP microcontroller U4 GAL6V8D, programmable logic device U5 65SC0 CMOS CPU U6 74HC64, shift register U7 74LS4, inverter U8 LM , voltage regulator U0,U9 LTC-477JR, seven segment LED U,U,U4 74HC57, data latch U 74HC54, tristate buffer U5 MAXA, RS level converter D,D5,D6,D7,D8,D9,D0, mm LED D,D D TVS5V_SOD transient voltage suppressor D N4007 rectifying diode D4 mm LED D N56A Q BC7 PNP transistor Resistors (all resistors are /8W +/-5%) R 680 R,R,R5 k R8,R4 4.7k R,R6 0k R,R7 0k RESISTOR SIP 9 R9 0 R,R0 0 Capacitors C uf electrolytic C,C,C4,C5,C6,C7 0uF electrolytic C 0uF 6V electrolytic C4 000uF5V electrolytic C5,C6,C7,C8,C9 0.uF disc ceramic C0,C 0.uF disc ceramic C 0uF 0V electrolytic C9,C8 00nF disc ceramic Additional parts JJP HEADER 0X JR CONN RECT 6 text LCD connector J DC Input J CON -pin header LS SPEAKER SW ESP switch SW IRQ SW RESET SW4 user S,S,S,S4,S5,S6,S7,S8, S9,S0,S,S,S,S4,Tact switch S5,S6,S7,S8,S9,S0, S,S,S,S4,S5,S6, S7,S8,S9,S0,S,S, S TP,TP,TP TEST POINT TP4 +5V TP5 GND VB SUB-D 9, Male (cross cable) Y-OSC-M-MEC OSC4 PCB double side plate through hole LED cover Clear RED color acrylic plastic Keyboard sticker printable SVG file

23 MONITOR PROGRAM LISTINGS

24 8/0/05 6: PM ; ; Monitor program source code for 650 Microprocessor Kit ; Written by Wichit Sirichote, kswichit@kmitl.ac.th ; Copyright (c) ; ; Source code was assembled with tasm assembler ; Example of using tasm ; ; d:\tasm\tasm -65 monitor.asm ; ; The object file will be Intel hex file ready for EPROM programmer ; The physical location is the nd block of 64kB space ; To program the kb EPROM, we must move it to the st block ; ; ; ; 6 DECEMBER ; 7 DECEMBER ; -ADD OUT OF RANGE CHECK FOR RELATIVE BYTE CALCULATION ; -ADD DOWNLOAD HEX FILE TO MONITOR SOURCE ; 9 DECEMBER ; -ADD START MESSAGE ON COLD BOOT ; 0 DECEMBER ; -TEST SINGLE STEP WITH 74LS ; - ADD REPEAT KEY ; - LOWER REPEAT SPEED ; - REMOVE ACCUMALATOR DISPLAY ON BREAK ; JANUARY ; - REMOVE BINARY DISPLAY IN REGISTER MODE ; - ADD REGISTER MODE DISPLAY FOR 0 BYTES ZERO PAGE, $00 TO $ ; JANUARY ; - PROVIDE PROGRAM COUNTER SAVING FOR SINGLE STEP RUNNING ; now user may change display address, data, to get back current ad ; press PC key to restore it, then press step ; ; 7 February ; lower brightness of the 7-segment ; calibrate beep frequency to 5Hz ; March ; add hex file download using MOS hex format ; now the board can accept both Intel and MOS hex file format. Tested ; no error, the GPIO will display 0D (CR), if error it will show ; ; March fix cold boot message, make beep on cold boot ; address of the I/O ports GPIO.EQU 8000H PORT0.EQU 800H PORT.EQU 800H PORT.EQU 800H DIGIT.EQU 800H SEG7.EQU 800H KIN.EQU 800H ; page zero register definition ; LOCATION $00 TO $7F ARE 8 BYTES FOR USER PROGRAM TESTING DSEG ORG 80H ; zero page memory definitions for monitor use REG_E.BLOCK REG_D.BLOCK REG_B.BLOCK REG_C.BLOCK HL.BLOCK ; 84H = L 85H = H DE.BLOCK REG_A.BLOCK Page of 8

25 8/0/05 6: PM _ERROR.BLOCK ; ERROR FLAG FOR INTEL HEX FILE DOWNLOADING A BCC.BLOCK ; BYTE CHECK SUM C BUFFER.BLOCK 6 ; 8BH - 90H PAGE ZERO DISPLAY BUFFER INVALID.BLOCK ; INVALID KEY HAS BEEN PRESSED FLAG BIT ; 0 VALID ; INVALID KEY.BLOCK STATE.BLOCK ZERO_FLAG.BLOCK ; ZERO WHEN HEX KEY PRESSED FOR ADDRESS OR DISPLAY.BLOCK ; display address PC_USER.BLOCK ; FOR SAVING CURRENT PC, ON RESET, IT SETS TO A USER_A.BLOCK B USER_X.BLOCK C USER_Y.BLOCK D USER_S.BLOCK ; USER STACK POINTER E USER_P.BLOCK ; PROGRAM STATUS REGISTER F SAVE_SP.BLOCK ; SAVE SYSTEM STACK A A0 START_ADDRESS.BLOCK A DESTINATION.BLOCK ; FOR OFFSET BYTE CALCULATION 00 00A4 OFFSET_BYTE.BLOCK ; OFFSET BYTE = DESTINATION - START_ADDRESS 00 00A6 COLD.BLOCK ; COLD BOOT OR WARM BOOT 00 00A A7 REPDELAY.BLOCK A8 SAVE_X.BLOCK A9 SAVE_Y.BLOCK AA AA DEBUG.BLOCK ; FOR PROGRAM DEBUGGING AC 00 00AC 0 00AC 0 00AC.CSEG 0 00AC 04 C000.ORG 0C000H ; START ADDRESS FOR ROM 05 C000 ;.ORG 000H ; START ADDRESS FOR CODE TESTING IN RAM 06 C C000 A9 BF LDA #$BF ; turn off break signal 08 C00 8D 0 80 STA PORT 09 C005 A9 00 LDA #0 00 C007 8D 0 80 STA PORT ; turn of 7-segment 0 C00A 0 C00A ; power up delay 0 C00A 04 C00A A 00 LDX #0 05 C00C CA POWER_UP_DELAY DEX 06 C00D D0 FD BNE POWER_UP_DELAY 07 C00F 08 C00F ; jump to main code 09 C00F 00 C00F 4C 7 C8 JMP MAIN 0 C0 0 C0 ; BIT/S SOFTWARE UART C0 ; one bit delay for 400 bit/s UART 04 C0 05 C0 A0 4C BIT_DELAY LDY #76 ; 90 Hz TEST AT MHZ OSCILLATOR 06 C04 88 LOOP DEY 07 C05 D0 FD BNE LOOP 08 C07 60 RTS 09 C C08 ;.5 bit delay 04 C08 04 C08 A0 7 BIT_5_DELAY LDY #4 ; DELAY.5 BIT 04 C0A 88 LOOP DEY 044 C0B D0 FD BNE LOOP 045 C0D 60 RTS 046 C0E 047 C0E ; SEND ASCII LETTER TO TERMINAL 048 C0E ; ENTRY: A 049 C0E 050 C0E SEND_BYTE: STA REG_E ; SAVE ACCUMULATOR 05 C00 05 C00 A9 F LDA #FH ; start bit is zero Page of 8

26 8/0/05 6: PM 05 C0 8D 0 80 STA PORT 054 C05 0 C0 JSR BIT_DELAY ; delay one bit 055 C C08 A9 08 LDA #8 ; 8-data bit wil be sent 057 C0A 85 8 STA REG_D 058 C0C 059 C0C A5 80 CHK_BIT: LDA REG_E 060 C0E 9 0 AND # 06 C00 F0 08 BEQ SEND_ZERO 06 C0 06 C0 A9 BF LDA #0BFH 064 C04 8D 0 80 STA PORT 065 C C07 4C 4 C0 JMP NEXT_BIT 067 C0A 068 C0A 069 C0A A9 F SEND_ZERO: LDA #FH 070 C0C 8D 0 80 STA PORT 07 C0F 4C 4 C0 JMP NEXT_BIT 07 C04 07 C04 0 C0 NEXT_BIT: JSR BIT_DELAY 074 C C LSR REG_E 076 C047 C6 8 DEC REG_D 077 C049 D0 E BNE CHK_BIT 078 C04B 079 C04B A9 BF LDA #0BFH 080 C04D 8D 0 80 STA PORT 08 C050 0 C0 JSR BIT_DELAY 08 C05 60 RTS 08 C C C054 ; RECEIVE BYTE FROM 400 BIT/S TERMINAL 086 C054 ; EXIT: A 087 C C054 AD 0 80 CIN LDA PORT0 089 C AND #80H 090 C059 D0 F9 BNE CIN 09 C05B 09 C05B 0 8 C0 JSR BIT_5_DELAY 09 C05E 094 C05E A9 07 LDA #7 095 C STA REG_D 096 C06 A9 00 LDA #0 097 C STA REG_E 098 C C C C066 AD 0 80 CHK_BIT_RX LDA PORT0 00 C AND #80H 00 C06B D0 09 BNE BIT_IS_ONE 004 C06D 005 C06D A5 80 LDA REG_E 006 C06F 9 7F AND #7FH 007 C STA REG_E 008 C07 4C 7F C0 JMP NEXT_BIT_RX 009 C C076 A5 80 BIT_IS_ONE LDA REG_E 0 C ORA #80H 0 C07A STA REG_E 0 C07C 4C 7F C0 JMP NEXT_BIT_RX 04 C07F 05 C07F 0 C0 NEXT_BIT_RX JSR BIT_DELAY 06 C08 07 C LSR REG_E 08 C C084 C6 8 DEC REG_D 00 C086 D0 DE BNE CHK_BIT_RX 0 C088 0 C088 0 C0 JSR BIT_DELAY ; CENTER OF STOP BIT 0 C08B 04 C08B A5 80 LDA REG_E 05 C08D 06 C08D 60 RTS 07 C08E 08 C08E Page of 8

27 8/0/05 6: PM 09 C08E ; PRINT TEXT FROM STRING AREA 00 C08E ; ENTRY: X POINTED TO OFFSET 0 C08E 0 C08E BD 00 EF PSTRING LDA TEXT,X 0 C09 C9 00 CMP #0 04 C09 D0 0 BNE PRINT_IT 05 C RTS 06 C C096 0 E C0 PRINT_IT JSR SEND_BYTE 08 C099 E8 INX 09 C09A 4C 8E C0 JMP PSTRING 040 C09D 04 C09D CR.EQU 0DH 04 C09D LF.EQU 0AH 04 C09D EOS.EQU C09D 045 C09D ;NEW LINE 046 C09D ; PRINT CR, LF 047 C09D 048 C09D A9 0D NEW_LINE LDA #0DH 049 C09F 0 E C0 JSR SEND_BYTE 050 C0A A9 0A LDA #0AH 05 C0A4 0 E C0 JSR SEND_BYTE 05 C0A7 60 RTS 05 C0A8 054 C0A8 055 C0A8 ; WRITE NIBBLE TO TERMINAL 056 C0A8 9 0F OUTX AND #0FH 057 C0AA 8 CLC 058 C0AB 69 0 ADC #0H 059 C0AD C9 A CMP #AH 060 C0AF 90 0 BCC OUTX 06 C0B 8 CLC 06 C0B ADC #7 06 C0B4 0 E C0 OUTX JSR SEND_BYTE 064 C0B7 60 RTS 065 C0B8 066 C0B8 067 C0B8 48 OUTX PHA 068 C0B9 069 C0B9 4A LSR A 070 C0BA 4A LSR A 07 C0BB 4A LSR A 07 C0BC 4A LSR A 07 C0BD 074 C0BD ; STA GPIO 075 C0BD 076 C0BD 0 A8 C0 JSR OUTX 077 C0C0 68 PLA 078 C0C 0 A8 C0 JSR OUTX 079 C0C4 60 RTS 080 C0C5 08 C0C5 08 C0C5 ; INCREMENT HL 08 C0C5 ; INCREMENT 6-BIT POINTER FOR 6-BIT MEMORY ACCESS 084 C0C5 085 C0C5 8 INC_HL CLC 086 C0C6 A5 84 LDA HL 087 C0C ADC # 088 C0CA STA HL 089 C0CC A5 85 LDA HL+ 090 C0CE ADC #0 09 C0D STA HL+ 09 C0D 60 RTS 09 C0D 094 C0D 095 C0D ; PRINT LINE OF MEMORY POINTED TO HL 096 C0D 097 C0D 0 9D C0 PRINT_LINE JSR NEW_LINE 098 C0D6 A9 0 LDA #6 099 C0D STA REG_C 000 C0DA 00 C0DA 00 C0DA 00 C0DA A5 85 LDA HL+ 004 C0DC 0 B8 C0 JSR OUTX Page 4 of 8

28 8/0/05 6: PM 005 C0DF A5 84 LDA HL 006 C0E 0 B8 C0 JSR OUTX 007 C0E4 008 C0E4 A9 A LDA #':' 009 C0E6 0 E C0 JSR SEND_BYTE 00 C0E9 0 C0E9 A0 00 PRINT_LINE LDY #0 0 C0EB B 84 LDA (HL),Y 0 C0ED 04 C0ED 0 B8 C0 JSR OUTX 05 C0F0 06 C0F0 A9 0 LDA #' ' 07 C0F 0 E C0 JSR SEND_BYTE 08 C0F5 09 C0F5 0 C5 C0 JSR INC_HL 00 C0F8 0 C0F8 C6 8 DEC REG_C 0 C0FA 0 C0FA D0 ED BNE PRINT_LINE 04 C0FC 05 C0FC 60 RTS 06 C0FD 07 C0FD ; CONVERT ASCII TO HEX 08 C0FD ; ENTRY: A 09 C0FD 00 C0FD 8 TO_HEX SEC 0 C0FE E9 0 SBC #0H 0 C00 C9 0 CMP #0H 0 C BCC ZERO_NINE 04 C04 9 DF AND #0B 05 C06 8 SEC 06 C07 E9 07 SBC #7 07 C09 08 C09 60 ZERO_NINE RTS 09 C0A 040 C0A ; CONVERT TWO ASCII LETTERS TO SINGLE BYTE 04 C0A ; EXIT: A 04 C0A 04 C0A 0 54 C0 GET_HEX JSR CIN 044 C0D 0 FD C0 JSR TO_HEX 045 C0 0A ASL A 046 C 0A ASL A 047 C 0A ASL A 048 C 0A ASL A 049 C4 050 C4 8D STA GPIO 05 C7 05 C STA REG_A 05 C9 054 C C0 JSR CIN 055 CC 0 FD C0 JSR TO_HEX 056 CF 8 CLC 057 C ADC REG_A 058 C 059 C 60 RTS 060 C 06 C ; CONVERT TWO ASCII LETTERS TO SINGLE BYTE 06 C ; EXIT: A 06 C 064 C 0 54 C0 GET_HEX JSR CIN 065 C6 48 PHA 066 C7 0 E C0 JSR SEND_BYTE ; ECHO TO TERMINAL 067 CA 68 PLA 068 CB 0 FD C0 JSR TO_HEX 069 CE 0A ASL A 070 CF 0A ASL A 07 C0 0A ASL A 07 C 0A ASL A 07 C 074 C 8D STA GPIO 075 C5 076 C STA REG_A 077 C7 078 C C0 JSR CIN 079 CA 48 PHA 080 CB 0 E C0 JSR SEND_BYTE Page 5 of 8

29 8/0/05 6: PM 08 CE 68 PLA 08 CF 0 FD C0 JSR TO_HEX 08 C4 8 CLC 084 C ADC REG_A 085 C C45 60 RTS 087 C C46 ; C46 SET_NEW_ADDRESS 090 C46 09 C46 0 E C0 JSR SEND_BYTE 09 C49 A C LDX #PROMPT&00FFH 09 C4B 0 8E C0 JSR PSTRING 094 C4E 0 C JSR GET_HEX 095 C STA HL+ 096 C5 0 C JSR GET_HEX 097 C STA HL 098 C58 60 RTS 099 C C59 8 ADD_BCC CLC 040 C5A 65 8A ADC BCC 040 C5C 85 8A STA BCC 040 C5E 60 RTS 0404 C5F 0405 C5F ; C5F ; GET_RECORD READS INTEL HEX FILE AND SAVE TO MEMORY 0407 C5F 0408 C5F A9 00 GET_RECORD LDA # C STA _ERROR 040 C6 04 C C0 GET_RECORD JSR CIN 04 C66 C9 A CMP #':' 04 C68 F0 07 BEQ GET_RECORD 044 C6A 045 C6A C9 B CMP #$B ; ';' 046 C6C D0 F5 BNE GET_RECORD 047 C6E 048 C6E 4C ED C JMP GET_MOS 049 C7 040 C7 04 C7 GET_RECORD 04 C7 04 C7 A9 00 LDA #0 044 C7 85 8A STA BCC 045 C C75 0 0A C JSR GET_HEX 047 C STA REG_C ; GET NUMBER OF BYTE 048 C7A 049 C7A 0 59 C JSR ADD_BCC 040 C7D 04 C7D 0 0A C JSR GET_HEX 04 C STA HL+ 04 C8 044 C C JSR ADD_BCC 045 C C85 0 0A C JSR GET_HEX 047 C STA HL ; GET LOAD ADDRESS 048 C8A 049 C8A 0 59 C JSR ADD_BCC 0440 C8D 044 C8D 0 0A C JSR GET_HEX 044 C C90 C9 00 CMP # C C9 F0 4 BEQ DATA_RECORD 0446 C C C0 WAIT_CR JSR CIN 0448 C97 C9 0D CMP #0DH 0449 C99 D0 F9 BNE WAIT_CR 0450 C9B 045 C9B 8D STA GPIO 045 C9E 045 C9E A5 89 LDA _ERROR 0454 CA0 C9 0 CMP # 0455 CA D0 0 BNE NOERROR 0456 CA4 Page 6 of 8

30 8/0/05 6: PM 0457 CA4 ; SHOW ERROR ON LED 0458 CA4 ; JSR OUT_OFF_RANGE 0459 CA CA4 8D STA GPIO 046 CA7 046 CA7 NOERROR 046 CA7 60 RTS 0464 CA CA8 DATA_RECORD 0466 CA CA8 0 0A C JSR GET_HEX 0468 CAB A0 00 LDY # CAD 9 84 STA (HL),Y ; WRITE TO MEMORY 0470 CAF 047 CAF 0 59 C JSR ADD_BCC 047 CB 047 CB 8D STA GPIO 0474 CB CB5 0 C5 C0 JSR INC_HL 0476 CB CB8 C6 8 DEC REG_C 0478 CBA D0 EC BNE DATA_RECORD ; UNTIL C= CBC 0480 CBC A5 8A LDA BCC 048 CBE 49 FF EOR #0FFH ; ONE'S COMPLEMENT 048 CC0 8 CLC 048 CC 69 0 ADC # ; TWO'S COMPLEMENT 0484 CC 85 8A STA BCC 0485 CC CC CC5 0 0A C JSR GET_HEX ; GET BYTE CHECK SUM 0488 CC CC8 C5 8A CMP BCC ; COMPARE WITH BYTE CHECK SUM 0490 CCA F0 04 BEQ SKIP 049 CCC 049 CCC A9 0 LDA # 049 CCE STA _ERROR ; ERROR FLAG = 0494 CD CD CD0 SKIP 0497 CD CD0 4C 6 C JMP GET_RECORD ; NEXT LINE 0499 CD 0500 CD 050 CD 050 CD SEND_PROMPT 050 CD 0504 CD 0 9D C0 JSR NEW_LINE 0505 CD6 A5 85 LDA HL CD8 0 B8 C0 JSR OUTX 0507 CDB A5 84 LDA HL 0508 CDD 0 B8 C0 JSR OUTX 0509 CE0 050 CE0 05 CE0 A C LDX #PROMPT&00FFH 05 CE 0 8E C0 JSR PSTRING 05 CE5 60 RTS 054 CE6 055 CE6 ;=================================================================== 056 CE6 ; get MOS record 057 CE6 ; sample MOS record 058 CE6 ; 059 CE6 ;8 000 A A5008D0080A00A00088D0FDCAD0F84C05 09B 050 CE6 ; D 05 CE6 ;00 05 CE6 ; 05 CE6 ; 8 is number of byte 054 CE6 ; 000 is load address 055 CE6 ; A9, 0, 85.. data byte 056 CE6 ; 09B is 6-bit check sum 057 CE6 058 CE6 059 CE6 050 CE6 GET_MOS 05 CE C0 JSR CIN 05 CE9 C9 B CMP #$B ; ';' Page 7 of 8

31 8/0/05 6: PM 05 CEB D0 F9 BNE GET_MOS 054 CED 055 CED GET_MOS 056 CED 057 CED A9 00 LDA #0 058 CEF 85 8A STA BCC 059 CF 85 8B STA BCC+ ; MOS uses 6-bit checksum 0540 CF 054 CF 054 CF 0 0A C JSR GET_HEX 054 CF STA REG_C ; GET NUMBER OF BYTE 0544 CF CF8 C9 00 CMP # CFA F0 6 BEQ END_RECORD 0547 CFC 0548 CFC 0 5A C JSR ADD_BCC_MOS 0549 CFF 0550 CFF 0 0A C JSR GET_HEX 055 C STA HL+ 055 C C04 0 5A C JSR ADD_BCC_MOS 0554 C C07 0 0A C JSR GET_HEX 0556 C0A STA HL ; GET LOAD ADDRESS 0557 C0C 0558 C0C 0 5A C JSR ADD_BCC_MOS 0559 C0F 0560 C0F 4C 6 C JMP DATA_RECORD 056 C 056 C 0 54 C0 END_RECORD JSR CIN 056 C5 C9 0D CMP #0DH 0564 C7 D0 F9 BNE END_RECORD 0565 C C9 8D STA GPIO 0567 CC 0568 CC A5 89 LDA _ERROR 0569 CE C9 0 CMP # 0570 C0 D0 0 BNE NOERROR 057 C 057 C ; SHOW ERROR ON LED 057 C 0574 C 8D STA GPIO 0575 C C C5 NOERROR 0578 C5 60 RTS 0579 C C6 DATA_RECORD 058 C6 058 C6 0 0A C JSR GET_HEX 058 C9 A0 00 LDY # CB 9 84 STA (HL),Y ; WRITE TO MEMORY 0585 CD 0586 CD 0 5A C JSR ADD_BCC_MOS 0587 C C0 8D STA GPIO 0589 C 0590 C 0 C5 C0 JSR INC_HL 059 C6 059 C6 C6 8 DEC REG_C 059 C8 D0 EC BNE DATA_RECORD ; UNTIL C= CA 0595 CA ; now get 6-bit check sum 0596 CA 0597 CA 0 0A C JSR GET_HEX ; GET 6-bit CHECK SUM 0598 CD STA HL CF ; STA DEBUG CF 060 CF 0 0A C JSR GET_HEX 060 C STA HL ; check sum now stored in HL+ and HL 060 C44 ; STA DEBUG 0604 C C44 A5 8B LDA BCC C46 C5 85 CMP HL C48 D0 09 BNE error_mos 0608 C4A A5 8A LDA BCC Page 8 of 8

32 8/0/05 6: PM 0609 C4C C5 84 CMP HL 060 C4E D0 0 BNE error_mos 06 C50 06 C50 4C 57 C JMP SKIP 06 C5 064 C5 error_mos 065 C5 A9 0 LDA # 066 C STA _ERROR ; ERROR FLAG = 067 C C C57 SKIP 060 C57 06 C57 4C E6 C JMP GET_MOS ; NEXT LINE 06 C5A 06 C5A 064 C5A ; add 6-bit check sum, stores in BCC+ and BCC 065 C5A 066 C5A ADD_BCC_MOS 067 C5A 068 C5A 8 CLC 069 C5B 65 8A ADC BCC 060 C5D 85 8A STA BCC 06 C5F A9 00 LDA #0 06 C6 65 8B ADC BCC+ 06 C6 85 8B STA BCC+ 064 C65 60 RTS 065 C C C66 ; END UART CODE C C66 ; SCAN DISPLAY ONLY 0640 C66 ; ENTRY: X POINTED TO NEXT MESSAGE BYTE 064 C66 ; FIX_MESSAGE LOCATION 064 C C66 SCAN: 0644 C STX REG_C 0645 C68 A9 0 LDA # 0646 C6A STA REG_E 0647 C6C 0648 C6C A9 06 LDA # C6E STA HL 0650 C C70 ;to the active column. 065 C70 A5 80 KCOL LDA REG_E 065 C C7 49 FF EOR #0FFH ; COMPLEMENT IT 0655 C C74 9 BF AND #0BFH ; BREAK MUST BE LOGIC '0' TO DISABLE 0657 C76 8D 0 80 STA DIGIT 0658 C C79 BD E C8 LDA START_MSG,X 0660 C7C 8D 0 80 STA SEG7 066 C7F 066 C7F A0 05 LDY #$5 066 C8 88 DELAY5 DEY 0664 C8 D0 FD BNE DELAY C C84 A9 00 LDA #0 ; TURN LED OFF 0667 C86 8D 0 80 STA SEG C C C C C89 E8 INX 067 C8A 0674 C8A A5 80 LDA REG_E 0675 C8C 0A ASL A 0676 C8D STA REG_E 0677 C8F 0678 C8F C6 84 DEC HL 0679 C9 D0 DD BNE KCOL 0680 C9 068 C9 A6 8 LDX REG_C 068 C C95 60 RTS 0684 C96 Page 9 of 8

33 8/0/05 6: PM 0685 C C96 ; SCAN DISPLAY AND KEYBOARD 0687 C96 ; ENTRY: DISPLAY BUFFER IN PAGE C96 ; EXIT: KEY = - NO KEY PRESSED 0689 C96 ; KEY >=0 KEY POSITION 0690 C96 ; REGSITERS USED: X,A,Y 069 C C96 SCAN: 069 C C C96 A 00 LDX # C C98 A9 00 LDA # C9A 85 8 STA REG_C 0699 C9C 0700 C9C A9 FF LDA #- 070 C9E 85 9 STA KEY 070 CA0 070 CA0 A9 0 LDA # 0704 CA STA REG_E 0705 CA CA4 A9 06 LDA # CA STA HL 0708 CA CA8 ;to the active column. 070 CA8 A5 80 KCOL LDA REG_E 07 CAA 07 CAA 49 FF EOR #0FFH ; COMPLEMENT IT 07 CAC 9 BF AND #0BFH ; MUST BE LOW FOR BREAK 074 CAE 075 CAE 8D 0 80 STA DIGIT 076 CB 077 CB B5 8C LDA BUFFER,X 078 CB 8D 0 80 STA SEG7 079 CB6 070 CB6 A0 0 LDY #$0 07 CB8 88 DELAY DEY 07 CB9 D0 FD BNE DELAY 07 CBB 074 CBB A9 00 LDA #0 ; TURN LED OFF 075 CBD 8D 0 80 STA SEG7 076 CC0 077 CC0 A0 LDY # CC 88 DELAY0 DEY 079 CC D0 FD BNE DELAY0 070 CC5 07 CC5 07 CC5 A9 06 LDA #6 07 CC STA REG_B 074 CC9 075 CC9 AD 0 80 LDA KIN 076 CCC 077 CCC 85 8 STA REG_D 078 CCE 079 CCE 0740 CCE 46 8 KROW LSR REG_D ;Rotate D bit right, bit CD0 ;of D will be rotated into 074 CD0 B0 04 BCS NOKEY ;carry flag. 074 CD 0744 CD A5 8 LDA REG_C 0745 CD STA KEY 0746 CD CD6 E6 8 NOKEY INC REG_C ;Increase current key-code by CD CD8 C6 8 DEC REG_B 0750 CDA D0 F BNE KROW 075 CDC 075 CDC E8 INX 075 CDD 0754 CDD A5 80 LDA REG_E 0755 CDF 0A ASL A 0756 CE STA REG_E 0757 CE 0758 CE 0759 CE C6 84 DEC HL 0760 CE4 D0 C BNE KCOL Page 0 of 8

34 8/0/05 6: PM 076 CE6 60 RTS 076 CE7 076 CE CE7 A0 C8 DEBOUNCE LDY # CE9 88 DELAY4 DEY 0766 CEA D0 FD BNE DELAY CEC 60 RTS 0768 CED 0769 CED ; CED 077 CED 0 96 C SCANKEY JSR SCAN 077 CF0 A5 9 LDA KEY 077 CF C9 FF CMP # CF4 F0 6 BEQ KEY_RELEASED 0775 CF CF6 AD 0 80 LDA PORT CF AND #40H 0778 CFB D0 F0 BNE SCANKEY 0779 CFD 0780 CFD ; IF REPEAT KEY WAS PRESSED, SLOW DOWN IT 078 CFD A9 0 LDA #0H 078 CFF 85 A7 STA REPDELAY 078 C C C DISPLAY4 JSR SCAN 0785 C04 C6 A7 DEC REPDELAY 0786 C06 D0 F9 BNE DISPLAY C C C08 A 00 LDX #0 ; THEN REPEAT KEY PRESS 0790 C0A 86 9 STX INVALID ; RESET INVALID FLAG 079 C0C KEY_RELEASED 079 C0C 079 C0C 0 E7 C JSR DEBOUNCE 0794 C0F 0795 C0F UNTIL_PRESS 0796 C0F 0797 C0F 0 96 C JSR SCAN 0798 C A5 9 LDA KEY 0799 C4 C9 FF CMP # C6 F0 F7 BEQ UNTIL_PRESS 080 C8 080 C8 0 E7 C JSR DEBOUNCE 080 CB 0804 CB 0 96 C JSR SCAN 0805 CE 0806 CE A5 9 LDA KEY 0807 C0 AA TAX 0808 C BD FF C8 LDA KEYTAB,X ; OPEN TABLE 0809 C4 080 C4 ;STA GPIO ; TEST NOW A IS INTERNAL CODE 08 C4 60 RTS 08 C5 08 C5 084 C5 ; CONVERT LOW NIBBLE IN ACCUMULATOR TO 7-SEGMENT PATTERN 085 C5 ; ENTRY: A 086 C5 ; EXIT: A 087 C5 088 C5 NIBBLE_7SEG 089 C5 AA TAX 080 C6 BD EF C8 LDA SEGTAB,X 08 C9 60 RTS 08 CA 08 CA 084 CA ; CONVERT BYTE TO 7-SEGMENT PATTERN 085 CA ; ENTRY: A 086 CA ; EXIT: DE 087 CA 088 CA 48 BYTE_7SEG PHA 089 CB 9 0F AND #0FH 080 CD 0 5 C JSR NIBBLE_7SEG 08 C STA DE 08 C 68 PLA 08 C 4A LSR A 084 C4 4A LSR A 085 C5 4A LSR A 086 C6 4A LSR A Page of 8

35 8/0/05 6: PM 087 C7 0 5 C JSR NIBBLE_7SEG 088 CA STA DE+ 089 CC 60 RTS 0840 CD 084 CD ; CONVERT BYTE TO 7-SEGMENT PATTERN AND SAVE TO DISPLAY BUFFER DATA FI 084 CD ; ENTRY: A 084 CD 0844 CD 48 DATA_DISPLAY PHA ; SAVE ACCUMULATOR 0845 CE 0 A C JSR BYTE_7SEG 0846 C4 A5 86 LDA DE 0847 C4 85 8C STA BUFFER 0848 C45 A5 87 LDA DE C D STA BUFFER C49 68 PLA 085 C4A 60 RTS 085 C4B 085 C4B ; CONVERT 6-BIT ADDRESS IN HL AND SAVE IT TO ADDRESS FILED DISPLAY BU 0854 C4B ; ENTRY: HL 0855 C4B 0856 C4B ADDRESS_DISPLAY 0857 C4B 0858 C4B A5 84 LDA HL 0859 C4D 0 A C JSR BYTE_7SEG 0860 C50 A5 86 LDA DE 086 C5 85 8E STA BUFFER+ 086 C54 A5 87 LDA DE+ 086 C F STA BUFFER C58 A5 85 LDA HL C5A 0 A C JSR BYTE_7SEG 0866 C5D A5 86 LDA DE 0867 C5F STA BUFFER C6 A5 87 LDA DE C STA BUFFER C65 60 RTS 087 C C66 ;********************************************************************* 087 C66 ; 0874 C66 ; EXECUTE FUNCTIONS OR HEX KEY ENTERED 0875 C66 ; CHECK HEX KEY OR FUNCTIONS KEY 0876 C66 ; ENTRY: A 0877 C C66 C9 0 KEYEXE CMP #0H 0879 C68 B0 4 BCS FUNCTION_KEY 0880 C6A 088 C6A 088 C6A ;HHHHHHHHHHHHHHH KEY HEX ENTERED HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH 088 C6A 0884 C6A 85 8 STA REG_C ; SAVE HEX KEY 0885 C6C A5 94 LDA STATE 0886 C6E 0887 C6E C9 0 CMP # 0888 C70 D0 05 BNE CHK_STATE 0889 C C7 A5 8 LDA REG_C 089 C74 4C C C5 JMP HEX_ADDR 089 C C77 C9 0 CHK_STATE CMP # 0894 C79 D0 0 BNE CHK_STATE 0895 C7B 4C 4A C5 JMP HEX_DATA 0896 C7E 0897 C7E C9 0 CHK_STATE CMP # 0898 C80 D0 0 BNE CHK_STATE C8 4C C7 JMP HEX_REG 0900 C C85 C9 05 CHK_STATE5 CMP #5 090 C87 D0 0 BNE CHK_STATE6 090 C89 4C 04 C5 JMP HEX_REL 0904 C8C 0905 C8C C9 06 CHK_STATE6 CMP # C8E D0 0 BNE CHK_STATE C90 4C 0 C5 JMP HEX_REL C C9 C9 07 CHK_STATE7 CMP #7 090 C95 D0 0 BNE CHK_STATE8 09 C97 4C EC C4 JMP HEX_SEND_FILE 09 C9A Page of 8

36 8/0/05 6: PM 09 C9A C9 08 CHK_STATE8 CMP #8 094 C9C D0 0 BNE CHK_STATE9 095 C9E 4C F8 C4 JMP HEX_SEND_FILE 096 CA 097 CA A5 8 CHK_STATE9 lda REG_C 098 CA 8D sta GPIO 099 CA6 A9 0 LDA # ; INVALID KEY PRESSED 090 CA STA INVALID 09 CAA 09 CAA 09 CAA 094 CAA 095 CAA 096 CAA ; HEX KEY WAS PRESSED 097 CAA 098 CAA 099 CAA 60 RTS 090 CAB 09 CAB ;FFFFFFFFFFFFFFFFFFFFFF FUNCTION KEY FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 09 CAB 09 CAB FUNCTION_KEY 094 CAB 095 CAB C9 9 CMP #9H ; KEY ADDR 096 CAD D0 0 BNE CHK_FUNC 097 CAF 4C 79 C4 JMP KEY_ADDR 098 CB 099 CB C9 4 CHK_FUNC CMP #4H ; KEY DATA 0940 CB4 D0 0 BNE CHK_FUNC 094 CB6 4C A9 C4 JMP KEY_DATA 094 CB9 094 CB9 C9 0 CHK_FUNC CMP #0H ; KEY CBB D0 0 BNE CHK_FUNC 0945 CBD 4C 6A C5 JMP KEY_INC 0946 CC CC0 C9 CHK_FUNC CMP #H ; KEY CC D0 0 BNE CHK_FUNC CC4 4C C5 C5 JMP KEY_DEC 0950 CC7 095 CC7 C9 8 CHK_FUNC4 CMP #8H 095 CC9 D0 0 BNE CHK_FUNC5 095 CCB 4C DE C5 JMP KEY_PC 0954 CCE 0955 CCE C9 B CHK_FUNC5 CMP #BH 0956 CD0 D0 0 BNE CHK_FUNC CD 4C F C5 JMP KEY_REG 0958 CD CD5 C9 CHK_FUNC6 CMP #H 0960 CD7 D0 0 BNE CHK_FUNC7 096 CD9 4C 4 C6 JMP KEY_GO 096 CDC 096 CDC C9 D CHK_FUNC7 CMP #DH 0964 CDE D0 0 BNE CHK_FUNC CE0 4C 65 C4 JMP KEY_REL 0966 CE 0967 CE C9 F CHK_FUNC8 CMP #FH 0968 CE5 D0 0 BNE CHK_FUNC CE7 4C 6 C4 JMP KEY_DOWNLOAD_HEX 0970 CEA 097 CEA C9 CHK_FUNC9 CMP #H 097 CEC D0 0 BNE CHK_FUNC0 097 CEE 4C 67 C6 JMP KEY_STEP 0974 CF 0975 CF 0976 CF C9 6 CHK_FUNC0 CMP #6H 0977 CF D0 0 BNE CHK_FUNC 0978 CF5 4C 0 C4 JMP KEY_INS 0979 CF CF8 C9 7 CHK_FUNC CMP #7H 098 CFA D0 04 BNE CHK_FUNC 098 CFC 4C 0 C4 JMP KEY_DEL 098 CFF 60 RTS 0984 C C400 CHK_FUNC 0986 C C RTS 0988 C40 Page of 8

37 8/0/05 6: PM 0989 C40 ; C40 NO_RESPONSE 099 C40 60 RTS 099 C C C40 60 KEY_DEL RTS 0995 C C40 ; C40 ; insert byte to current display C40 ; shift down kb, 56 bytes C C40 A5 94 KEY_INS LDA STATE 00 C405 C9 0 CMP # 00 C407 F0 08 BEQ KEY_INS 00 C409 C9 0 CMP # 004 C40B F0 04 BEQ KEY_INS 005 C40D 006 C40D 0 0 C4 JSR NO_RESPONSE 007 C40 60 RTS 008 C4 009 C4 A5 96 KEY_INS LDA DISPLAY 00 C STA DE 0 C45 A5 97 LDA DISPLAY+ 0 C STA DE+ 0 C49 04 C49 8 CLC 05 C4A A5 87 LDA DE+ 06 C4C 69 8 ADC #40 ; DE=DE+$ C4E STA DE+ 08 C40 09 C40 00 C40 0 C40 0 C40 60 RTS 0 C4 04 C4 05 C4 06 C4 07 C4 08 C4 09 C4 00 C4 ; C4 KEY_SEND_HEX 0 C4 A9 07 LDA #7 0 C STA STATE ; STATE = 7 FOR SENDING HEX FILE 04 C45 05 C45 A9 00 LDA #0 06 C STA ZERO_FLAG 07 C C4 JSR STILL_ADDRESS 08 C4C A9 AE LDA #0AEH 09 C4E 85 8C STA BUFFER 040 C40 A9 0 LDA # 04 C4 85 8D STA BUFFER+ 04 C44 60 RTS 04 C C45 60 RTS 045 C C C46 ; C46 KEY_DOWNLOAD_HEX 049 C C46 A9 B LDA #0BH ; PRINT LOAD 05 C STA BUFFER+5 05 C4A A9 85 LDA #85H 05 C4C 85 9 STA BUFFER C4E A9 A LDA #0AH 055 C STA BUFFER C44 A9 F LDA #FH 057 C F STA BUFFER+ 058 C446 A9 B LDA #0BH 059 C E STA BUFFER+ 060 C44A A9 00 LDA #0 06 C44C 85 8D STA BUFFER+ 06 C44E 85 8C STA BUFFER 06 C C450 ; JSR NEW_LINE Page 4 of 8

38 8/0/05 6: PM 065 C450 ; JSR NEW_LINE 066 C450 ; JSR NEW_LINE 067 C450 A9 0A LDA #0 068 C STA STATE 069 C RTS 070 C C455 A9 55 GO_STATE0 LDA #55H 07 C457 8D STA GPIO 07 C45A 074 C45A 075 C45A 0 5F C JSR GET_RECORD ; GET INTEL HEX FILE 076 C45D 077 C45D A9 0 LDA # 078 C45F STA STATE 079 C46 0 B C4 JSR STILL_DATA 080 C C RTS 08 C C C465 ; C465 A9 05 KEY_REL LDA #5 086 C STA STATE ; STATE = 5 FOR RELATIVE BYTE CALCULATION 087 C C469 A9 00 LDA #0 089 C46B STA ZERO_FLAG 090 C46D 0 8 C4 JSR STILL_ADDRESS 09 C470 A9 AE LDA #0AEH 09 C C STA BUFFER 09 C474 A9 0 LDA # 094 C D STA BUFFER+ 095 C RTS 096 C C C479 ; C479 A9 0 KEY_ADDR LDA # 00 C47B STA STATE ; STATE = FOR ADDRESS MODE 0 C47D 0 C47D A9 00 LDA #0 0 C47F STA ZERO_FLAG 04 C48 05 C48 STILL_ADDRESS 06 C48 0 D9 C4 JSR READ_MEMORY 07 C C484 A5 9 LDA BUFFER+5 09 C ORA #40H 0 C STA BUFFER+5 C48A C48A A5 90 LDA BUFFER+4 C48C ORA #40H 4 C48E STA BUFFER+4 5 C490 6 C490 A5 8F LDA BUFFER+ 7 C ORA #40H 8 C F STA BUFFER+ 9 C496 0 C496 A5 8E LDA BUFFER+ C ORA #40H C49A 85 8E STA BUFFER+ C49C 4 C49C A5 8D LDA BUFFER+ 5 C49E 9 BF AND #~40H 6 C4A0 85 8D STA BUFFER+ 7 C4A 8 C4A A5 8C LDA BUFFER 9 C4A4 9 BF AND #~40H 0 C4A6 85 8C STA BUFFER C4A8 C4A8 60 RTS C4A9 ; C4A9 A9 0 KEY_DATA LDA # 5 C4AB STA STATE ; STATE = FOR DATA MODE 6 C4AD 7 C4AD A9 00 LDA #0 8 C4AF STA ZERO_FLAG 9 C4B 40 C4B 0 D9 C4 STILL_DATA JSR READ_MEMORY Page 5 of 8

39 8/0/05 6: PM 4 C4B4 4 C4B4 A5 9 LDA BUFFER+5 4 C4B6 9 BF AND #~40H 44 C4B STA BUFFER+5 45 C4BA 46 C4BA A5 90 LDA BUFFER+4 47 C4BC 9 BF AND #~40H 48 C4BE STA BUFFER+4 49 C4C0 50 C4C0 A5 8F LDA BUFFER+ 5 C4C 9 BF AND #~40H 5 C4C4 85 8F STA BUFFER+ 5 C4C6 54 C4C6 A5 8E LDA BUFFER+ 55 C4C8 9 BF AND #~40H 56 C4CA 85 8E STA BUFFER+ 57 C4CC 58 C4CC A5 8D LDA BUFFER+ 59 C4CE ORA #40H 60 C4D0 85 8D STA BUFFER+ 6 C4D 6 C4D A5 8C LDA BUFFER 6 C4D ORA #40H 64 C4D6 85 8C STA BUFFER 65 C4D8 66 C4D8 60 RTS 67 C4D9 68 C4D9 69 C4D9 ; READ MEMORY 70 C4D9 7 C4D9 READ_MEMORY 7 C4D9 7 C4D9 A5 96 LDA DISPLAY 74 C4DB STA HL 75 C4DD A5 97 LDA DISPLAY+ 76 C4DF STA HL+ 77 C4E 0 4B C JSR ADDRESS_DISPLAY 78 C4E4 A0 00 LDY #0 79 C4E6 B 84 LDA (HL),Y 80 C4E8 8 C4E8 ;STA GPIO 8 C4E8 8 C4E8 0 D C JSR DATA_DISPLAY 84 C4EB 60 RTS 85 C4EC ; C4EC 87 C4EC 0 C C5 HEX_SEND_FILE JSR HEX_ADDR 88 C4EF A9 AE LDA #0AEH 89 C4F 85 8C STA BUFFER 90 C4F A9 0 LDA # 9 C4F5 85 8D STA BUFFER+ 9 C4F7 60 RTS 9 C4F8 94 C4F8 0 C C5 HEX_SEND_FILE JSR HEX_ADDR 95 C4FB A9 8F LDA #08FH 96 C4FD 85 8C STA BUFFER 97 C4FF A9 0 LDA # 98 C D STA BUFFER+ 99 C50 60 RTS 00 C504 0 C504 ; C504 0 C504 0 C C5 HEX_REL JSR HEX_ADDR 04 C507 A9 AE LDA #0AEH 05 C C STA BUFFER 06 C50B A9 0 LDA # 07 C50D 85 8D STA BUFFER+ 08 C50F 60 RTS 09 C50 0 C50 C50 C50 0 C C5 HEX_REL6 JSR HEX_ADDR C5 A9 B LDA #0BH 4 C C STA BUFFER 5 C57 A9 0 LDA # 6 C D STA BUFFER+ Page 6 of 8

40 8/0/05 6: PM 7 C5B 60 RTS 8 C5C 9 C5C 0 C5C ; HEX KEY FOR ADDRESS C5C C5C A5 95 HEX_ADDR LDA ZERO_FLAG C5E C9 00 CMP #0 4 C50 D0 0A BNE SHIFT_ADDRESS 5 C5 6 C5 A9 0 LDA # 7 C STA ZERO_FLAG 8 C56 A9 00 LDA #0 9 C STA DISPLAY 0 C5A STA DISPLAY+ C5C C5C 8 SHIFT_ADDRESS CLC C5D 6 96 ROL DISPLAY 4 C5F 6 97 ROL DISPLAY+ 5 C5 6 C5 8 CLC 7 C ROL DISPLAY 8 C ROL DISPLAY+ 9 C56 40 C56 8 CLC 4 C ROL DISPLAY 4 C ROL DISPLAY+ 4 C5B 44 C5B 8 CLC 45 C5C 6 96 ROL DISPLAY 46 C5E 6 97 ROL DISPLAY+ 47 C C540 A5 96 LDA DISPLAY 49 C ORA REG_C 50 C STA DISPLAY 5 C546 5 C546 ; JSR READ_MEMORY 5 C C C4 JSR STILL_ADDRESS 55 C C RTS 57 C54A ; HEX KEY FOR DATA MODE C54A 59 C54A 60 C54A A5 95 HEX_DATA LDA ZERO_FLAG 6 C54C C9 00 CMP #0 6 C54E D0 0A BNE SHIFT_DATA 6 C C550 A9 0 LDA # 65 C STA ZERO_FLAG 66 C C554 A9 00 LDA #0 68 C556 A0 00 LDY #0 69 C STA (DISPLAY),Y 70 C55A 7 C55A A0 00 SHIFT_DATA LDY #0 7 C55C B 96 LDA (DISPLAY),Y 7 C55E 0A ASL A 74 C55F 0A ASL A 75 C560 0A ASL A 76 C56 0A ASL A 77 C ORA REG_C 78 C STA (DISPLAY),Y 79 C C566 ; JSR READ_MEMORY 8 C566 0 B C4 JSR STILL_DATA 8 C RTS 8 C56A 84 C56A ; INCREMENT CURRENT ADDRESS BY ONE 85 C56A ; 86 C56A 87 C56A A5 94 KEY_INC LDA STATE 88 C56C C9 05 CMP #5 89 C56E F0 D BEQ REL_KEY_PRESSED 90 C570 9 C570 C9 07 CMP #7 9 C57 F0 5 BEQ SEND_INC Page 7 of 8

41 8/0/05 6: PM 9 C C574 A9 0 LDA # 95 C STA STATE ; STATE = FOR DATA MODE 96 C C578 A9 00 LDA #0 98 C57A STA ZERO_FLAG 99 C57C 00 C57C 0 C57C 8 CLC 0 C57D A5 96 LDA DISPLAY 0 C57F 69 0 ADC # 04 C STA DISPLAY 05 C58 A5 97 LDA DISPLAY+ 06 C ADC #0 07 C STA DISPLAY+ 08 C589 ; JSR READ_MEMORY 09 C589 0 B C4 JSR STILL_DATA 0 C58C 60 RTS C58D C58D REL_KEY_PRESSED C58D 4 C58D ; Save start address 5 C58D 6 C58D A5 96 LDA DISPLAY 7 C58F 85 A0 STA START_ADDRESS 8 C59 A5 97 LDA DISPLAY+ 9 C59 85 A STA START_ADDRESS+ 0 C595 C595 A9 06 LDA #6 C STA STATE C599 A9 00 LDA #0 4 C59B STA ZERO_FLAG 5 C59D 6 C59D 0 8 C4 JSR STILL_ADDRESS 7 C5A0 A9 B LDA #0BH 8 C5A 85 8C STA BUFFER 9 C5A4 A9 0 LDA # 0 C5A6 85 8D STA BUFFER+ C5A8 60 RTS C5A9 C5A9 4 C5A9 SEND_INC ; Save start address 5 C5A9 6 C5A9 A5 96 LDA DISPLAY 7 C5AB 85 A0 STA START_ADDRESS 8 C5AD A5 97 LDA DISPLAY+ 9 C5AF 85 A STA START_ADDRESS+ 40 C5B 4 C5B A9 08 LDA #8 4 C5B STA STATE 4 C5B5 A9 00 LDA #0 44 C5B STA ZERO_FLAG 45 C5B9 46 C5B9 0 8 C4 JSR STILL_ADDRESS 47 C5BC A9 8F LDA #08FH 48 C5BE 85 8C STA BUFFER 49 C5C0 A9 0 LDA # 50 C5C 85 8D STA BUFFER+ 5 C5C4 60 RTS 5 C5C5 5 C5C5 54 C5C5 55 C5C5 56 C5C5 57 C5C5 58 C5C5 59 C5C5 ; DECREMENT CURRENT ADDRESS BY ONE 60 C5C5 ; 6 C5C5 6 C5C5 A9 0 KEY_DEC LDA # 6 C5C STA STATE ; STATE = FOR DATA MODE 64 C5C9 65 C5C9 A9 00 LDA #0 66 C5CB STA ZERO_FLAG 67 C5CD 68 C5CD Page 8 of 8

42 8/0/05 6: PM 69 C5CD 8 SEC 70 C5CE A5 96 LDA DISPLAY 7 C5D0 E9 0 SBC # 7 C5D STA DISPLAY 7 C5D4 A5 97 LDA DISPLAY+ 74 C5D6 E9 00 SBC #0 75 C5D STA DISPLAY+ 76 C5DA ; JSR READ_MEMORY 77 C5DA 0 B C4 JSR STILL_DATA 78 C5DD 60 RTS 79 C5DE 80 C5DE ; KEY PC, SET CURRENT USER ADDRESS 8 C5DE 8 C5DE A9 0 KEY_PC LDA # 8 C5E STA STATE ; STATE = FOR DATA MODE 84 C5E 85 C5E A9 00 LDA #0 86 C5E STA ZERO_FLAG 87 C5E6 88 C5E6 A5 98 LDA PC_USER 89 C5E STA DISPLAY 90 C5EA A5 99 LDA PC_USER+ 9 C5EC STA DISPLAY+ 9 C5EE ; JSR READ_MEMORY 9 C5EE 0 B C4 JSR STILL_DATA 94 C5F 60 RTS 95 C5F 96 C5F ; KEY REGSITER 97 C5F ; SET STATE TO FOR REGISTER INPUT WITH HEX KEY 98 C5F 99 C5F A9 0 KEY_REG LDA # 400 C5F STA STATE ; STATE = FOR REGISTER DISPLAY 40 C5F6 40 C5F6 A9 0 LDA # 40 C5F STA BUFFER C5FA A9 8F LDA #8FH 405 C5FC STA BUFFER C5FE A9 BE LDA #0BEH 407 C F STA BUFFER+ 408 C60 A9 0 LDA # 409 C E STA BUFFER+ 40 C606 A9 00 LDA #0 4 C D STA BUFFER+ 4 C60A 85 8C STA BUFFER 4 C60C 44 C60C 60 RTS 45 C60D 46 C60D ; C60D GO_STATE8 48 C60D 49 C60D A5 96 LDA DISPLAY 40 C60F 85 A STA DESTINATION ; DESTINATION IS NOW ENDING ADDRESS 4 C6 A5 97 LDA DISPLAY+ 4 C6 85 A STA DESTINATION+ 4 C65 44 C65 ; NOW COMPUTE NUMBER OF BYTE = DESTINATION - START_ADDRESS 45 C65 A5 A0 LDA START_ADDRESS 46 C STA HL 47 C69 A5 A LDA START_ADDRESS+ 48 C6B STA HL+ 49 C6D 40 C6D 8 SEC 4 C6E A5 A LDA DESTINATION 4 C60 E5 84 SBC HL 4 C6 85 A4 STA OFFSET_BYTE 44 C64 45 C64 A5 A LDA DESTINATION+ 46 C66 E5 85 SBC HL+ 47 C68 85 A5 STA OFFSET_BYTE+ ; OFFSET = NUMBER OF BYTE 48 C6A 49 C6A ; DEVIDE NUMBER OF BYTE WITH 6 TO GET NUMBER OF RECORD TO BE SENT 440 C6A 44 C6A 46 A5 LSR OFFSET_BYTE+ 44 C6C 66 A4 ROR OFFSET_BYTE 44 C6E 444 C6E 46 A5 LSR OFFSET_BYTE+ Page 9 of 8