ID 112C: MCU Architecture Evolution Now Better than Ever So who s the Best?

Transcription

1 ID 112C: MCU Architecture Evolution Now Better than Ever So who s the Best? Renesas Electronics America Inc. Mark Rootz Sr. Marketing Manager 12 October 2010 Version: 1.2

2 Mark Rootz Renesas Sr. Marketing Manager, 32-bit MCUs Definition and Promotion of 32-bit MCUs, N. America BSEE and MSEE from University of Missouri Rolla Seven years at STMicroelectronics Marketing Manager, STR9 32-bit ARM9 MCU line (France) Product Marketing Manager, upsd 8-bit 8051 MCU (San Jose CA) Product definition, technical marketing, business mgt, infrastructure Three years at Waferscale Inc Applications Manager, upsd MCUs Tools, software, training, documentation, solutions, silicon validation Three years at Hypertech Inc Project Manager and engineering Automotive powertrain controller software and hardware Twelve years at McDonnell Aircraft (now Boeing) Project Manager and engineering F15/F18 fighter avionics systems engineering (weapons, radar, navigation) Real-time simulation/test environment for complete avionics suite Embedded MCUs, MPUs, PLDs software and hardware design 2

3 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 3

4 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4

5 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display Legacy Cores Next-generation migration to RX General Purpose Up to 10 DMIPS, 130nm process 350 ua/mhz, 1uA standby Capacitive touch Ultra Low Power Up to 25 DMIPS, 150nm process 190 ua/mhz, 0.3uA standby Application-specific integration Embedded Security Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 5

6 RX: Performance without Sacrafice Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display Legacy Cores Next-generation migration to RX Key Attributes 7

7 RX Innovation Single Chip Enablement Coldfire CortexM3/M4 Kinetis TMS320 There are many 32-bit MCU/DSP Architectures covering varied capabilities PIC32 ARM7/9 In a single Family of devices, RX will Encompass / Exceed these Capabilities AVR32 8

8 RX Innovation Single Chip Enablement A single RX MCU can: Interpret a multitude of analog and digital input sources Generate precision analog and digital outputs in real time 9

9 RX Innovation Single Chip Enablement One MCU family for many applications * Photos are examples of end-products that could use an RX600 MCU. RX600 MCUs not necessarily used in these products. 10

10 RX Microcontrollers Best of the Best RX MCUs were conceived and designed from the best CPU architecture and technology available in the industry today delivering the perfect blend of: CPU and Memory Performance Analog and DSP Capability Power and Memory Efficiency Scalability Best of the Best Connectivity System Cost 11

11 Agenda Traditional Architectures 32-bit Choices RX Architecture Memory Speed vs. Performance Comparing with Other 32-bit MCUs Who s the Best? Q & A 12

12 Key Takeaways By the end of this session you will be able to: Understand Key MCU Architectural Elements Understand RX Architecture Compare RX with Other Architectures Make an Informed Decision 13

13 MCU, DSP, Digital Signal Controller What s the Difference? Traditional MCUs Single-Chip Device Interrupt Management System Fast Interrupt Response Efficient General Instructions Fine Power Management Wide Connectivity Choice Rich Supervisory Functions Easily Programmed in C Simple Low-Cost Tools Broad Ecosystem Simple Integer Math DSC Optimum Blend of MCU and DSP Traditional DSPs Multi-Chip Solution Single-Task Oriented Slower Interrupt Response Very Specific Instructions High Power Consumption Limited Connectivity Choice Few Supervisory Functions Complex Software More Expensive Special Tools Narrow Selection of 3 rd Parties Hardware Multiply and Divide Saturating Math 1-Cycle, wide Multiply-Accumulate Barrel Shifters Simultaneous Code/Data Access Floating Point Unit 14

14 The Evolved DSC, Many Practical Uses More MCUs are gaining DSC Features MCUs now have better analog capabilities Signal processing is a must Pushes bandwidth limits of traditional MCUs DSC Applications Motor Control Digital Power Management Audio Codecs Medical Monitoring Factory Automation Even benefits traditional MCU applications More work in less time 15

15 16/32-bit MCUs and DSCs in the Market MCUs Core Vendor CPU Width (bits) DMIPS/MHz of CPU Core Available Frequency (MHz) Flash Speed (MHz) Max Flash Size (KB) V850ES Renesas ARM CortexM3 Various <= PIC32 6 Microchip ARM7TDMI (Flash) Various <= DSCs Core Vendor CPU Width (bits) DMIPS/MHz of CPU Core Available Frequency (MHz) Flash Speed (MHz) Max Flash Size (KB) MAC (result width bits) SH-2A (Flash) Renesas and RX600 Renesas and AVR32 9,10,11 Atmel , 48, and 64 - ARM CortexM4 12,13 Various <= and STR9 ARM966E 14 ST and 64 - TMS320 Delfino (Flash) 15 TI 32 n/a TMS320 Piccolo 16 TI 32 n/a F8000/ Freescale No spec dspic 18 Microchip No spec FPU (width bits) 1 Core is capable of, no released product yet 2 Based on existing CM3 and CM4 -based MCUs in mass production today 3 Optional FPU 4 MIPS, not DMIPS 5 MIPS, not DMIPS. 80MHz external clock yields 40MIPS 6 Microchip. PIC32MX3XX/4XX Family Data Sheet, DS61143E 7 ARM, An Introduction to the ARM Cortex-M3 Processor, Oct Renesas 32-bit Flash MCU market assessment 9 Atmel, AVR32 brochure 7919F-AVR32-07/09/5K 10 Atmel, AVR32 Architecture Document 32000B-AVR32-11/07 11 Atmel, AT32UC3A datasheet 32058G-AVR32-01/09 12 ARM, CortexM4 Features Summary, 13 ARM, Cortex-M4 Technical Reference Manual r0p0 14 ST, STR91xFAxxx datasheet rev 6 15 TI, Data Manual, TMS320F283xx & TMS320F282xx DSCs, SPRS439H, March TI, Data Manual, TMS320F280xx MCus, SPRS584D, June Freescale, Data Sheet, 56F8323/56F bit DSCs, MC56F8323 rev 17, May Microchip, Data Sheet, dspic33fjxxxmcx06a/x08a/x10a, 16-bit DSCs, DS70594B,

16 CISC and RISC Traditional CISC Complex Instruction Set Computer GOAL: Small Memory Footprint Any inst accesses memory Many rich instructions Many addressing modes Variable instruction formats Smaller code size in memory Single register set Multi-clock instructions Less to no pipelining Longer interrupt response RX is Best of Both Mem-to-Mem instructions 73 Inst + DSP + FPU 10 addressing modes 1 to 8 byte instructions Up to 28% smaller code 16 x 32-bit registers One clock per instruction 5-stage pipeline 5-clock interrupt response Plus it has an FPU. Traditional RISC Reduced Instruction Set Computer GOAL: 1 Clock per Instruction Only load/store mem access Few instructions Few addressing modes Fixed instruction formats Larger code size in memory Multiple register sets Single-clock instructions Highly pipelined Faster interrupt response Let s Build an RX 17

17 64bits 64bits 64bits 64bits TICK TICK TICK TICK TICK TICK TICK TICK TICK RX Architecture CPU Core and Pipeline RX600 CISC CPU 100MHz CPU Core 1.65 DMIPS/MHz 9 x 32bit Control Registers 16 x 32bit General Purpose Registers Memory Protect Unit 32bit Floating Point Unit 16x16 or 32x32 MAC, 48bit or 80bit Result 32 x 32 DIV or MULT, 32bit or 64bit Result Interrupt Control On-Chip Debug 64bit path Instruction 32bit path Operand (Data) 5-STAGE PIPELINE F D E M W F E D F E D F M E D F F W M E D ENHANCED HARVARD ARCHITECTURE 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION D F W M E M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER E D F W M M E D F W Achieves One Clock-Per-Instruction (CPI) PRE-FETCH QUEUE (PFQ) Holds 4 to 32 Instructions for Slower Memory WRITE BUFFER Buffer Only for Writes For Slow Memory Inst Data Typically Flash Memory 64 RX Flash is 10 nsec, or 100 MHz zero-wait Memory Interface RX SRAM is also 10 nsec 32 Typically SRAM 18

18 RX Architecture Memory Interface RX600 MCU 64 bits RX600 CPU 100MHz PIPELINE PFQ BUFFER 64b INST 32b DATA BUS MATRIX 64 bits Bus Master of Internal Main Bus 1 32 bits SRAM, 100MHz Access Flash Memory, 100MHz Access External Bus Pins for CPU 32 bits External Bus Controller (BSC) 32 bits Internal Main Bus 1 Bus Bridge Peripherals 100 MHz Flash and SRAM means zero wait-state code and data access PFQ minimizes stalls from slower memory, such as external memory Bus master of Internal Bus 1 is the CPU Next we look at Internal Bus 2 19

19 One External Device Another External Device CNTL CNTL CNTL RX Architecture System Interface RX600 MCU RX600 CPU 100MHz PIPELINE PFQ BUFFER 64b INST 32b DATA BUS MATRIX 64 bits 64 bits External Bus Pins for CPU Bus Master of Internal Main Bus 1 32 bits External Bus Controller (BSC) 32 bits 32 bits 32 bits Internal Main Bus 1 Internal Main Bus 2 SRAM, 100MHz Access Flash Memory, 100MHz Access EXDMA (external bus master) Bus Bridge Bus Bridge DTC (bus master) DMAC (bus master) Ethernet DMAC (bus master) Multiple Peripheral Busses to Spread Bandwidth Loading CNTL Communication (USB, CAN, SCI, SPI, I2C) Timers (MTU, TPU, TMR, CMT) Analog (DAC, ADC, PGA) GPIO System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS) 2K FIFO FIFO 2K Ethernet MAC 20

20 RX CPU Core Performance DMIPS per MHz ARM7 ARM9 Cortex-M3 Cortex-M4 RX 1.65 DMIPS/MHz Note: Dhrystone 2.1 numbers for ARM processors taken from 21

21 Up to 43% Power Reduction Milliwatts* per DMIPS 43% less = RX600 = A Cortex-M3 based MCU Note: Derived from I DD specifications stated in product datasheets Low power modes 500mA* per MHz in Run Mode All Peripherals ON Four Low-Power Modes Sleep All-Module Stop Standby Deep Standby 2.5mA* in Deep Standby RX63x, RTC ON Low power design techniques Clock gating Low power HVT transistors in slower paths Power gating * Typical Conditions, 3.3V and 25 o C, all peripheral clocks on 22

22 RX600 Instruction Set = Single clock instruction 23

23 RX Instruction Set Summary and Size Instruction Length (bytes) List of Instructions Number of Instructions 1 NOP, RTS, BRK BCnd BRA 1 6% have minimum instruction length of 1 byte 2 RMPA, ROLC, RORC, SAT, SATR, POP, POPC, POPM, PUSHC, PUSHM, JMP, JSR, SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, SWHILE, CLRPSW, RTE, RTFI, SETPSW, WAIT 2-3 ABS, NEG, NOT, SHAR, SHLL, SHLR, RTSD MOVU, PUSH, BSR SUB, BCLR, BSET, BTST ADD, AND, CMP, MUL, OR MOV 1 3 ROTL, ROTR, REVL, REVW, INT, MVFC, MACHI, MACLO, MULHI, MULLO, MVFACHI, MVFACMI, MVTACHI, MVTACLO, RACW 3-5 FTOI, ROUND, SCCnd, BMCnd, BNOT SBB, ITOF, XCHG DIV, DIVU, EMUL, EMULU, MAX, MIN, TST, XOR, FADD, FCMP, FDIV, FMUL, FSUB, MVTC 4-6 ADC STNZ, STZ 2 MOV instruction length is 2-8 bytes Total = 89 instructions 49% have minimum instruction length of 2 bytes 42% have minimum instruction length of 3 bytes 24

24 MOV instruction example Function Source Destination IMM REG #IMM:32 Rd opcode #IMM:32 Rd #IMM:32 [Rd] opcode #IMM:32 Rd IMM MEM #IMM:16 #IMM:8 [Rd] [Rd] opcode opcode #IMM:16 #IMM:8 Rd Rd #IMM:32 dsp:16[rd] opcode dsp:16 #IMM:32 Rd REG REG Rs Rd REG MEM Rs [Rd] MEM REG [Rs] Rd opcode Rd Rs opcode Rd Rs opcode Rd Rs MEM MEM [Rs] [Rd] opcode Rd Rs Direct Memory-to-Memory operation Instruction length (bytes) 25

25 Example: Moving data in memory Traditional RISC RX LDR r3, [r1] STR r3, [r2] 2 bytes 2 bytes MOV [r1], [r2] 2 bytes Number of Cycles = 4 Code size = 4 bytes Number of Cycles = 3 Code size = 2 bytes Direct Memory-to-Memory operation allows RX to avoid lengthy load/store operations and results in smaller code size 26

26 Up to 28% Code Size Reduction Code size (relative) Motor control Data communication Data conversion Real-time control System control 28% less 19% less 17% less 25% less 25% less 1.0 = RX600 = A Cortex-M3 based MCU Note: Internal benchmark test, your results may vary 27

27 RX makes Out-of-Order Instruction Decisions Instructions 1) MOV [R1], R2 2) ADD R4, R5 3) SUB R4, R5 F D E M M WB F D S S E WB F S S Instructions 2) and 3) delayed, waiting on 1) D E WB CPU Clock Fetch Decode Execute Memory Write Back Stall 1) MOV [R1], R2 F D E M M WB 2) ADD R4, R5 F D S S E WB 3) SUB R4, R5 F S S D E WB Delay is Eliminated Is possible when there are no dependencies Multiple WB within same clock cycle OK if destination is different 28

28 IRQ Interrupt Handling = Automatic by CPU = Done by Firmware RX Normal Interrupt Resolve Interrupt 7clks typ. RX Fast Interrupt Resolve Interrupt, PC & PSW to Backup Regs PC & PSW to Stack Optional Push Gen Regs to Stack Optional Push Gen Regs to Stack ISR ISR Optional Pop Gen Regs from Stack PC&PSW from B/U Regs, Return 5 clks typ. 3 clks RX Fast Interrupt plus Gen Register Usage Resolve Interrupt, PC & PSW to Backup Regs ISR Return 5 clks typ. 3 clks Optional Pop Gen Regs from Stack Save many clocks POP PC & PSW from Stack 6 clks Return Save 5 clocks * ARM, Technical Reference Manuals: CortexM3 r1p1, CortexM4 r0p0 General CPU Registers R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 29

29 IRQ ARM Cortex M3 or M4* Resolve Interrupt, and Push CPU State and 5 Regs to Stack 12 clks ISR Interrupt Handling Pop CPU State and 5 regs from Stack, and Return 12 clks = Automatic by CPU = Done by Firmware RX Typical Interrupt Resolve Interrupt PC & PSW to Stack Optional Push Gen Regs to Stack ISR Optional Pop Gen Regs from Stack POP PC & PSW from Stack Return 7clks typ. 6 clks RX Fast Interrupt Resolve Interrupt, PC & PSW to Backup Regs RX Fast Interrupt plus Gen Register Usage Resolve Interrupt, PC & PSW to Backup Regs Optional Push Gen Regs to Stack ISR ISR Return 5 clks typ. 3 clks Optional Pop Gen Regs from Stack PC&PSW from B/U Regs, Return 5 clks typ. 3 clks Save up to 16 clocks * ARM, Technical Reference Manuals: CortexM3 r1p1, CortexM4 r0p0 30

30 FPU directly accesses General Registers Typical Operation RX Operation General Registers Load/Store No Load/Store Instructions Needed General Registers Floating- Point Unit Dedicated Data Registers Smaller code size Floating- Point Unit Higher FPU performance 31

31 FPU Applications Pump control Pressure regulator Digital filtering Thermo couple conversion Motor Control Flow Control Motion Control Renesas Electronics Electronics America America Inc. Inc.

32 FPU benefits: Two examples 2- Thermocouple Conversion Sensorless vector motor control compiled for Fixed Integer vs Floating Point FPU 1- Motor Control FPU provides the best combined execution time and code size FPU removes limitations due to scaling or saturation Improves accuracy for motor position and speed Increases motor efficiency Size in Byte Easy code development and maintenance. Write formulas directly into C code Reduces CPU loading Reduces code size 0 Look Up Table Fixed Point Math Software Library FPU Renesas Electronics Electronics America America Inc. Inc.

33 FPU Comparison Example: Conversion of thermocouple reading to temperature Thermocouple formula: Temperature = S (a n * x n ) n = 0 ~ 5; a 0 ~ a 5 are constants; x is A/D reading MCU Operating Frequency (MHZ) CPU Cycles (count) Actual Execution Time (usec) Execution Time with Ideal Memory (usec) Code Size (bytes) RX A CM3-based MCU > 16x Faster > 18x Smaller The FPU provides a dramatic increase in performance and code efficiency over math libraries. RX610 MCU: Renesas Compiler v0.02 Alpha, Size Max A CM3-based MCU: IAR Compiler v4.42a, Size Max 34

34 DSP Arithmetic Functions Repeated Multiply and Accumulate (RMPA) Multiply-Accumulate unit Memory (ADC Samples) 32-bit Memory (coefficients) Accumulate 80-bit 32-bit Multiply and Accumulate (MAC) General register 16-bit Multiply-Accumulate unit General register 16-bit 48-bit 35

35 Processing performance Performance and Flash Speed RX with 100 MHz Flash Competing MCU with 30 MHz Flash 30 MHz 60 MHz 100 MHz MCU frequency IF D E M WB IF D E M WB no wait IF W D D E E M WB M WB IF W D D E E M WB M WB 1 wait cycle IF W D W E D M WB E M WB IF W D W E D M WB E M WB 2 wait cycles 36

36 Completion Time, 100 iterations of FIR Algorithm (usec) DSP and Benefit of 10nsec Flash FIR Filter, RX600 and a CM3-based MCU A CM3 MCU Theorectical (73 CPU cycles per Iteration) A CM3 MCU Actual w/ Memory Acceleration A CM3 MCU Actual w/o Memory Acceleration RX600 Theorectical (46 CPU cycles per Iteration) Theoretical performance with No-Wait Memory for this CM3 MCU Performance loss due to Flash slower than CPU demand on a CM3 MCU Lower is Better RX600 Actual 81 wait Tap FIR Filter 2 wait 16 x 16 state to 32-bit accumulate states Better, but delay remains Mitigation effect of Memory Acceleration on a CM3 MCU Theoretical performance with No-Wait Memory for RX RX has 63% better performance MCU Operating Frequency (MHz) Theoretical is Identical to Actual performance for RX600 because of 10nsec Flash 8 Tap FIR Filter, 16 x 16 to 32bit accumulate RX610 MCU: Renesas compiler v1.0, Speed 2, macro used for RMPA A CM3-based MCU: IAR Compiler v , Speed Max 37

37 Operating Frequency (MHz) Flash-MCU History and Speed MCU Freq. Renesas Flash Freq. General Flash Freq. Renesas MONOS reaches 100MHz single cycle access (40nm) 100 (0.18um) (0.15um) (90nm) (0.35um) (0.5um) 10 (0.8um) Competitors Year Source: Renesas MONOS for EEPROM & IC-card Flash-MONOS 38

38 RX Family Roadmap Max MHz H8SX 32 Bit H8S 16 Bit R32C 32 Bit M16C 16 Bit RX600 Series 32 Bit, 90nm Extreme High Performance High Efficiency Family RX200 Series 32 Bit, 130 nm High Performance Low Power / Low Voltage RX nm 100MHz+ Existing MCUs

39 RX600 System On A Chip 40

40 RX600 Series Portfolio LGA64 5x5mm 0.5mm LQFP64 10x10mm 0.5mm LQFP80 14x14mm 0.65mm LGA85 7x7mm0. 65mm LQFP100 14x14mm 0.5mm LQFP112 20x20mm 0.65mm LQFP144 20x20mm 0.5mm LGA145 9x9mm 0.65mm BGA176 13x13m m0.8mm 41

41 RX Migration Between Series 2MB Flash RX600 Series - 100Mhz Extreme Performance 1MB Migration Within RX Family 512KB 384KB 256KB 128KB 64KB 32KB Common CPU & Peripherals RX200 Series - 50Mhz Low Power / Low Voltage / / Pins RX600: 500uA/MHz (all peripherals on), 2.5uA RTC Deep Standby, 2.7V to 3.6V RX200: 200uA/MHz (all peripherals on), <1uA RTC Deep Standby, 1.62V to 3.6V 42

42 RX Solutions Motor Control, RX62T Drive Sensorless PMAC Motor Field Oriented Control, 3-phase High integration, low system cost See for details Direct Drive TFT-LCD, RX62N Drive 4.3 Color WQVGA TFT-LCD by RGB Full basic graphic library and demo Source code included WiFi Connectivity, RX62N RDK Ethernet, USB Host/Device/USB, CAN Many surrounding functions/features Source code, built-in JTAG debugger b/g/n WiFi, RX62N Simple SPI connection to WiFi module Kit contains driver and examples Very low power b/g/n connectivity 43

43 RX Tools for Solutions Single Integrated Development & Debugging Environment HEW4 Plus Renesas C/C++ $1200* See for details On-Chip Debug JTAG and USB-HS connection Program Flash Single step execution 256 Software break points 12 Hardware breakpoints PC and data breakpoints On-chip Trace branches/cycles Read/Write SRAM Read/Write C variables Performance monitoring Non-intrusive Hot-plug capable $99* E1 HEW4 also supports GNU-RX C/C++ compiler, all at $0 Wide 3 rd Party Support for IDE, Compilers, Middleware, RTOS: Micrium, IAR, Segger, CMX, KPIT Cummings, freertos, and more Hi-Speed Trace JTAG, USB-HS, plus 6 lines connection Trace depth: - 2M branches/cycles SRAM monitor, 4 KB E20 $995* * Suggested resale price when sold individually 44

44 Comparing other 32-bit CPU Architectures Feature Unit RX600 CortexM3 1 CortexM4 2 AVR32A 3 PIC32 4 CPU Type - CISC, DSC RISC, MCU RISC, DSC RISC, DSC RISC, MCU Performance DMIPS/MHz Pipeline Length Stages Inst Lengths Bytes 1 to 8 2 and 4 2 and 4 2 and 4 2 and 4 # of Instructions For CPU,DSP 80, 9 97,3 97,83 115,8 129, 2 FPU # of instructions Yes, 8 No, 0 Option, 25 No, 0 No, 0 General Regs # of regs, bits 15 x x x x x 32 Min Intr Latency CPU Clocks 7 or 5 12 or 6 12 or 6 12 or 2 12 instructions MPU - Option Option Option Option No Bit Manipulation - Yes Yes Yes Yes Yes Debug Connection JTAG or 2-wire JTAG or 2-wire JTAG or 2-wire JTAG JTAG Hi-Speed Trace Connection 6-wire 6-wire 6-wire 12-wire 4,8,or 16-wire References: 1 ARM, CortexM3 Technical Reference Manual Revision:r1p1, ARMv7-M Architecture Reference Manual DDI 0403C_errata_v3 2 ARM, CortexM4 Technical Reference Manual Revision:r0p0, ARMv7-M Architecture Reference Manual DDI 0403C_errata_v3 3 Atmel, AVR32C Technical Reference Manual 32002A-AVR32-03/07 4 Microchip, PIC32MX Family Reference Manual DS611271C. MIPS Technology, MIPS32 Architecture for Programmers Vol II: MIPS32 Instruction Set, rev 2.5, MIPS32 MK4 Processor Core Datasheet, Rev

45 Who s the Best? You Decide based on what you have seen. To help your decision, here are publicly released benchmark results based on widely acknowledged Coremark TM from EEMBC. *Vendor *Processor Type *CPU Freq (MHz) *CoreMark / MHz *CoreMark *Compiler Comment Microchip PIC32MX360F512L MCU GCC Only 30 MHz operation Microchip PIC32MX360F512L MCU GCC Renesas RX610 DSC TI ST Stellaris LM3S9B96 CortexM3 STM32 CortexM3 120MHz. 90nm MCU MCU GNURX Keil V KEIL Microchip PIC24HJ128GP202 MCU GCC4.0.3 ST STM32F103RB CortexM3 MCU GCC NXP LPC1768 MCU ARMCC 4.0 TI ST Stellaris LM3S9B96 CortexM3 STM32F103RB CortexM3 MCU Keil V MCU GCC Freescale ColdFire MCF52233 MCU IAR EW 1.20 Freescale ColdFire MCF5274 MCU GCC4.1.1 *Source: as of 1 Sep 2010 Sorted by CoreMark/MHz Negative effect of slow Flash Full speed with no loss of performance Has new ART memory accelerator Negative effect of slow Flash Negative effect of slow Flash 46

46 Who s the Best? Now sorted by raw Coremark, not Coremark/MHz *Vendor *Processor Type ST STM32 CortexM3 120MHz. 90nm *CPU Freq (MHz) *CoreMark / MHz MCU Renesas RX610 DSC *CoreMark *Compiler Comment KEIL GNURX Microchip PIC32MX360F512L MCU GCC NXP LPC1768 MCU ARMCC 4.0 TI Stellaris LM3S9B96 CortexM3 MCU Keil V Freescale ColdFire MCF5274 MCU GCC4.1.1 ST TI STM32F103RB CortexM3 Stellaris LM3S9B96 CortexM3 MCU GCC MCU Keil V Microchip PIC32MX360F512L MCU GCC Microchip PIC24HJ128GP202 MCU GCC4.0.3 Freescale ColdFire MCF52233 MCU IAR EW 1.20 ST STM32F103RB CortexM3 Sorted by CoreMark/MHz MCU GCC Much Higher CPU freq needed for same result Positive effect of efficient CPU and fast Flash *Source: as of 1 Sep

47 Questions 1: What is the read access time of RX600 Flash Memory? 10 nsec (100MHz) across entire voltage range 2.7V to 3.6V 2: How many DMIPS/MHz does RX600 produce, and how many mw/dmip does it consume? 1.65 DMIPS/MHz, and 1mW/DMIPS 3: What does the RMPA instruction do? Repeat Multiply Accumulate. One instruction automatically multiplies data from two different memory arrays, and adds result to 80-bit accumulator, then post-increments to next two values. Repeats until specified array length is met. DSP!! 48

48 Innovation Single Chip Enablement See for details One MCU Family for many applications 49

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