Design Status of the CERN-SRAM macrocell

Transcription

1 Design Status of the CERN-SRAM macrocell IBM 0.25 µm User Group Meeting Imperial College, London June 2002 KLOUKINAS Kostas EP/CME-PS

2 CERN-SRAM specifications Scalable Design Configurable Bit organization (n x 9-bit). Configurable Memory Size. Synchronous Dual-Port Operation Allowing Read/Write operations on the same clock cycle. Typical Operating Frequency: 40 Mhz. Low Power Design Full Static Operation. Two stage hierarchical word decoding. Write Address Read Address RD WR CLK Data in SRAM Radiation Tolerant Design June 17, 2002 KLOUKINAS Kostas EP/CME-PS 2

3 SRAM Design in 0.25µ Row Decoder A6 Data in Write enable BLPC Bit Line Bit Line A0 WLPC Bit line precharge time Word Line Scalability is accomplised with the use of replica row cells and wordlines. Low Power is enhanced by gating bit-line & wordline precharge cycles when not accessing the memory. Word line precharge time Data out June 17, 2002 KLOUKINAS Kostas EP/CME-PS 3

4 Dual Port SRAM block diagram Din<m..0> WA<n..0> RA<n..0> Clk R W Addr. Reg. Addr. Reg. Data Reg. clk Timing Logic 7 Row decoder Write Drivers SRAM Array n-7 Read Logic Column decoder Word Line precharge Dual-port functionality is realized with a time sharing access mechanism. Registered Inputs Latched Outputs Data Latch Dout<m..0> June 17, 2002 KLOUKINAS Kostas EP/CME-PS 4

5 Timing of the SRAM Interface WRITE READ READ/WRITE t S t H t S t H clk WA RA W R Din Dout June 17, 2002 KLOUKINAS Kostas EP/CME-PS 5

6 Basic Layout Blocks WordLine Buffers SRAM column, 128 x 9bits (50.4 µm x µm) Input Data Registers Row Decoder Address Registers Timing logic Column Decoder Output Data Mux Output Data Latches June 17, 2002 KLOUKINAS Kostas EP/CME-PS 6

7 Modular SRAM design. A<11..5> Block Column 1K x 9 2K x 9 4K x rows 128 rows Row Decoder 4:1 A<2..1> A<0> 4:1 4:1 4:1 4:1 4:1 4:1 4:1 A<4..3> 4:1 4:1 2:1 D<8..0> June 17, 2002 KLOUKINAS Kostas EP/CME-PS 7

8 Submitted SRAM Chips 1 st st Prototype (CERN (CERN MPW MPW 4) 4) Configuration: 1Kx9 bit bit Size: ~560µm x 1,300µm Area: ~0.73mm 2 2 Submitted: Oct. Oct Chip Received: Feb Feb 2001 Tested: Apr. Apr Status: O.K. O.K. Design: CERN_SRAM_1K Designer: Kloukinas Kostas EP/CME-PS June 17, 2002 KLOUKINAS Kostas EP/CME-PS 8

9 Submitted SRAM Chips 2 nd nd Prototype (CERN (CERN MPW MPW 5) 5) Configuration: 4Kx9 bit bit Size: ~1,850µm x 1,300µm Area: ~2.4mm 2 2 Submitted: May May 2001 Chip Received: Aug Tested: Oct. Oct Status: O.K. O.K. Design: CERN_SRAM_4K Designer: Kloukinas Kostas EP/CME-PS June 17, 2002 KLOUKINAS Kostas EP/CME-PS 9

10 CERN SRAM test results Test chip: 4Kx9bit Functional tests Max operating frequency: Read only operations per clock cycle : 2.5V Read/Write operations per clock cycle : 2.5V Read access time: 2.5V Power dissipation: 15µW / 2.5V for R/W operations within the same clock cycle 40MHz). Tests for process variations: Differences in the access time < 1ns for: -3σ, 1.5σ, typ, +1.5σ, +3σ June 17, 2002 KLOUKINAS Kostas EP/CME-PS 10

11 Clock Duty Cycle Tests 50MHz Read per cycle Read/Write per cycle Test chip: 4Kx9bit R W 55MHz Read per cycle Read/Write per cycle Duty Cycle variations 50 MHz 55 MHz 60 MHz 50% ± 20% 50% ± 10% 50% ± 5% June 17, 2002 KLOUKINAS Kostas EP/CME-PS 11

12 Power dissipation CERN SRAM 4K Test chip: 4Kx9bit Power Dissipation (uw) Standby NOP Read Write Read/Write Power Operation (uw/mhz) Standby 0.10 NOP 1.90 Read 7.40 Write Read/Write Clock frequency (MHz) Operation Standby NOP Read Write Read/Write Test Conditions Description Pattern File No operation, addr. & data in to highz nop1.set No operation, addr. & data changing in every clnop2.set checkerboard data pattern SRAM_0.set checkerboard data pattern SRAM_0.set checkerboard data pattern SRAM_1.set June 17, 2002 KLOUKINAS Kostas EP/CME-PS 12

13 Irradiation Tests Ionizing Total Dose: up to 10MRad No increase in power dissipation. No measurable degradation in performance. Single Event Upset: under preparation (in collaboration with CERN EP/MIC group) Test chip: 4Kx9bit June 17, 2002 KLOUKINAS Kostas EP/CME-PS 13

14 CERN SRAM popularity! ATLAS SCAC chip Memory configuration: 128 x 18bit Detector: ATLAS tracker Lab: NEVIS Labs Designer: Stephan Boettcher Status: Tested O.K. ATLAS DTMROC chip Memory configuration: 128 x 153 bits Detector: ATLAS TRT Lab: CERN Designer: Robert Szczygiel Status: Tested O.K. CMS K chip Memory configuration: 2K x 18 bits Detector: CMS Preshower Lab: CERN Designer: Kostas Kloukinas Status: work in progress ATLAS MCC chip Memory configuration: 128 x 27bit Detector: ATLAS PIXEL Lab: INFN Genova Designer: Roberto Beccherle Status: Tested O.K. ALICE AMBRA chip Memory configuration: 16K X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Torino Designer: Gianni Mazza Status: Submitted ALICE CARLOS chip Memory configuration: 256 X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Bologna Designer: Alessandro Gabrielli Status: work in progress June 17, 2002 KLOUKINAS Kostas EP/CME-PS 14

15 Design Support Delivery of SRAM design library Half a day design CERN Designer configures his macrocell Review the macrocell design June 17, 2002 KLOUKINAS Kostas EP/CME-PS 15

16 Conclusions Design Status Design meets specifications. Macrocell has been successfully used in a number of ASIC designs. Future Plans None. No further development is foreseen. Design Support Contact Person: Kostas.Kloukinas@CERN.ch Information on the Web June 17, 2002 KLOUKINAS Kostas EP/CME-PS 16