Chapter 0 Introduction

Transcription

1 Chapter 0 Introduction Jin-Fu Li Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan

2 Applications of ICs Consumer Electronics Automotive Electronics Green Power Electronics Biomedical Electronics Jin-Fu Li, EE, NCU 2

3 System on Chip SOC a product class and design style that integrates technology and design elements from other system driver classes (microprocessor unit, embedded memory, analog/mixed-signal component as well as reprogrammable logic) into a wide range of high-complexity, high-value semiconductor products (ITRS 2011) Jin-Fu Li, EE, NCU 3

4 Trends for SOC Consumer Portable Driver Source: ITRS 2011 Jin-Fu Li, EE, NCU 4

5 SOC Consumer Portable Driver Architecture Source: ITRS 2011 Jin-Fu Li, EE, NCU 5

6 SOC Consumer Portable Design Complexity Source: ITRS 2011 Jin-Fu Li, EE, NCU 6

7 SOC Consumer Portable Power Consumption Source: ITRS 2011 Jin-Fu Li, EE, NCU 7

8 SOC Consumer Portable Processing Performance Source: ITRS 2011 Jin-Fu Li, EE, NCU 8

9 Source: ITRS 2010 Jin-Fu Li, EE, NCU 9

10 Modern SOC Design Challenges Power issue: Energy consumption, power dissipation, power delivery Reliability issue Variability Soft error (single-event upset) Device degradation Yield issue. Y=e -AD Jin-Fu Li, EE, NCU 10

11 Architecture of Current SOC Chips Multi-core chip architecture Use multiple identical cores to design a chip Network-on-chip communication infrastructure Multiple point-to-point data links interconnected by switches (i.e., routers) μ Engine RAM unit Compute unit DDR2 Controller DDR2 Controller Source: IEEE Computer, Source: IEEE Micro, Jin-Fu Li, EE, NCU 11

12 Examples SPARC V9 (Sun) Source: IEEE JSSC, x4 mesh built with Xpipes library components Cell Processor (IBM) Teraflops processor (Intel) Source: IEEE JSSC, Niagara2 (Sun) Source: IEEE Micro, Source: IEEE JSSC, Source: IEEE Micro, Jin-Fu Li, EE, NCU 12

13 Cell Processor (JSSC, Jan. 2006) Jin-Fu Li, EE, NCU 13

14 Example: Niagara2 & POWER6 (JSSC, 2008) Niagara2 (Sun) POWER6 (IBM) Design-for-Testability Features: 1. Logic BIST 2. BIST for arrays 3. BISR for arrays 4. Design-for-Testability Features: Scans + ATPG 2. BIST for arrays 3.. Jin-Fu Li, EE, NCU 14

15 Example: SPARC (JSSC, 2011) Process: TSMC 40nm Metal layers (Cu): 11 Transistor types: 4 # of Cores: 16 6MB L2 cache Die area: 377mm 2 # of pins: 2117 Jin-Fu Li, EE, NCU 15

16 Number of Transistors per Microprocessor Chip Source: Proceedings of IEEE, May Jin-Fu Li, EE, NCU 16

17 Transistor Cost Source: Proceedings of IEEE, May Jin-Fu Li, EE, NCU 17

18 Downsizing Rates of Audio/Video Products Source: Proceedings of IEEE, May Jin-Fu Li, EE, NCU 18

19 Fundamental Elements of Electronic Systems Processor (multi-core architecture) Computation Memory Data (Content) Communication Interface; Bus; Network Jin-Fu Li, EE, NCU 19

20 3D Integration Technology Technology evolution Bipolar CMOS Multicore 3D integration + System-in-package (3D-SiP) System-in-package stacking dies using bonding wires Source: ISQED, Jin-Fu Li, EE, NCU 20

21 Emerging IC Design Technology 3D IC 3D integration stacking dies using through silicon via (TSV) Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack Processor Energy/Power Source: IBM, Source: Proceedings of IEEE, Jan Jin-Fu Li, EE, NCU 21

22 Advantages of 3D IC: Heterogeneous Integration Combine disparate technologies DRAM, flash, RF, etc. Combine different technology nodes For example: 65nm technology and 45nm technology Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack Processor Energy/Power Source: Proceedings of IEEE, Jan Jin-Fu Li, EE, NCU 22

23 Advantages of 3D IC: Low Power & Small Form Factor Power SOB SIP 3D-IC Technology Jin-Fu Li, EE, NCU 23

24 Advantages of 3D IC: High Bandwidth 3D IC allows much more IO resources than 2D IC For example, Stacking of processor and memory Memory Memory CPU CPU Bandwidth is limited by IOs Many TSVs are allowed for high bandwidth transportation Jin-Fu Li, EE, NCU 24

25 Applications of 3D ICs Short-term Midium-term Long-term Memory wall Memory capacity Smart or Trusted Memory Heterogeneous Integration Source: Proceedings of IEEE Source: Proceedings of IEEE Heterogeneous Integration & High Complexity Systems (terabyte of internet traffic/sec; petabytes of data stored in the cloud; etc.) Jin-Fu Li, EE, NCU 25

26 Possible Applications: Smart Phone An important development direction is the interaction with the user, and sensorbased smartphones. Motion sensors, accelerometers and gesture reading devices should improve a lot this interaction, and combined with the connectivity widespread, it should create a new set of opportunities for consumers. Unfortunately, an aspect which won't mean a major leap in smartphones development is battery life. Augmented Reality Map Jin-Fu Li, EE, NCU 26

27 Possible Applications: Automotive Cloud Service System Source: IEEE Computer, June Requirement: high bandwidth (real time) and low power; small form factor Jin-Fu Li, EE, NCU 27

28 Possible Applications: Active Safety for Automotive Subaru introduced the EyeSight system version 2, introduced in 2010, which can stop a vehicle traveling at up to 30 km/h via a stereo camera mounted inside the front window. A 3D image processor analyzes the images that two cameras capture and estimates the distance to the obstacle. Source: IEEE Computer, June Jin-Fu Li, EE, NCU 28

29 Possible Applications: Healthcare Adhesive-bandage-type sensor Source: Proceedings of IEEE, May Jin-Fu Li, EE, NCU 29

30 Possible Applications: Healthcare Bionic ear Source: Proceedings of IEEE, May Jin-Fu Li, EE, NCU 30

31 Possible Applications: Superspecs Source: Mail Online, Jin-Fu Li, EE, NCU 31

32 Challenges of 3D-IC Implementations Yield Design for resiliency Thermal Can we overcome it? Test Reliability Source: IBM, Jin-Fu Li, EE, NCU 32

33 What will You Learn from This Course? Memory array Memory Subsystems Control Input Processor Link Input/Output Datapath Output CPU To/from network I/O Source: IEEE JSSC, Chip Architecture Low-Power Design Testing Jin-Fu Li, EE, NCU 33