Over the SoC Verification Hurdles

Transcription

1 Yuan Ze University Over the SoC Verification Hurdles November 7, 2006 Chong-Min Kyung

2 Contents Part 1 ; Introduction to KAIST Part 2 ; Verification Agony Part 3 ; programmable processor development Part 4 ; H.264 decoder case Conclusion Over the SoC Veri Hurdles (YZU) 2

3 PART Over the SoC Veri Hurdles (YZU) 3

4 Korea s 10 New Growth Engines ( Percentage of SoC ; Overall 34%) Semiconductor (40%) Robot (25%) Home Network (50%) Car & Telematics (50%) Display (25%) Digital TV (80%) Mobile Communications (70%) Software & Digital Contents Batteries New Medicine & Bio Over the SoC Veri Hurdles (YZU) 4

5 KAIST (Korea Advanced Institute of Science and Technology)

6 KAIST as a whole About 400 Faculty members in 20 departments (EECS being the biggest with 85(52EE, 32CS) professors) As of 2003, produced 5380 Ph.D. s 14,800 Masters, and 6520 Bachelors. Current Population : 2980 BS, 1970 MS, and 2360 Ph.D. students Over the SoC Veri Hurdles (YZU) 6

7 Distinctive Features of KAIST Belonging to Ministry of Science and Technology (not Ministry of Education) No tuition fees, scholarship for all students Exemption of military service for Ph.D. students Over the SoC Veri Hurdles (YZU) 7

8 Why was KAIST founded? Based on Report of Frederick Terman in 1971 To supply competitive engineering graduates to the labor-intensive industry Initial focus was on master level Due to the serious opposition by existing universities and Minister of Education, KAIST, a purely a graduate school, belonged to Ministry of Science and Technology from the beginning. Has become a model for engineering graduate school in Korea. JAIST and NAIST founded in Japan. So Mission was completed. Now what? Over the SoC Veri Hurdles (YZU) 8

9 Students After Graduation Total number of Graduates have been 26,359 since its inauguration. 100% 80% Other 60% Government University 40% 20% Research Industry 0% Advanced Studies B.S.(6,442) M.S.(14,710) Ph.D.(5,207) Over the SoC Veri Hurdles (YZU) 9

10 K A I S T Electrical Engineering A place where young scientists Dreams and enthusiasm are alive Over the SoC Veri Hurdles (YZU) 10

11 Department of KAIST Research-oriented department with 15 research centers each with > US$1M annual funding 64 Start-up companies started by graduates since faculty members, 760 graduate students (480 Ph.D. and 280 M.S. candidates graduate) and 350 undergraduate students Over the SoC Veri Hurdles (YZU) 11

12 Academics KAIST Electrical Engineering 393 Faculty 53 (13%) 5,478 BS 1,454 /MS 1,964 /Ph.D 2,060 (BS freshmen are excepted) 29,199 BS 7,393 /MS 15,816 /Ph.D 5,990 Enrollment Graduates 928 (17%) BS 281 /MS 261 /Ph.D 386 4,914 (17%) BS 1,451 /MS 2,426 /Ph.D Million USD 2003 Research Expenditures 20.6 Million USD (23%) Over the SoC Veri Hurdles (YZU) 12

13 Facilities Information & Electronics B/D(6th) Center for HighPerformance Integrated Systmes Information & Electronics B/D(5th) LG Semicon Hall Semiconductor B/D Computer Lab Image Processing B/D Over the SoC Veri Hurdles (YZU) 13 Satellite Technology Research Center

14 CHiPS (Center for High- Performance Integrated Systems) Over the SoC Veri Hurdles (YZU) 14

15 PART Over the SoC Veri Hurdles (YZU) 15

16 Challenges with SoC (System-on-Chip) Verification Short time-to-market High gate count Needs Co-verification H/W and S/W components in a single platform. Co-design of multiple heterogeneous components. First-time success is a MUST. No second chance! Over the SoC Veri Hurdles (YZU) 16

17 Overview of Verification Methodologies Simulation Basic verification tool Hardware Accelerated Simulation Semi-formal Verification Emulation Formal Verification Prototyping Over the SoC Veri Hurdles (YZU) 17

18 Designer s agony Verification is extremely difficult to complete. And the cost of untreated bugs is extremely high, especially toward the pipeline end and toward the deeper submicron process Over the SoC Veri Hurdles (YZU) 18

19 Verification Performance Gap ; more serious than the design productivity gap Growing gap between the demand for verification and the simulation technology offered by various options. Verification Performance Gap Simulation performance Small ASIC Medium ASIC Complex ASIC SOC Verification complexity Over the SoC Veri Hurdles (YZU) 19 Design complexity System-on-a-chip verification, 2001 P.Rashinkar

20 Bug Fixing Cost varies in Time Cost of fixing a bug increases as design progresses. Need verification method at early design stage Cost of Fixing a Bug Behavioral Design RTL Design Gate Level Design Device Production Over the SoC Veri Hurdles (YZU) 20 Verification methodology manual, 2000 TransEDA

21 PART Over the SoC Veri Hurdles (YZU) 21

22 Case #1 (Processor development) C model for ISS + C model for all environment incl. hardware Compiler to be developed in parallel We wanted to verify our understanding of x86 instruction behavior before any detailed design as well as implementation Over the SoC Veri Hurdles (YZU) 22

23 HK386 (1995.9) Chip Feature 32-bit microprocessor which is pin and instruction level compatible with Intel s i μm CMOS technology Package: 132-pin PGA Die size: cm 2 Architectural Feature Pipelined Instruction Execution 64 Terabytes Virtual Address Space Integrated Memory Management Unit (MMU) On-Chip Address Translation Caches Over the SoC Veri Hurdles (YZU) 23

24 VPC(Virtual PC) Environment CPU model intel i386 Interface routines PC Chipset model BIOS (Assembly and C routine) X window Keyboard with Xlib Memory x86 interface Debugging feature Virtual PC platform interface Simulation & Debugging UNIX file system PC model Platform Over the SoC Veri Hurdles (YZU) 24

25 HK386 HK Over the SoC Veri Hurdles (YZU) 25

26 HK386 (1995) Design Specification Instruction level, Pin-to-Pin compatible with i386 Operation speed : 40 MHz 0.8 μm DLM CMOS ASIC Test Programs MS DOS 6.0, Windows 3.1, Office 4.0 CAD tools, games, etc.. MS Win. 3.1 MS Office MaxPlus II Over the SoC Veri Hurdles (YZU) 26

27 Microprocessor Design Verification CPU Model Methodology more refined model C Language HDL Instruction Behavior In C (Polaris) Microarchitecture in C RTL Verilog Gate-Level Verilog Virtual Chip FlexPC MCV PLI Real Mother-board H/W Virtual PC in C (VPC) Target Environment MCV : Microcode Verifier PLI : Programming Language Over the SoC Veri Hurdles (YZU) 27

28 Virtual Chip : Verify Early, In-System Virtual Chip: Making Functional Models Work on Real Target System [DAC98] Simulating ISS of a Processor Chip along with real target environment Chip Model;ISS Chip Socket Target board Host computer as Virtual Chip cable Pin Signal Generator with Buffers Over the SoC Veri Hurdles (YZU) 28

29 C Model Verifier Target System Simulation Host PentiumPro 200MHz CPU socket PSG PSG 2 ALTERA EPM7192 Target System 500kHz Pentium Slow-downed Motherboard Over the SoC Veri Hurdles (YZU) 29

30 isave design process Host computer compiles the algorithm and downloads it to isave. Processing Engine (PE) executes the chip model in C/C++, SystemC, etc. Target Interface Engine (TIE) takes care of the chip interface with the target board. Target board where isave is plugged into instead of the real chip Over the SoC Veri Hurdles (YZU) 30

31 Semi-real-time MPEG2 decoding - MPEG2 decoding - Emulation with isave prototype directly plugged into target Over the SoC Veri Hurdles (YZU) 31

32 Reducing TTM using Virtual Chip Conventional design flow H/W System Application S/W Architectural model Board design design RTL model Gate-level model idle idle H/W Emulation H/W prototype (H/W emulation) Verification w/ H/W Virtual Chip design flow; EARLY,IN-SYSTEM H/W System Architectural model Board design design RTL model Gate-level model Application S/W Over the SoC Veri Hurdles (YZU) 32 H/W prototype (Virtual Chip) H/W Emulation Verification w/ H/W Design time is drastically reduced

33 x86 Emulation Configuration Probe Module 500kHz Slowed-Down PC Target Interface Board Hardware Emulator Over the SoC Veri Hurdles (YZU) 33

34 Instructions (thousand) Booting Windows 20M instructions on Marcia 0 Simulation debugs, Emulation approves. setup version update 1 HDL saver Attached HDL Simulation Over the SoC Veri Hurdles (YZU) 34 Time (weeks) version update 2 version update 3 Windows Hardware Emulation DOS

35 What about Emulation? Extremely expensive Needs a lot of time for Compile Needs an expensive slowed-down PC ($20,000 for 500kHz clocking) However worked at the last minute Finding bugs is not easy Needs a systematic and well-distributed procedure for verification than just one big equipment Over the SoC Veri Hurdles (YZU) 35

36 PART Over the SoC Veri Hurdles (YZU) 36

37 Case #3 ; Overview of H.264 Digital Multimedia Broadcasting (DMB) Video Standard: H.264 Simulation with ARM ISS to profile H.264 decoder s functions Target Processor: ARM946-ES Entropy Decoding Quantized Coefficients Inverse Transform + + Deblocking Filter Decoded Macroblock Intra-Frame Prediction Over the SoC Veri Hurdles (YZU) 37 Motion Data Intra/Inter Motion Comp. Prediction Memory

38 Algorithm Verification and HW/SW partitioning Profiling Results Deblocking Filter: 19.25% Entropy decoding: 45.58% Inverse Transform: 17.00% Entropy Decoding Entropy Decoding Deblocking Filter Quantized Coefficients Hardware Inverse Transform Inverse Transform Inverse Quantization Intra/Inter Motion Data + + Deblocking Filter Intra-Frame Prediction Motion Comp. Prediction Intra Prediction Motion Compensation Memory Software Decoded Macroblock Over the SoC Veri Hurdles (YZU) 38

39 Co-simulation S/W (C code) Intra Prediction Motion Compensation SimBase H/W (Verilog) Entropy Decoding Deblocking Filter Inverse Transform/Quantization ARM ISS (AXD) IPC HDL Simulator (Modelsim) Communication channel Entropy Decoding Intra Prediction Deblocking Filter Motion Compensation Inverse Transform Inverse Quantization Over the SoC Veri Hurdles (YZU) 39

40 Co-emulation Host PC ARM core module JTAG Intra Prediction Motion Compensation Entropy Decoding PCI channel RS232C Deblocking Filter Inverse Transform Inverse Quantization Simulation Accelerator DPP port ProBase Over the SoC Veri Hurdles (YZU) 40

41 intuition ; ARM + FPGA + simulation Communication localization Bus partitioning & communication localization DMA: Direct Memory Access Controller PIC: Programmable Interrupt Controller A dedicated frame memory access path to LCD controller A separated bus, DMA controller, and dual-port memory for audio controller How do we know bandwidth requirements before running software on top of hardware. How do we determine access priority and interrupt priority Over the SoC Veri Hurdles (YZU) 41

42 intuition ARM/AMBA ARM Core Tile Host I/F based on USB DDR2 SDRAM DDR2 SDRAM DIMM ZBT SSRAM Host I/F & BILA DDR2 controller ZBT & Flash controller Flash SD/MMC FPGA MMC controller B2B connector LCD controller Color graphic LCD ARM ARM interface ZBT SSRAM USB controller Ethernet controller Audio codec PS/2 controller UART GPIO USB OTG Ethernet (10/100) AC97 codec PS/2 (x2) Line driver (x2) Touch screen AMBA bus structure Over the SoC Veri Hurdles (YZU) 42

43 Dual-iNTUITION for MPSoC Touch-screen LCD ARM Core Tile ARM Core Tile intuition basic Over the SoC Veri Hurdles (YZU) 43

44 AMBA Architecture Builder SoC design concept Automatic synthesis, P&R AMBA architecture builder Over the SoC Veri Hurdles (YZU) 44

45 Application Example 1 ARM-Based Audio System Development Development Hardware development using AMBA architecture builder Firmware development using ARM compiler and ICE intuition ARM11 SRAM Flash icon AMBA Bus System Blutooth AC97 MMC SRAM (Frame buf) DDR2 (Audio buf) Over the SoC Veri Hurdles (YZU) 45

46 Application Example 2 Windows-CE Development Microsoft Platform Builder (OS development) Microsoft Embedded Visual C++ (Application development) OS image Ethernet Dynalith iflash (Flash ROM programming) Over the SoC Veri Hurdles (YZU) 46

47 An example of SoC design & Verification Serial Memory SoC Ethernet Video Audio What are necessary? System design Hardware design Software programming Inter-disciplinary HW/SW co-design & verification Over the SoC Veri Hurdles (YZU) 47

48 OpenIDEA & incite usage example Over the SoC Veri Hurdles (YZU) 48

49 Software Simulation PC/ Workstation IDE GDB ISS Peri. Model Peri. Model Peri. Model Over the SoC Veri Hurdles (YZU) 49

50 PC/ Workstation HW-SW Co-Simulation IDE GDB ISS HDL Simulator Bus Model Peri. Model Peri. Model OR IDE GDB ISS HDL Simulator Processor Model Bus Model Peri. Model Peri. Model Over the SoC Veri Hurdles (YZU) 50

51 HW-SW Co-Emulation PC/ Workstation incite HDL Simulator HW Board IDE GDB Proc. Model Bus Model USB Bus Model Peri. Model Peri. Model Peri. Model OR HW Board IDE GDB USB Processor Model Bus Model Peri. Model Peri. Model Over the SoC Veri Hurdles (YZU) 51

52 Concluding Remarks Verification is a critical process, because it is difficult, costly, and incurs huge penalty, when not properly dealt with Two different examples Programmable processor (x86) Fixed function accelerator (H.264 decoder) Over the SoC Veri Hurdles (YZU) 52

53 Thank you! Over the SoC Veri Hurdles (YZU) 53