What Comes Next? Reconfigurable Nanoelectronics and Defect Tolerance. Technology Shifts. Size Matters. Ops/sec/$
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1 Reconfigurable Nanoelectronics and Defect Tolerance Seth Copen Goldstein Carnegie Mellon University HLDVT 11/13/03 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 1 1.E+11 1.E+10 1.E+09 1.E+06 1.E+03 1.E+00 What Comes Next? Ops/sec/$ Mechanical/ Relays Tubes/ Transistor doubles every 1.0 years CMOS doubles every few months? nanometer doubles every doubles every 1.E years 2.3 years Combination of Hans Moravac + Larry Roberts + Gordon Bell WordSize*ops/s/sysprice 1.E From Gray Turing Award Lecture HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 2 Technology Shifts Size Matters Size of Devices Inches to Microns to Nanometers Type of Interconnect Rods to Lithowires to Nanowires Method of Fabrication Hammers to Light to Self-Assembly Largest Sustainable System 10 1 to 10 8 to Reliability Bad to Excellent to Unknown As we scale down: Devices become more variable more faulty (defects & faults) numerous Fabrication becomes More constrained More expensive Design becomes More complicated More expensive CMOS Drain Gate Source MIT IBM 1 dopant atom Nano HP HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 3 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 4
2 As we scale down: Devices become more variable more faulty (defects & faults) numerous Fabrication becomes More constrained More expensive Design becomes More complicated More expensive Size Matters Mask Cost / Wafer Level Exposure ($) Logic Ts (M)/Chip Requires: Affordable Total Cost / Wafer Level Exposure Wafer Exposures/Mask um 0.25 um 0.18 um 0.13 um Karen Brown, NIST SIA Roadmap Generation Complexity '81 '83 '85 '87 '89 '93 '95 '97 '99 '01 '03 SEMATECH Productivity Defect tolerant architectures Higher level specification Universal substrate '05 '07 '09 Logic Ts (K)/Staff Mon As we scale down: Devices become more variable more faulty (defects & faults) numerous Fabrication becomes More constrained More expensive Design becomes More complicated More expensive A CMOS RAM cell Size Matters Mask Cost / Wafer Level Exposure ($) Logic Ts (M)/Chip NanoRAM cell Requires: Affordable Total Cost / Wafer Level Exposure Wafer Exposures/Mask um 0.25 um 0.18 um 0.13 um Karen Brown, NIST SIA Roadmap Generation Complexity '81 '83 '85 '87 '89 '93 '95 '97 '99 '01 '03 SEMATECH Productivity Defect tolerant architectures Higher level specification Universal substrate '05 '07 '09 Logic Ts (K)/Staff Mon HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 5 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 6 Defect Tolerant Architectures Features: Regular topology Homogenous resources Fine-grained? Post-fabrication modification Example from today: DRAM Requires external device for testing Requires external device for repair Logic? FPGA Key is redundancy HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 7 FPGA Interconnection network Universal gates and/or storage elements Programmable Switches HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 8
3 Reconfigurable Computing Reconfigurability & DFT General-Purpose int reverse(int x) int k,r=0; for (k=0; k<64; k++) r = x&1; x = x >> 1; r = r << 1; int func(int* a,int *b) int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b Compiler Custom Hardware General-Purpose Custom Hardware Place& Route FPGA computing fabric Regular periodic Fine-grained Homogenous programs circuits Logic Blocks Routing Resources HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 9 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 10 Reconfigurability & DFT DFT tool flow Place& Route FPGA computing fabric Regular Tester Place& Route periodic Fine-grained Homogenous programs circuits Aides defect tolerance Fabric (Async.) Circuit Netlist Defect Unaware Place-and- Route Defect Map Soft Config. Defect Aware Place-and- Route Hard Config. HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 11 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 12
4 Finding The Defects Built-In Self-Test Need to discover the characteristics of the individual components, but Can t selectively stimulate or probe the components Download test machines vertically HOST Thin link Configure the device to test itself! HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 13 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 14 Built-In Self-Test Built-In Self-Test vertically horizontally Combine data And Identify fault! Configure the device to test itself! Configure the device to test itself! HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 15 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 16
5 What if more defects? What if more defects? vertically horizontally vertically horizontally Configure the device to test itself! Configure the device to test itself! HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 17 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 18 What if more defects? High DefectRates: Our Algorithm Finds probabilities of being defective Eliminates components w/ high prob. P robability- Assignm ent Phase Defect- Location Phase Need more complex testing methods as defect rate increases Key insight: Testers need to return more than binary information Fabric 2 key ideas: Probabilistic Defect Map More powerful test-circuits More than binary info; e.g. approximate defect counts More powerful analysis techniques Defect Map HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 19 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 20
6 High DefectRates: Our Algorithm How It Works Eliminates remaining defects Deterministic; no mistakes Fabric P robability- Assignm ent Phase Probabilistic Defect Map Defect- Location Phase Defect Map See Mahim Mishra's Talk at ITC 03 (Can be found at HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 21 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 22 Reconfigurable Computing Advantages of Reconfigurable General-Purpose int reverse(int x) int k,r=0; for (k=0; k<64; k++) r = x&1; x = x >> 1; r = r << 1; int func(int* a,int *b) int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b Compiler Custom Hardware General-Purpose Custom Hardware Logic Blocks Routing Resources Flexibility of a processor Performance of custom hardware Near You have to Storeand Address the configuration HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 23 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 24
7 a0 a Heart of an FPGA data a0 a1 Universal gate = RAM a1 & a2 data in The costofthefpga: IncreasedArea-DelayProduct control 0 Switch controlled by a 1-bit RAM cell Key Component: Reconfigurable Switch HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 25 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 26 Key Component: Reconfigurable Switch Key Component: Reconfigurable Switch HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 27 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 28
8 Key Component: Reconfigurable Switch Reconfigurable Molecular Switch: Eliminates overhead for reconfigurable computing The Molecular Electronics Advantage: A Reconfigurable Switch Each crosspoint is a reconfigurable switch Can be programmed using the signal wires Eliminates overhead found in CMOS FPGAs! HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 29 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 30 Fabrication Is Different Building a Computing Crystal Devices & wires alone are not useful Key to nanoscale computing is bottom-up assembly Control, configuration decompression, & defect mapping seed HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 31 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 32
9 Building a Computing Crystal With defects Assembly Computing Crystals Implications Devices only at cross-points (only 2 terminal devices?) Only regular structures Defect-tolerance required Functionality must be added post-fabrication Reconfigurable! HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 33 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 34 Abstraction Layers Still OK? Applications Algorithms Programming Languages Breaking Abstractions Applications Algorithms Programming Languages Intermediate Representations ISA Microarchitecture Circuits Fabrication Devices Probably Not Tools Intermediate Representations ISA Microarchitecture Circuits Reconfigurable Fabrication Devices Fabric Tools HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 35 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 36
10 E.g., Asynchronous Design E.g., ISA has to go? data + data valid ack Tolerant of Layout Parametric variation Variable Latency Operations Low-power Natural implementation for dataflow Attacks other problems (e.g., clock skew, distribution, ) Current ISA hides to much Good for Forward compatibility Human oriented assembly Ad hock additions Bad for Exploiting resources Managing new constraints, e.g., power exploiting compiler Verification What can replace ISA? In general, how do we eliminate barriers without increasing complexity? HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 37 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 38 Power Density (W/cm2) Another Consideration: Power Sun s Surface 1000 Rocket Nuclear Nozzle 100 Reactor 8086 Hot Plate P Pentium Power densities too high to keep junctions at low temps Source: Irwin & Borkar, De Intel Power α 1/Parallel PαCV 2 F Fα(V-V th ) 5/4, for CMOS V In relevant range: F α V So,PαCF 3 Also, 1/A α T n, early VLSI theory result (1 n 2) If we fix T, then F -1 α T, F α A -1/n If n=2, P α CA -3/2 If C α A, P α A -1 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 39 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 40
11 Reconfigurable Computing Spanning 10-orders of Magnitude General-Purpose int reverse(int x) int k,r=0; for (k=0; k<64; k++) r = x&1; x = x >> 1; r = r << 1; int func(int* a,int *b) int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b Compiler Custom Hardware General-Purpose Custom Hardware Logic Blocks 1 Program Phoenix Compilers Theory Architecture Routing Resources 10 Billion Gates HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 41 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 42 Bryant s Law Processor verification is always 10 years behind What to do? Don t use processors! 1. Program Circuits From Compilers 2. Split-phase Abstract Machines 3. soft P&R on indiv configs int reverse(int x) int k,r=0; for (k=0; k<64; k++) r = x&1; x = x >> 1; r = r << 1; Certifying Circuits! Computations & local storage Unknown latency ops. 4. Placement on chip HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 43 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 44
12 Conclusions Reconfigurable Computing is inevitable Cost of manufacturing Defect tolerance Fabrication constraints X-point (e.g., Molecular) switches are ideal for reconfigurable device EN: New constraints, but huge potential Billions of devices per cm 2 Ultra-low power Faster design time Easier verification Conclusions - 2 New Abstractions are required Defect tolerance Spatial Computing Asynchronous Circuits Abstraction Requirements: Tool friendly not human friendly Support parallel research activities Promote interdisciplinary research HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 45 HLDVT '03 (11/13/03) 2003 Seth Copen Goldstein 46
2002 Seth Copen Goldstein 1
58%/Yr compound Complexity growth rate 2%/Yr compound Productivity growth rate * @ $ 5K/Staff Yr. (in 997 Dollars) Source: MATECH NanoComputing Architectures Seth Copen Goldstein Carnegie Mellon University
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