Learning about VHDL & FPGA s

Transcription

1 DE NAYER Instituut J. De Nayerlaan 5 B-2860 Sint-Katelijne-Waver Tel. (015) Fax. (015) ppe@denayer.wenk.be ddr@denayer.wenk.be tti@denayer.wenk.be pvp@denayer.wenk.be website: emsys.denayer.wenk.be Learning about VHDL & FPGA s Version 1.0 HOBU-Fonds Project IWT Title : Embedded Systeemontwerp op basis van Soft- en Hardcore FPGA s Projectleader : Ing. Patrick Pelgrims Projectassistants : Ing. Dries Driessens Ing. Tom Tierens Ing. Philip Van Pelt Copyright (c) 2003 by Patrick Pelgrims, Tom Tierens, Dries Driessens and Philip Van Pelt. This material may be distributed only subject to the terms and conditions set forth in the Open Publication License, v1.0 or later (the latest version is presently available at Page 1 of 127

2 I. Introduction Traditionally, digital logic was implemented using the classic TTL-logic, a collection of digital functions (ports, counters,...). Figure 1: TTL NAND port Figure 1 gives an example of a NAND TTL port with the corresponding DIP-package. More complex systems can be designed by combining these basic structures. To illustrate this, an XOR function is implemented using AND, OR and NOT ports. TTL logic contains XOR- functions and the design is therefore only intended as an example. It is also possible to design an XOR by only using 4 NAND gates. A A B Out B Out Figure 2: Possible TTL implementation of XOR port As the complexity of designs grew, these methods became inadequate. The large amount of IC s together with the difficult routing and placement on the PCB made development and testing too complex. The first attempts to overcome these problems were to integrate a basic programmable structure into one Integrated Circuit (IC). This building block could now replace several classic TTLcomponents, thus reducing IC count. A Programmable Array Logic (or PAL) consists of a programmable ROM with added logic capacity (see Figure 3). Page 2 of 127

3 Figure 3: PAL schematic These devices were an enormous success. Instead of having a separate IC for each function, there now was one component that could be programmed to behave as any other TTL module. Figure 4 illustrates the XOR function implemented on a PAL. Figure 4: XOR implementation on PAL Because of the fixed topology, designs were limited to a few gates. Techniques evolved and the next generation of programmable hardware is called FPGA. Page 3 of 127

4 II. FPGA FPGA s (Field Programmable Gate Array) are devices that contain lots of building blocks (ports, logic, ) with a complete interconnection structure (see Figure 5a). By programming these connections, different logical blocks or slices can be linked to obtain the desired circuit. (a) (b) (c) Figure 5: (a) Xilinx FPGA structure (b) Altera FPGA structure (c) Programmable interconnections (Xilinx) (d) I/O block (Altera Stratix) (d) Page 4 of 127

5 Figures 6 and 7 give an example of a logical element (LE) and a Configurable Logic Block (CLB). A LE or CLB consists out of three parts: a Look-Up Table (LUT), a Flip-flop (FF) and a multiplexer (MUX). The LUT is similar to the PAL structure. It is the combinatorial part of the cell and describes the function of that element, just like a truth table that maps the input to the output. Therefore the table can behave as any function: F =f(f 1,F 2,F 3,F 4 ) with F i being the inputs and F the output. If needed, the LUT can also be used as fast RAM. A FF latches the data to be able to work synchronously. Finally the MUX will send the data to the appropriate line where it can be used by the next LE, CLB or block. The MUX maps the outputs of the LUT to the different output lines. A 4-bit signal selects 16 possible LUT outputs. An FPGA uses different kinds of lines to transport signals across the device. Each LE or CLB is connected to its neighbours with direct lines. This assures fast communication to combine several LE s or CLB s together. Longer lines connect clusters of LE s or CLB s, whereas long lines run over the complete FPGA. Together with the programmable interconnections (see Figure 5c) and the programmable I/O blocks, a complete design can be developed using only one programmable digital IC. The two major vendors of programmable logic are Altera and Xilinx. Each uses different approaches and will therefore be discussed next to each other. Logical Element (LE) of an Altera Cyclone Figure 6: LE overview Page 5 of 127

6 Configurable Logic Block (CLB) with 2 slices of a Xilinx Spartan Figure 7: CLB overview The advantages of using these techniques over a classical TTL-based system are speed and adaptability. When an error is made or a system upgrade is ready, reprogramming the device is sufficient to alter the system. Thus, cutting down design time. The automatic syntheses, easy testability and in-system logic analysers shorten this even more. On the other hand, the same device can perform different tasks according to the configuration downloaded into it (this can even be done on board without removing the component). Due to the increased complexity of FPGA s, it is possible to implement more complex and demanding structures and even integrate a complete design on one chip. The difference with e.g. a microprocessor is that the logic can execute in parallel. In a microprocessor all instructions are performed one after the other. The software gives the sequence of instructions that will execute. When comparing to a normal processor, FPGA s can perform better. The parallelism allows for more efficient computation. If the latter can carry out 100 instructions at the same time, the clock can be 100 times slower without losing any execution speed. An FPGA running at 50MHz can therefore be faster than a processor running at 500MHz, depending on the application. All this is possible by the large amount of transistors available in FPGA s. Programming these devices isn t easy. Each Look-Up Table (LUT), I/O block and interconnection needs to be programmed. This is the price you pay for flexibility. Luckily a programming language and tools were developed to make this a less complex task. The hardware isn t programmed bit by bit, but described in a high-level description language. By describing the behaviour, design can be completed in a shorter period and the code will be more readable and portable than a schematic entry. Page 6 of 127

7 III. VHDL language VHDL is an acronym that stands for VHSIC Hardware Description Language. VHSIC is yet another acronym meaning Very High Speed Integrated Circuits. It can be used to describe, simulate, synthesize and document any digital electronic circuit. By downloading a configuration into an FPGA, a physical system is obtained. This system will be a combination of different logical elements (AND-, OR-ports,...) and other digital structures (Memory,...). Because this language is an international standard, it is independent of the FPGA manufacturer. The same code can be compiled for different IC s of different vendors. The final implementations may be different, but the functional properties will be the same for all devices. Notice that VHDL is not a programming language but a descriptive language. You always have to keep the hardware in mind. Think in hardware, not software. There are some alternatives to VHDL, of which VERILOG and ABEL are the most important ones. Building blocks are the basic structures of the VHDL language. The top-level block is composed of different building blocks. Each sub-block can also be composed of other blocks (see Figure 8). Block A Block B Block C Block D Block E Block F Figure 8: VHDL block structure Each block consists of two parts: an entity and an architecture element (see Figure 9). The entity describes the interface to that block and a separate part, the architecture, associated with the entity describes how that block operates. The entity is like a pin description in a data book, specifying the inputs and outputs to the block. The architecture can be compared to a schematic for the block, describing in words (not symbols) what the block does. Page 7 of 127

8 VHDL file Entity declaration Architecture declaration Figure 9: VHDL-file structure This is illustrated in the following example: Figure 10a is the interface of a building block. Only the in-and outputs are given. The block itself is a black box. What it does is described by the architecture. If you want to design a XOR function, the architecture will be: C<=A xor B (cfr. C=A xor B). The VHDL code representing this block is given in figure 10b. A B (a) C Entity entity XORport is port ( A,B: in BIT; C: out BIT end XORport; Architecture architecture dataflow of XORport is C<=A xor B; end dataflow; (b) Figure 10: (a) Interface (b) Architecture structure In the XORport entity declaration, A and B are declared as input bits, whereas C is declared as output bit. The architecture describes what the box will do; in this case the dataflow architecture uses the XORport entity and describes the behaviour of a XOR-port. A signal assignment statement describes how data flows from the signals on the right side of the <= operator to the signal on the left side. Note: the <= symbol was chosen carefully to avoid confusion with the variable assignment operator (usually = ) of typical programming languages. The signal assignment operator in VHDL specifies a relationship between signals, not a transfer of data as in most programming languages. Evaluating the expression is performed by substituting the values of the signals in the expression and computing the result of each operator in the expression. The implementation of this XOR port is indicated in the next figures (see Figures 11 and 12). The first image gives a complete overview of the FPGA, whereas the next ones represent a zoomed in portion of the complete design. The second figure shows clearly the two input pins and the output pin. The logical unit is depicted in the last figure. Figure 13 shows the XORport-entity compiled by the Xilinx tool chain. Compare this to the schematic you would have expected to see. Page 8 of 127

9 Figure 11: XOR implementation on Altera Cyclone (a) (b) (c) Figure 12: XOR implementation on Xilinx Spartan (a) Overview (b) Routing (c) CLB overview Page 9 of 127

10 Figure 13: Generated XOR design by Xilinx When analysing the code in figure 10b, a syntax for writing VHDL code can be derived (see figure 14a and 14b). Entity Architecture entity entity-name is architecture architecture-name of entity-name is port ( variable declarations signal-names : mode signal-type; signal declarations signal-names : mode signal-type; constant declarations function definitions signal-names : mode signal-type component declarations end entity-name; concurrent-statement; concurrent-statement; end architecture-name; (a) (b) Figure 14: (a) Overview of entity (b) Architecture syntax Different signal-types are given in figure 15. Because the bit -types are not always satisfactory, it s best to use the std_logic -types. They can describe the status of a signal/pin more accurately (e.g. low, high, high impedance, don t care, ). Signal-type Signal-mode bit ( 1 or 0 ) in bit_vector (combination of bits) out boolean ( true or false ) buffer integer ( to ) inout real user-defined types (defined by libraries) std_logic std_logic_vector Figure 15: Overview of signal-types and signal-modes Page 10 of 127

11 Signal declarations Signals are the wires of VHDL. They are used to connect different blocks. Syntax: signal signal-names : signal-type Variable declarations Same as signals, but no physical significance. Syntax: variable variable-names : variable-type Constant declarations Fixed numbers can de declared constant to improve readability Syntax: constant constant-names : constant-type := constant-value Function definitions Functions have the same meaning in VHDL as in most programming Component declarations languages. They can be used to define subroutines. Definitions of the components (blocks) you want to use in your design. Figure 16: Overview of architecture declarations There are three ways to write an architecture: dataflow, behavioural and structural. These three will become clear while completing this course. In short, the dataflow structure will assign signals to certain outputs, given the inputs. This is done completely in parallel. Sometimes it is easier to write the code in a behavioural way. This means that different classic statements, like if-then-else, can be used. It will be executed sequential, thus one line after the other. The structural method is used to add the blocks described above to your architecture. A design can combine these different techniques. In this way each part of the code can be written in the most optimal approach. But more about this is explained later. Let s start by actually making our first design. Page 11 of 127

12 IV. First design IMPORTANT: Before powering up your development board or downloading a design, check everything and ask the instructor for confirmation. Make sure you are using the correct wall adaptor and be careful with lingering metal pieces or wires. Design an application to let the GPIO LEDs (general purpose input/output LED) react to the buttons. Figure 17: VHDL block scheme First the general design flow (see Figure 18) is illustrated. A step-by-step tutorial for both programming an Altera and a Xilinx device is worked out below. In the two designs, similar steps can be extracted: Design Synthese Mapping Routing Fitting Generate programming file Page 12 of 127

13 (a) (b) Figure 18: (a) Altera design flow (b) Xilinx design flow Page 13 of 127

14 A) ALTERA (Quartus) 1. Create a new project First close any existing projects (Quartus automatically loads the last project used). File -> New Project Wizard Enter the filename and project name: E.g.: Filename: c:\qdesigns\labovhdl Project name: exercise1 Press Next No need to add extra files to project Press Next Press Next Choose the family and type of FPGA (Stratix: EP1S10F780C6ES, Cyclone: EP1C20F400C7). Press Next Press Finish 2. Make a new VHDL file File -> New Select VHDL-file. File -> Save As (give your file the same name as you will give your entity) E.g.: button_to_led.vhd Now select this new file as the top entity of our design. This will be the entity used to connect to the pins of the FPGA. Select the Files -tab of the Project Navigator (View -> Utility Windows) Right click on the newly added file (Device Design Files) and select Set Compiler Focus To Current Entity. 3. Write an entity/architecture description Now write the VHDL-code in the new file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity button_to_led is port ( sw : IN std_logic_vector (3 downto 0 ledout : OUT std_logic_vector (3 downto 0) end button_to_led; architecture button_to_led_arch of button_to_led is ledout <= sw; end button_to_led_arch; Figure 19: Button_to_led VHDL code Page 14 of 127

15 The first two lines indicate which library to use. Normally the standard logic library (std_logic) is used. It consists of a more complete set of states to correctly represent internal behaviour. From now on, only use these types (std_logic and std_logic_vector). Possible includes are: IEEE.STD_LOGIC_1164.ALL => adding basic std_logic functions IEEE.STD_LOGIC_ARITH.ALL => adding arrhythmic functions IEEE.STD_LOGIC_UNSIGNED.ALL => adding unsigned arrhythmic functions IEEE.STD_LOGIC_SIGNED.ALL => adding signed arrhythmic functions The suffix ALL indicates that all functions of that library are included. The entity consists of 4 inputs (buttons) and 4 outputs (LEDs). A single input for each button can be assigned, but it is easier to define them together (see Figure 19 & 20) as an array of input pins. This will make the design much more readable. Notice the definition of the size of our input vector (n-1 downto 0). This method can be used to access any part of the array. E.g.: sw(2) sw(3 downto 2) entity button_to_led is port ( sw1 : IN std_logic; sw2 : IN std_logic; sw3 : IN std_logic; sw4 : IN std_logic; ledout1 : OUT std_logic; ledout2 : OUT std_logic; ledout3 : OUT std_logic; ledout4 : OUT std_logic end button_to_led; Figure 20: Button_to_led entity code without using vectors The architecture is quite straightforward: send the status of the sw-vector to the ledout-vector. A little more explanation is needed, though. This is the dataflow-structure discussed earlier. Every line written after the -statement executes in parallel. This means that the code written, won t execute one step after the other. All is done simultaneously. The results of the calculations therefore aren t available until the next update cycle is reached. You can look at the code as one big loop, starting with the BEGIN -statement until the END -statement. The signals are never updated inside the loop, only at the end. The next example (see Figure 21) illustrates this. Assume that a is defined as INOUT (multidirectional pin). architecture button_to_led_arch of button_to_led is a <= b; c <= a; end button_to_led_arch; Figure 21: Example of dataflow-structure Page 15 of 127

16 Intuitively, after execution a, b and c should have the same value. Because these processes work in parallel, this is not true. The signal a is only changed at the end of the file. So assume that a=1, b=2 and c=3 before execution. At first, one would expect a to hold the value of b after the first statement. Then the next line would send this value to c. At the end a would equal b and c (a=b=c=2). But is not the case at all. Actually the two statements are executed at the same time. So when c <= a is carried out, the new value of a isn t available yet and therefore the old value is used. The signal a gets the old value of b and the signal c gets the old value of a. After one cycle, the result will be: a=2, b=2 and c=1. When all signals are updated, a new cycle starts. The next time step will result in the following values: a=2, b=2, c=2. 4. Analyse design Before continuing the design, the synthesis tool needs to analyse the code written and checks it for the correct syntax. Processing -> Start -> Start analysis and synthesis If the code has no syntactical errors, everything should work fine. Otherwise some debugging needs to be done (more about that later). 5. Assign pins If the desired circuit is implemented on a physical device, the design must to be mapped on the available programmable component by assigning signals to the pins of the FPGA. The integrated design environment needs to know how to allocate the signals to the available pins. Here you define which pin corresponds with which signal in your design. In appendix A an overview of the pins used in this tutorial can be found. For this design only the Button and the LED pins are of importance. See schematics in appendix E for more details. The easiest way is to use the pin assigner, but it is also possible to adapt the assignment in notepad. Start the pin assigner: Assignments -> Assign pins For each pin select the corresponding number and press the... - button next to the pin name field. Press start and select the pin name you want to assign to this physical pin. Press > and OK E.g.: w5 => sw[0] Press add Repeat this until all pins are assigned. After assigning all pins press OK Press ok IMPORTANT: Before exiting the Settings menu. Press the Device & pin options button. Go to the Unused pins tab and select As inputs, tri-stated. We protect the hardware to define unused pins as input. This way we are sure not to cause short-circuits. Internally a pull-up resistor is foreseen to prevent the pin from oscillating. When you forget to do this, your design won t work. Page 16 of 127

17 6. Synthesis and fitting Processing -> Start Compilation Firstly the tool chain will generate all needed data from your VHDL-files. It will then try to fit this design into the desired device and performs some tests. The result is a bit-file (*.SOF) that can be downloaded to a physical device using a JTAG cable. 7. Programming the device Connect the parallel cable to your parallel port and extend it with the Altera ByteBlaster II cable. This extension can be plugged onto the evaluation board on the JTAG-port (indicated with ByteBlaster). Make sure the red wire is pointing to the Ethernet connector on the Stratix board and not to the serial port. The programmer will send the data through the parallel cable where the ByteBlaster will convert it to JTAG signals. The FPGA or a controller IC will then download the new configuration after reset. Tools -> Programmer Check the Program/Configure -checkbox and press the Program -icon (left-top corner). 8. Testing the design Normally a design is verified by a simulator before testing it in physical hardware. Your design could destroy some hardware on your development board. This simple project normally won t cause any problems. How to simulate a design is explained later in this course. On start-up, all LED s are lit. This is because the buttons are active low (Button pressed = 0 ). Remember this for the next designs. Page 17 of 127

18 B) XILINX (ISE) 1. Create a new project First close any existing projects (ISE automatically loads the last project used). File -> New Project Enter the project name and project location: E.g.: Filename: c:\xdesigns\labovhdl Project name: exercise1 Press Next Choose the family and type of FPGA (Spartan2E: xc2s200e pq208 6, Spartan3: xc3s200 ft256). Choose following settings: Top-level Module Type: HDL Synthesis tool: XST Simulator: other Generated simulation language: VHDL Press Next Press Next Press Finish 2. Make a new VHDL file Right click on device (xc2s200e, xc3s200) -> New Source Select VHDL-Module and enter file name. E.g.: button_to_led.vhd Press Next Press Next Press Finish 3. Write an entity/architecture description Now write the VHDL-code in the new file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity button_to_led is port ( sw : IN std_logic_vector (3 downto 0 ledout : OUT std_logic_vector (3 downto 0) end button_to_led; architecture button_to_led_arch of button_to_led is ledout <= sw; end button_to_led_arch; Figure 22: Button_to_led VHDL code Page 18 of 127

19 The first two lines indicate which library to use. Normally the standard logic library (std_logic) is used. It consists of a more complete set of states to correctly represent internal behaviour. From now on, only use these types (std_logic and std_logic_vector). Possible includes are: IEEE.STD_LOGIC_1164.ALL => adding basic std_logic functions IEEE.STD_LOGIC_ARITH.ALL => adding arrhythmic functions IEEE.STD_LOGIC_UNSIGNED.ALL => adding unsigned arrhythmic functions IEEE.STD_LOGIC_SIGNED.ALL => adding signed arrhythmic functions The suffix ALL indicates that all functions of that library are included. The entity consists of 4 inputs (buttons) and 4 outputs (LEDs). A single input for each button can be assigned, but it is easier to define them together (see Figure 22 & 23) as an array of input pins. This will make the design much more readable. Notice the definition of the size of our input vector (n-1 downto 0). This method can be used to access any part of the array. E.g.: sw(2) sw(3 downto 2) entity button_to_led is port ( sw1 : IN std_logic; sw2 : IN std_logic; sw3 : IN std_logic; sw4 : IN std_logic; ledout1 : OUT std_logic; ledout2 : OUT std_logic; ledout3 : OUT std_logic; ledout4 : OUT std_logic end button_to_led; Figure 23: Button_to_led entity code without using vectors The architecture is quite straightforward: send the status of the sw-vector to the ledout-vector. A little more explanation is needed, though. This is the dataflow-structure discussed earlier. Every line written after the -statement executes in parallel. This means that the code written, won t execute one step after the other. All is done simultaneously. The results of the calculations therefore aren t available until the next update cycle is reached. You can look at the code as one big loop, starting with the BEGIN -statement until the END -statement. The signals are never updated inside the loop, only at the end. The next example (see Figure 24) illustrates this. Assume that a is defined as INOUT (multidirectional pin). architecture button_to_led_arch of button_to_led is a <= b; c <= a; end button_to_led_arch; Figure 24: Example of dataflow-structure Page 19 of 127

20 Intuitively, after execution a, b and c should have the same value. Because these processes work in parallel, this is not true. The signal a is only changed at the end of the file. So assume that a=1, b=2 and c=3 before execution. At first, one would expect a to hold the value of b after the first statement. Then the next line would send this value to c. At the end a would equal b and c (a=b=c=2). But is not the case at all. Actually the two statements are executed at the same time. So when c <= a is carried out, the new value of a isn t available yet and therefore the old value is used. The signal a gets the old value of b and the signal c gets the old value of a. After one cycle, the result will be: a=2, b=2 and c=1. When all signals are updated, a new cycle starts. The next time step will result in the following values: a=2, b=2, c=2. 4. Assign pins If the desired circuit needs to be implemented on a physical device, the design needs to be mapped on the available programmable component by assigning signals to the pins of the FPGA. The integrated design environment needs to know how to allocate the signals to the available pins. Here you define which pin corresponds with which signal in your design. In appendix A an overview of the pins used in this tutorial can be found. For this design only the Button and the LED pins are of importance. See schematics in appendix E for more details. Select the top-entity in the Sources in Project -list. Right click and select New Source. Select User Document and enter the filename (<top-entity>.ucf) For each pin write the following line of code: NET "<pin-name>" LOC = "<pin-location>"; E.g.: NET "button" LOC = "P40"; NET "sw<0>" LOC = "P16"; 5. Synthesis and fitting Firstly the tool chain will generate all needed data from your VHDL-files. It will then try to fit this design into the desired device and performs some tests. The result is a bit-file (*.BIT) that can be downloaded to a physical device using a JTAG cable. Select the top-entity in the Sources in Project -list. Right click on Generate Programming File in the Processes for Source -window and select Run Page 20 of 127

21 6. Programming the device Connect the parallel cable to your parallel port and to the parallel port on the evaluation board. The programmer will send the date through the parallel cable to the evaluation board where it will be converted to JTAG signals. The FPGA or a controller IC will then download the new configuration on reset. Open impact program. File -> New Select Configure devices. Press Next Select Boundary-scan Mode. Press Next Select Automatically connect. Make sure the parallel cable is connected correctly, SW1 is set to JTAG and the power of your development board is switched on. Press Finish Select the download file (<top-entity>.bit) Press Open Program by right clicking on the device icon and select Program. 7. Testing the design Normally a design is verified by a simulator before testing it in physical hardware. Your design could destroy some hardware on your development board. This simple project normally won t cause any problems. How to simulate a design is explained later in this course. On start-up, all LED s are lit. This is because the buttons are active low (Button pressed = 0 ). Remember this for the next designs. Page 21 of 127

22 V. Exercises All schematics and code can be found in appendix D. For more information consult these files. A) Implementing a 4-bit to 7-segment decoder Next design will be a little more complicated. Decode the input switches and visualise the states on the 7-segment displays. So when the binary code 5 (1001) is applied to the switches, the number 5 will show on the display. Four inputs and seven outputs are necessary for this design. The architecture will be a bit more difficult. For each output pin, we need a combination of the input pins to decide if that element should be lit or not. Figure 25 gives the layout of the 7-segement displays. Figure 25: 7-segment display This problem can be solved using Karnaugh-cards. The result will be like: A <= { [ b(0) and b(2) ] or [ b(2) and b(1) and b(0)] }; Remember that the buttons are inverted (active low). Assign the correct pins and test the application on the board. Board schematics can be found in appendix E. Page 22 of 127

23 B) Adapting the 7-segment decoder The implementation of the previous 7-segment decoder was a lot of work. Luckily there exist some techniques that can speed up the design of different components. In the ning of the course the three methods to write an architecture in VHDL are explained. So far only the dataflow approach was used. Using the behavioural architecture can improve things (see figure 26). The input bits aren t inverted because this block of code is used later on in other designs. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decode7segment is port ( code : IN std_logic_vector (3 downto 0 seg7 : OUT std_logic_vector (6 downto 0) end decode7segment; architecture dec7seg_arch of decode7segment is process(code) case code is when "0000" => seg7(6 downto 0) <= " "; when "0001" => seg7(6 downto 0) <= " ";... when others => seg7(6 downto 0) <= " "; end case; end process; end dec7seg_arch; Figure 26: 7-segment decoder using behavioural architecture All code, written in the behavioural way must be included in the process tags. Next to this tag, the process s starting condition is defined. In this case this block of code should be executed each time the code parameter changes ( process(code) ). Within this block, different sequential lines of code can be written. For the 7-segment decoder a case is used. The parameter code is evaluated. If it equals 0000 set seg7 to " ". If it equals 0001 to " ". Board schematics can be found in appendix E. Page 23 of 127

24 The more general behavioural processes are summarised bellow. process(signal-names) -- sequential code: e.g.: case (signal-name) is when condition => action1;... when others => action2; end case; if (condition) then action1; elsif (condition) then action2;... else action3; end process; for variable/signal-name in start-value to stop-value loop action; end loop; Figure 27: Overview behavioural architecture Page 24 of 127

25 C) Implementing a 4bit counter In the next case, a counter will be implemented. To visualize the values of the counter, the 7-segment decoder designed above can be used. Try to make a counter that counts from 0 to F using behavioural techniques. The counter should be synchronized (changes only occur at clock transition) and react to the rising edge of the clock. When a button is pressed, the counter is incremented on each clock cycle. Clock Count COUNTER 4-bit Output process(clk) if (clk'event and clk='1') then action; end process; (b) (a) Figure 28: (a) counter schematic (b) rising edge detection Notice that after the if -statement, no more else or elsif -statements are possible. It looks strange but when you keep the hardware in mind it s obvious. A rising edge can be detected but what is a not rising edge? (A falling edge?, No edge?,...) Hint: define an internal signal that represents the state of the counter. The counter and the 7-segment decoder are two VHDL blocks (and files) that need to be put together to visualise the counter. This will be done using the third and last method that can be used to describe hardware in VHDL: the structural method. This powerful technique allows programmers to combine different blocks and build a design from pre-defined structures. Make a new VHDL-file that will contain the actual top-entity for our counter. The design should look like figure 29. Clock 7-segment Out 7 --component declarations component entity-name port (signal-names : mode signal-type end component; --signals to connect blocks signal-names : mode signal-type; (a) component-name : component port map (signal-mapping (b) Figure 29: (a) block schematic of counter_main (b) Overview structural architecture Page 25 of 127

26 Figure 29b gives an overview of the structural architecture. Use this to make the counter work. Signal mapping is done by assigning a signal or value to each in- and output pin of the component. E.g.: clk => MyClockSignal, Enable => 1 By assigning the same signal to different pins, a connection is made between these pins. This is the equivalent of wiring different hardware components together. Try to check the syntax of the design, synthesise and implement this new exercise on the design board. Don t forget to make it your new top-entity. Why does the display only show the number 8? Page 26 of 127

27 D) Working with clock-dividers To overcome the problems detected in the previous exercise, downscaling of the clock is needed. Try to write an entity that is able to achieve this. Two inputs, the clock and the scale factor, and 1 output, the scaled-down clock are needed. It s important that the output is synchronous with the input and that the output is a clock-signal, not a pulse-signal. Remember that the onboard clock runs at 50MHz. Try to implement the previous counter, but this time with a scaled-down clock. This should solve the problem encountered in the last exercise. The schematic should look like this: Clock (50MHz) Scale factor Clock divider Clock (scaled) Enable ( 1 ) Counter 4-bit code Figure 30: Schematic of scaled counter 4 7-segment decoder 7 Display Page 27 of 127

28 VI. Simulating design in ModelSim To analyse the VHDL design, a program called ModelSim is used. This program can simulate complete designs or parts of them. Before programming an FPGA, always simulate everything so you know what can be expected during operation. It is possible to damage the hardware when downloading incorrect designs. 1. Opening New Project File -> New -> Project Choose a project name and location. Press OK Press Add existing design Add all the VHDL-files. 2. Making a Test Bench To be able to test the design, a test bench must be written. This file is a VHDL file that describes and defines in- and outputs for simulation (see Figure 31). This will be the current top-level entity. The Unit Under Test (UUT) is the entity to be tested. By selecting different entities you can simulate different parts of your design. The test bench will be your new top-level entity for the simulator. All other files need to be connected to this file as if they are a part of this entity. An example of a test bench is given in Figure 32. Adapt this file so it will match your design. Figure 31: Test bench Page 28 of 127

29 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity tstbench is outp : OUT std_logic_vector (6 downto 0) end tstbench; architecture test of tstbench is component declarations => adding your design to the test bench -- component counter_main is port (clock : IN std_logic; ledout : OUT std_logic_vector (6 downto 0) end component; signal declarations -- signal clk : std_logic := '0'; -- generate clocks process(clk) clk <= not clk after 20 ns; -- 50MHz end process; hook up components => connect your design to the correct signals -- u1: counter_main port map (clock => clk, ledout => outp end test; Figure 32: Test Bench example The after -command can only be used in simulation. It can t be implemented in hardware. By inverting the clock signal every 20ns we make a 50MHz clock. Some programs are able to generate a test bench. But as there is no common graphical user interface for generated test benches, it s better to learn to write one by hand. Signals can be initialised to a certain value by using the := operator. This only works in simulation. An FPGA can t automatically preload values to its signals. Page 29 of 127

30 3. Compiling files Compile -> Compile All Errors can be seen by double clicking on the red error line ( Compile of... failed with... errors ). If an error occurs in a certain file (probably the test bench), first try the following: Right click on the file->properties-> VHDL -tab-> Use 1993 Language Syntax must be checked 4. Simulate Simulate->Simulate Select the top-entity file (the test bench). Press OK Right click on the test bench-file and select Add->Add to Wave A new window will open with all the signals from the test bench. Press Run for each time step Analyse the behaviour of the entity by looking at the waveforms. 5. Alternatives A Logic State Analyser (LSA) can be used to look to the FPGA pins or even at all the signals inside a design. Those systems are really expensive. Some vendors provide an on-chip analyser (Altera s Signal Tap and Xilinx ILA). Unfortunately these are not included in the web-pack version of Quartus. Page 30 of 127

31 VII. Exercises continued A) Advanced counter Expand the counter with an asynchronous reset and a start/stop button (start counter when pressed, stop counter when pressed again). To get started, an example of a reset is given. process(clk, reset) if (reset = '0') then reset code; elsif (clk'event and clk='1') then synchronous code; end process; process(clk) if (clk'event and clk='1') then if (reset = '0') then reset code; synchronous code; end process; (a) (b) Figure 33: Example of an asynchronous (a) and synchronous (b) reset Page 31 of 127

32 B) Exotic counter Expand the basic counter to output following sequence. Sequence: 0 1 A 5 F E 3 C 9 8 B D Use a Finite State Machine (FSM) to achieve this (see appendix C). An FSM can easily be implemented in VHDL using the case -statements in combination with an internal state -signal. Ex.: type states is (s0, s1, s2, signal state : states; case state is when s0 => output <= "0010"; state<=s1; when s1 => output <= "0001"; state<=s2; when others => output <= "1001"; state<=s0; end case; Figure 34: Example VHDL FSM Page 32 of 127

33 C) Dual-display counter Expand the basic counter so it can use 2 displays. The range is from 00 to FF. When using the Xilinx Spartan development board, multiplexing is needed. In turn apply the data for the first and second display while changing the select signals (see Figure 35). When the transistor a1 is high, the data will be sent to display one. Other displays can be selected in a similar way. Figure 35: Multiplexed LEDs Page 33 of 127

34 VIII. Final projects A) UART: Universal Asynchronous Receiver and Transmitter The purpose of this case is to design a complete sender and receiver module that uses the UART-serial connection. Work together in groups and divide the work - Agree on interfaces and topology - Design individual blocks - Simulate and test each block and the complete design - Combine blocks - Send and receive data with other teams using a general-purpose serial cable. Following top-level designs can be used to design the transmitter/receiver and the UART block. These designs are only intended as guidelines. Other implementations can be used also. When the enable signal is high the counter is active and increments it s value. This value is displayed by the first 7-segment display and transmitted by the UART on the send command. See remarks for more details. Enable Clock Counter 4 7Segment1 (TX data) Send data UART 4 7Segment2 (RX data) TX RX Serial port Figure 36: Block scheme UART sender-receiver Page 34 of 127

35 Data In 4 Buffer 4 Parity check Send data CS Write Control (state node) CS CS 1 0 Muliplexer TX Busy Clock Clock divider (a) Buffer Data Out 4 RX Buffer 4 Parity check parity CS CS CS Clock Clock divider CLK Read Control Error (b) Figure 37: Schematics UART (a) write port (b) read port Read ready Page 35 of 127

36 Remarks: - All blocks should be synchronous. - A multiplexer can be used to easily send serial data. - Send the serial data at 24.4KHz (=50MHz/2048). If everybody uses the same transmission speed, you can connect to each other later on. - The parity bit is defined as follows: when the amount of 1 -bits in the data is odd then the parity bit is set, otherwise it is cleared. - Start bit= 0, Stop bit= 1, transmit data with LSB first. - Try to sample in the middle of the waveform when the RX signal is stable, not at the edges. Use sampling clock that is 8 or 16 times higher than the UART clock. - The output signals (Busy, Error, Read ready) can be connected to LEDs to view if everything works properly. - For testing, connect pin 2 (TX) and 3 (RX) of the serial connector with a wire. This creates a loop back to easily test your system. - Board schematics can be found in appendix E. Idle Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Idle Figure 38: Timing RX en TX Page 36 of 127

37 B) LCD controller Another possibility is to make an LCD controller. Try to adapt the previous counters so they are able to output to the LCD display. As the LCD module is only available for the Altera development board, this project can t be made on a Xilinx board. Follow the same procedure as in the previous project. Clock PLL/ DLL CLK Start/Stop Reset Counter Data Character 4 10 control Reset Data Enable Figure 39: Block scheme LCD controller LCD control LCD 10 Clock Counter Counter msec 4 Carry Sec 4 Counter Carry Figure 40: Counter Character control: This block generates the commands that need to be sent to the display. On reset, an initialisation is performed. Afterwards it sequentially writes all the characters to be displayed, returns to the starting position and repeats this loop. LCD control: Here the timing for the LCD takes place. For each command, a specific timing is required (See figure 44). This block takes as input the command coming from the previous block and makes sure it is delivered to the display in the correct way. Min 4 Page 37 of 127

38 Pin number Symbol Level I/O Function 1 Vss - - Power supply (GND) 2 Vcc - - Power supply (+5V) 3 Vee - - Contrast adjust 4 RS 0/1 I 5 R/W 0/1 I 0 = Instruction input 1 = Data input 0 = Write to LCD module 1 = Read from LCD module 6 E 1, 1->0 I Enable signal 7 DB0 0/1 I/O Data bus line 0 (LSB) 8 DB1 0/1 I/O Data bus line 1 9 DB2 0/1 I/O Data bus line 2 10 DB3 0/1 I/O Data bus line 3 11 DB4 0/1 I/O Data bus line 4 12 DB5 0/1 I/O Data bus line 5 13 DB6 0/1 I/O Data bus line 6 14 DB7 0/1 I/O Data bus line 7 (MSB) Figure 41: LCD pin configuration Instruction Code (RS R/W DB7->DB0) Description Execution time Clear display Clears display and returns cursor to 1.64mS the home position (address 0). Cursor home * Returns cursor to home position 1.64mS (address 0). Also returns display being shifted to the original position. DDRAM contents remains unchanged. Entry mode set I/D S Sets cursor move direction (I/D), 40uS specifies to shift the display (S). These operations are performed during data read/write. Display D C B Sets On/Off of all display (D), cursor 40uS control On/Off and blink of cursor position character (B). Cursor control S/C R/L * * Sets cursor-move or display-shift 40uS (S/C), shift direction (R/L). DDRAM contents remains unchanged. Function set DL N F * * Sets interface data length (DL), 40uS number of display line (N) and character font (F). Write data 1 0 DATA (see figure 45) Writes data to CGRAM or DDRAM. 40uS Figure 42: LCD commands Page 38 of 127

39 Bit name Setting / Status I/D 0 = Decrement cursor position 1 = Increment cursor position S 0 = No display shift 1 = Display shift D 0 = Display off 1 = Display on C 0 = Cursor off 1 = Cursor on B 0 = Cursor blink off 1 = Cursor blink on S/C 0 = Move cursor 1 = Shift display R/L 0 = Shift left 1 = Shift right DL 0 = 4-bit interface 1 = 8-bit interface N 0 = 1/8 or 1/11 Duty (1 line) 1 = 1/16 Duty (2 lines) F 0 = 5x7 dots 1 = 5x10 dots Figure 43: Bit names Figure 44: LCD timing Figure 45: Character set Page 39 of 127

40 Remarks: - All blocks should be synchronous. - Try to use the build-in PLL/DLL to divide your clock signal. Quartus and ISE have a wizard to make your own PLLs/DLLs. Quartus: Mega wizard Plug-in ISE: Create new source -> IP (CoreGen) - The LCD is very time critical. If you write the data too fast, errors will occur. The display controller needs time to be able to process the commands. - Not all commands take the same time to execute. - Try to make a counter for each character to be displayed. This means that you need 2 timers for the seconds (34sec=>3 & 4). - The other displays (seven segment, LEDs,..) can be used to output some debug data or help you visualise the process. - Board schematics can be found in appendix E. - Start with something simple and try to expand your project. e.g.: First try to display one character before moving on. Page 40 of 127

41 C) Audio filter with memory control The purpose of this project is to write an audio file into the FPGA s SRAM. This file will then be looped, passed through a filter and sent to the audio lineout interface. As the audio module is only available for the Altera development board, this project can t be made as easy on the Xilinx board. The latter hasn t got the correct connectors for the LCD module. Follow the same procedures as the previous projects. The grey coloured blocks in figure 46 are available together with a software program to load an audio file to the hardware module. Clock Clock Input control UART RX Data 8 TX Ready (not used) Clock Memory 8 R/W RX control Data 18 Address Memory See figure Data 8 Rate Filter(s) CLK Data Figure 46: Block scheme audio filter 8 CLK PWM Audio Memory control: This block takes care of the communications with the SRAM. It consists of a read and a write procedure. Each cycle consists of three synchronous commands as depicted in Figure 47. First initialise SDRAM, afterwards read or write the date and finally restore the bus. Filter(s): The audio coming from the memory is filtered. The coefficients of four FIR-filters, together covering the complete spectrum, are given later in this text (figure 48). PWM: In order to convert the digital data back to an analogue voltage, Pulse Width Modulation is used. Use 8-bit data words. Read Write Figure 47: Read and write SRAM timing Page 41 of 127

42 Figure 48: Finite Impulse Response filter FIR1 ( Hz) 8 VARIABLE GAIN FIR2 ( Hz) VARIABLE GAIN FIR3 (630Hz-3.5kHz) VARIABLE GAIN FIR4 (3.5kHz-...) VARIABLE GAIN Figure 49: Possible filter implementation (4 bands Equaliser) Page 42 of 127

43 FIR1 (LP 110 Hz) FIR2 (BP Hz) FIR3 (BP 630 Hz khz) FIR4 (HP 3.5 khz) B B B B B B B B B B B B B B B B Figure 50: Possible filter coefficients (FIR Hamming window) Figure 51: Visual Basic interface The Visual Basic program reads an audio file with consists of 8-bit words, sampled at 12.5kHz. It will send this data to its serial port. Remarks: - All blocks should be synchronous. - To be able to use the audio lineout, an extension board (Lancelot VGA) is available. Attach this board correctly to the development kit before powering up. Therefore use connectors J11, J12 and J13. - Make an interface so you can view and change some settings (e.g. gain). - The values given in figure 50 are generated by MatLab. They need to be adapted before they can be used in VHDL. - Two SRAM s are used in parallel to have a 24-bit wide memory. Some signals are shared, other signals are IC specific. See pin configuration in appendix A for more details. - Board schematics can be found in appendix E. Page 43 of 127

44 IX. Appendix A (Pins) A) Altera Stratix (NIOS development board) (a) (b) Figure 52: Altera development board Page 44 of 127

45 Switches 7-segment 1 LCD SW0 W5 A A18 E K3 SW1 W6 B C18 RS M7 SW2 AB2 C D18 R/W M8 SW3 AB1 D A19 D0 H3 E B19 D1 L7 LEDs F C19 D2 L8 D0 H27 G E19 D3 H2 D1 H28 DP D19 D4 H1 D2 L23 D5 L6 D3 L24 7-segment 2 D6 L5 D4 J25 A B18 D7 J4 D5 J26 B B20 D6 L20 C A20 Clock K17 D7 L19 D C20 E A21 CPU reset AC9 UART F B21 TDX U21 G C21 Audio Left M8 RDX Y28 DP D21 Right H3 SRAM CS B24 D0 B8 D1 A8 WE C24 D2 A9 D3 C9 OE B26 D4 E10 D5 A10 BHE0 F17 D6 C10 D7 B10 BHE1 L17 D8 A11 D9 C11 BLE0 M18 D10 D11 D11 B11 BLE1 J18 D12 D10 D13 G10 D14 F10 D15 H11 A0 B3 D16 G11 D17 F8 A1 B5 D18 J9 D19 J13 A2 B4 D20 L13 D21 M11 A3 C4 D22 L11 D23 G7 A4 A5 A5 C5 A6 D5 A7 E6 A8 A6 A9 B7 A10 D6 A11 A7 A12 D7 A13 C6 A14 C7 A15 B6 A16 D8 A17 C8 Figure 53: Pin configuration Stratix Page 45 of 127

46 B) Xilinx Spartan2E (Digilent development board) (a) (b) (c) (d) Figure 54: Digilent FPGA and I/O board IMPORTANT: Connect the I/O board to connectors J6(E) and J7(F) otherwise the pins bellow aren t correct. Buttons 7-segment Switches BTN1 P40 A P17 SW1 P16 BTN2 P41 B P20 SW2 P18 BTN3 P42 C P22 SW3 P21 BTN4 P43 D P24 SW4 P23 BTN5 P64 E P29 SW5 P27 F P31 SW6 P30 LEDs G P34 SW7 P33 D1 P44 DP P36 SW8 P35 D2 P46 Select1 P45 D3 P48 Select2 P47 UART D4 P55 Select3 P49 TX P201 D5 P57 Select4 P56 RX P202 D6 P59 D7 P61 Clock P80 D8 P63 Figure 55: Pin configuration Spartan Page 46 of 127

47 C) Xilinx Spartan3 (Digilent development board) (a) Figure 54: Digilent FPGA board (b) Buttons 7-segment Switches BTN0 M13 A E14 SW0 F12 BTN1 M14 B G13 SW1 G12 BTN2 L13 C N15 SW2 H14 BTN3 L14 D P15 SW3 H13 E R16 SW4 J14 LEDs F F13 SW5 J13 LD0 K12 G N16 SW6 K14 LD1 P14 DP P16 SW7 K13 LD2 L12 AN0 D14 LD3 N14 AN1 G14 UART LD4 P13 AN2 F14 TX R13 LD5 N12 AN3 E13 RX T13 LD6 P12 LD7 P11 Clock T9 Figure 55: Pin configuration Spartan Page 47 of 127