ELE306 FALL2003 LAB3

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1 ELE306 FALL2003 LAB3 VGA and PS/2 --- reusing existing VHDL modules In this lab, the use of existing VHDL modules will be used to create designs. These modules will help interface the PS/2 keyboard and the VGA (640x480) monitor. There are four external VHDL modules needed for this lab: three of them (keyboard.vhd, vga_sync.vhd, and square.vhd) will be available in ftp://ftp.ele.uri.edu/outgoing/jcl/306; while the fourth one (sevenseg.vhd) is from lab 2. Exercise (Creating a design with the keyboard as an input) Create a project called lab3a. Insert the provided two files into the project sevenseg.vhd and keyboard.vhd. A good approach to insert these files is to save the two files to the directory and then through Quartus add the two files to the project Project->Add/Remove Files in Project. Create a VHDL file called lab3 (be sure to set it as the top-level entity by Project- >Set Compiler Focus to Current Entity). Type the contents of the following table into this file. LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.all; ENTITY lab3 IS PORT( clk25mhz : IN std_logic; reset : IN std_logic; keyboard_clk, keyboard_data : IN std_logic; display1, display2 : OUT std_logic_vector(6 DOWNTO 0) END lab3; ARCHITECTURE mylab3 OF lab3 IS COMPONENT keyboard PORT( keyboard_clk, keyboard_data, clock_25mhz, reset, read : IN STD_LOGIC; scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 scan_ready : OUT STD_LOGIC COMPONENT sevenseg PORT( ain : IN std_logic_vector(3 DOWNTO 0 aout : OUT std_logic_vector( 6 DOWNTO 0) --define signals

2 SIGNAL sscan_code : std_logic_vector( 7 DOWNTO 0 --keyboard SIGNAL sscan_ready : std_logic; --keyboard BEGIN keyboardout: keyboard PORT MAP( keyboard_clk => keyboard_clk, keyboard_data => keyboard_data, clock_25mhz => clk25mhz, read => '0', reset => NOT reset, scan_code => sscan_code, scan_ready => sscan_ready sevenseg1: sevenseg PORT MAP( ain => sscan_code(7 DOWNTO 4), aout => display1 sevenseg2: sevenseg PORT MAP( ain => sscan_code(3 DOWNTO 0), aout => display2 END mylab3; For now, we will not delve into the workings of the PS/2 standard, but data is serially transmitted over the keyboard_data line and the keyboard module recombines the 11bit packets into an 8bit character that is held in scan_code. When the process of receiving the 11bits is done, the scan_ready line will be set to signify a character is ready to be read. The packet consists of a start bit 0, the 8 character bits, an odd parity bit, and a stop bit 1. To send a character with a character value of 31 (or in binary), the following series of bits would be sent Since we cannot display the value of the 8 bits on one seven-segment display, two displays are used. Assign the pins given in the following table. Pin Name clk25mhz display1[0] display1[1] display1[2] display1[3] display1[4] display1[5] display1[6] display2[0] display2[1] display2[2] display2[3] display2[4] display2[5] display2[6] keyboard_clk keyboard_data reset Pin Location Pin_91 Pin_13 Pin_12 Pin_11 Pin_9 Pin_8 Pin_7 Pin_6 Pin_24 Pin_23 Pin_21 Pin_20 Pin_19 Pin_18 Pin_17 Pin_30 Pin_31 Pin_41 Do a functional simulation, timing simulation, and then demonstrate the working results to the TA. Exercise (Using a VGA monitor)

3 Copy the current project directory and name it lab3b. This will avoid the need of retyping settings or any source files. Add square.vhd and vga_sync.vhd to the project. It would be a good idea to save the two files to the project directory and then add the files to the project as was done in the previous exercise. Modify the file lab3.vhd to correspond to what is given in the table below. LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.all; ENTITY lab3 IS PORT( clk25mhz : IN std_logic; reset : IN std_logic; red_out : OUT std_logic; green_out : OUT std_logic; blue_out : OUT std_logic; horiz_sync_out : OUT std_logic; vert_sync_out : OUT std_logic; keyboard_clk, keyboard_data : IN std_logic; display1, display2 : OUT std_logic_vector(6 DOWNTO 0) END lab3; ARCHITECTURE mylab3 OF lab3 IS --Define the components COMPONENT square PORT( move_clk : IN std_logic; reset : IN std_logic; pixel_col : IN std_logic_vector( 9 DOWNTO 0 pixel_row : IN std_logic_vector( 9 DOWNTO 0 red : OUT std_logic; green : OUT std_logic; blue : OUT std_logic COMPONENT VGA_SYNC PORT(clock_25Mhz, red, green, blue : IN STD_LOGIC; red_out, green_out, blue_out, horiz_sync_out, vert_sync_out : OUT STD_LOGIC; pixel_row, pixel_column : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) COMPONENT keyboard PORT( keyboard_clk, keyboard_data, clock_25mhz, reset, read : IN STD_LOGIC; scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 scan_ready : OUT STD_LOGIC

4 COMPONENT sevenseg PORT( ain : IN std_logic_vector(3 DOWNTO 0 aout : OUT std_logic_vector( 6 DOWNTO 0) --define signals SIGNAL sred, sgreen, sblue : std_logic; --vga display SIGNAL spixel_row, spixel_column : std_logic_vector(9 DOWNTO 0 --vga display SIGNAL sclk_cnt : std_logic_vector( 19 DOWNTO 0 --step down counter for move_clk SIGNAL sscan_code : std_logic_vector( 7 DOWNTO 0 --keyboard SIGNAL sscan_ready : std_logic; --keyboard BEGIN vgaout : VGA_SYNC PORT MAP( clock_25mhz => clk25mhz, red => sred, green => sgreen, blue => sblue, red_out => red_out, green_out => green_out, blue_out => blue_out, horiz_sync_out => horiz_sync_out, vert_sync_out => vert_sync_out, pixel_row => spixel_row, pixel_column => spixel_column squareout: square PORT MAP( move_clk => sclk_cnt(19), reset => reset, pixel_col => spixel_column, pixel_row => spixel_row, red => sred, green => sgreen, blue => sblue keyboardout: keyboard PORT MAP( keyboard_clk => keyboard_clk, keyboard_data => keyboard_data, clock_25mhz => clk25mhz, read => '0', reset => reset, scan_code => sscan_code, scan_ready => sscan_ready sevenseg1: sevenseg PORT MAP( ain => sscan_code(7 DOWNTO 4), aout => display1 sevenseg2: sevenseg PORT MAP( ain => sscan_code(3 DOWNTO 0), aout => display2 PROCESS( clk25mhz, reset ) begin IF(reset='0') THEN sclk_cnt <= " "; ELSIF( clk25mhz'event AND clk25mhz = '1') THEN sclk_cnt <= sclk_cnt + 1; END IF; END PROCESS; END mylab3; A description of how the vga_sync.vhd file and VGA monitor functions can be found in Chapter 9 of the book Rapid Prototyping of Digital Systems. The square.vhd file draws a square on the screen that moves towards the bottom right. Assign the following pins. Pin Name blue_out clk25mhz display1[0] display1[1] display1[2] display1[3] display1[4] display1[5] display1[6] Pin Location Pin_238 Pin_91 Pin_13 Pin_12 Pin_11 Pin_9 Pin_8 Pin_7 Pin_6

5 display2[0] display2[1] display2[2] display2[3] display2[4] display2[5] display2[6] green_out horiz_sync_out keyboard_clk keyboard_data red_out reset vert_sync_out Pin_24 Pin_23 Pin_21 Pin_20 Pin_19 Pin_18 Pin_17 Pin_237 Pin_240 Pin_30 Pin_31 Pin_236 Pin_41 Pin_239 Do a functional simulation, timing simulation, and then demonstrate the working results to the TA. Note that the sequence of events for displaying the entire screen is too large for the simulation screen. Therefore, you may simulate for only one horizontal scan, as shown in the attached example waveforms. Assignment Modify the exercises to produce a bouncing square that rebounds off of the boundaries of the screen. Utilize the keyboard to create an edit mode which is entered by hitting the Enter key. Once in the edit mode, you should be able to use the arrow keys to move the cursor around the screen. When the Enter key is hit again, the edit mode is exited and the ball continues to bounce from the new position. Report: Function and timing simulations from lab3a and lab3b exercises. For the assignment: 1. An overview of your design using diagram, flowchart, or whatever means necessary to express your thought process. 2. The VHDL codes (no need to include the reused VHDL modules). 3. Function and timing simulation waveforms. 4. Lesson learned.

6 Date: October 6, 2003 db\lab3-sim.vwf Project: lab3 0 ps 3.2 us 5.25 us 25 ns clk25mhz keyboard_clk keyboard_data reset keyboard:keyboardout SHIFTIN display1 display2 keyboard:keyboardout filter Page 1 of 2

7 Date: October 6, 2003 db\lab3-sim.vwf Project: lab3 5.3 us 12.0 us Page 2 of 2

8 Date: October 6, 2003 db\lab3-sim.vwf Project: lab3 0 ps 12.8 us 25.6 us 38.4 us 45.0 us 25 ns clk25mhz reset horiz_sync_out vert_sync_out red_out green_out blue_out display1 display Page 1 of 1

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