Digital VLSI Design I

Transcription

1 igital VLSI esign I MITRM XMITIO Problems Points Total 6 Was the exam fair? yes no

2 Problem 4 points Mark your yes, no, or not applicable answers for all the given choices!.. onsidering unit size tranzistors on the same chip, which of the following driving circuits will charge a large capacitive load, LO, within the shortest time: x two p-channel transistors in series, x two p-channel transistors in parallel, x two n-channel transistors in series, x two n-channel transistors in parallel, _ x two transmission-gates in cascade,. Latch-up is a name for the effect that: x is used in MOS technology to separate p-channels from n-channels, x deteriorates transmission of signals when more than four transmission-gates are coupled in series, x can cause charge redistrubution inside n-type MOS logic blocks, x can cause system failures in MOS VLSI circuits.. When standard-cell libraries are designed, the folowing features are standardized: x the power line separations, x the power line directions, x the power consumption, x the number of signal terminals x the cell width,

3 .4 n uler trail in a graph G(V,) is a walk that: x passes through all the vertices of the set V and all the edges of the set, x passes through all the vertices of the set V exactly once, x passes through all the edges of the set exactly once, x passes through all the edges of the set exactly once and returns to the starting vertex, x passes through all the vertices of the set V and all the edges of the set exactly once,. The following technologies and design styles have the routing channels of variable width: x standard cell design, x gate arrays, x sea of gates, x field programmable gate arrays, x full custom design..6 Gate electrical effort delay h G of a logic gate G is dependent on: x gate s own output parasitic capacitance, _x parasitic input capacitance of G, _x the capacitance L loading the output of G, x parasitic input capacitance of the reference inverter.. Path delay of a cascade of gates is equal to : x Σ f j, the sum of gate effort delays of the gates in the path, x Π f j, the product of gate effort delays of the gates in the path x Σ p j, the sum of gate parasitic delays of the gates in the path, _x Σ f j + Σ p j, the sum of the sums of gate effort delays and gate parasitic delays of the gates in the path.

4 4 Problem 0 points Figures.(a) and.(c) show a sticks representation of a MOS cell, while Figure.(b) shows the legend which explains how conducting layers are represented by stick patterns/colors. V V Legend p-diff n-diff poly metal metal cont.cut (b) G G (a) (c) V G Fig.. MOS cell. (a) Sticks representation. (b) Legend for patterns/colors in (a). (c)sticks representation when M layer is removed. (d)transistor level circuit model of the cell in (a). Prepare the following informattion for the layout shown in Figure.(a). (d). xtract the Transistor level circuit model of the cell in (a), and draw it in the space reserved for Figure.(c).. Write a one sentence behavioral description of the cell. Layout shown in Figures.(a) and.(b) implements a level-controled, high-active, inverting -type flip-flop.

5 Problem points Given is the logic function of five variables, Z = ( +) (+). esign a static MOS gate that implements the function Z using one single unbroken row of p- diffusion for all p-channel transistors, and one single unbroken row of n-diffusion for all n-channel transistors. In your design show the following steps.. Prepare the electrical model of the gate and show it in the space reserved for Figure... onstruct the gate graph G G of the electrical model and show its graphical representation in the space reserved for Figure.. In the graphical representation of G G : - circuit nodes are represented by vertexes, and transistors are represented by edges, - the graphical representation of the p-block subgraph is drawn in red colour, and the graphical representation of the n-block subgraph is drawn in black color, - edges are labelled by the signals on the corresponding transistor gates. I I V V I I Z Z = ( +) (+) I I I 4 I 4 V SS V SS Figure. lectrical model of the gate.. Graphical representation of the graph G G of the electrical model of Figure..

6 6 4.. Prepare the lists of all of uler trails: in the n-block subgraph of G G, in the p-block subgraph of G G, and of all couples of uler trails which have the same ordering of line labels in the n-block and p-block subgraphs. n-block p-block common to p and n blocks.4. In the space reserved for Figure., prepare the sticks representation of the single-metal-layer layout of the designed gate with horizontal unbroken diffusion rows, and vertical signal lines, using: - yellow lines for p-diffusion, - green lines for n-diffusion, - red lines for polysilicon, - blue lines for metal. Z Y V Legend p-dif n-dif poly metal cont.cut V SS Figure. Sticks representation of the layout of the designed gate.