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2 Short answers 2 points each For the following four circuits, identify the value of the output from the following choices. Consider the D-latch a rising edge triggered latch. a.) b.) c.) (stored value of ) d.) (inverse of stored value of ) e.) undefined The expression A B C + A B C + A B is not in proper Sum-of-Products format. What boolean algebra operation would you need to apply to correct this? a.) It's not a problem; illegal term drops out b.) Distributive Law c.) Use "F-O-I-L" d.) Take the inverse of the inverse e.) DeMorgan's Theorem f.) It can't be fixed 6. True or False: There exists exactly one pattern of rectangles for every pattern of 's and 's in a Karnaugh map. 7. True or False: In a Karnaugh map, there must be an adjacent cell for every possible single-variable change. For example, if a Karnaugh map has three input variables, then there must be three cells adjacent to every cell in the map where only one variable value changes in a move to that cell. 8. How many cells does a 3 input Karnaugh map have? a.) 4 b.) 6 c.) 8 d.) 6 e.) 24 f.) In a 4-variable Karnaugh map, how many input variables (A, B, C, or D) does a product have if its corresponding rectangle of 's contains 2 cells? a.) b.) 2 c.) 3 d.) 4 e.) Cannot be determined. A falling edge triggered latch copies data from the D input to the output when the clock is: a.) a logic b.) changing from a to a c.) a logic d.) changing from a to a

3 . True or False: Both the S and inputs to a D-latch have priority over the D and clock inputs. 2. Make the connections to the latch in the figure to the right that makes a divide-by-two circuit, i.e., divides D the frequency F in half at the output. F 3. Which of the following sums produces the truth table to the right? a.) c.) A + B + C b.) A + B + C c.) A + B + C B + C d.) B + C d.) None of the above 4. Fill in the truth table for the NAND circuit shown below. A '' X A X A B C X The next four problems use the state machine diagram to the right. Assume that the states are numbered so that bit S 2 is the MSB and bit S is the LSB. 5. What is the maximum number of states that this system can handle? I = Next state logic Clock 6. True or false: If the input I changed from to, but everything else remained unchanged, the output of the system would remain unchanged. 7. What is the current state of this system? Keep your answer in binary. D S 2 D S D S Output logic 8. If the clock were to pulse right now, what would the next state be? Keep your answer in binary. 9. True or False: enumbering the states of a state machine has no effect on the "next state" logic for the digital hardware implementation. 2. How many latches will a state machine with 22 states require? a.) b.) 2 c.) 3 d.) 4 e.) 5 f.) 6 g.) 7 2. If a group of four rows or columns in a Karnaugh map is identified with two variables, it is numbered,,, instead of,,,. Why?

4 22. For the multiplexer/selector shown to the right, what is the output Y? D D D 2 D 3 Y S S 23. For the Karnaugh map to the right, identify the problems with each of the three rectangles shown. (2 points each) ectangle : ectangle 2: AB ectangle ectangle 2 ectangle 3 CD ectangle 3: Medium answers 4 points each 24. Convert the Sum-of_Products circuit shown below to NAND-NAND logic, i.e., a circuit that contains nothing but NAND gates (and possible inverters at inputs). A B C 25. Complete the truth table to the right with the values for the following Sum-of-Products expression: X = ( A C) + ( A B C ) + ( A B C ) 26. In the Karnaugh map to the right, draw the best pattern of rectangles you can. Do not derive the SOP expression. A B C X CD AB X

5 27. Create a Karnaugh map from the truth table below. Do not worry about making the rectangles. A B C X 28. Show the D latch output waveform based on the inputs D, S,, and clock indicated in the graph to the right. Assume the latch captures on the rising edge. (The figure below is just for a reference.) Clock D D Clock Longer answers Points vary per problem 29. Make the state diagram that will output a when the sequence is detected in a serial stream of bits. For example, if the following binary stream is received: then s will be output here. (Notice that the last zero of the second pattern is shared with the first zero of the third pattern.) At all other times, the system will output zeros. Label the input D. (8 points) Initial state No digits

6 3. Derive the minimum SOP expression from the Karnaugh map below. (6 points) CD AB 3. Create the next state truth table and the output truth table for the state diagram to the right. Use the variable names S and S to represent the most significant and least significant bits respectively of the binary number identifying the state. Label the output 'X'. (8 points) K= K= K= K= K= K= K= K=

7 32. The three Boolean expressions below represent the next state bits (S ' and S ') and the output bit X based on the current state (S and S ) and the input A. Draw the logic circuit for the state machine including the latches and output circuitry. Be sure to label the latch inputs and other signals. (8 points) S ' = S A S ' = S A X = S S

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### Section 001. Read this before starting! You may use one sheet of scrap paper that you will turn in with your test.

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Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,

Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,

Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,

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Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 3 for Fall Semester,

### East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 3 for Fall Semester, 2006

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### Section 001. Read this before starting!

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### East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 3 for Fall Semester, 2005

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### East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 2 for Fall Semester, 2007

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### Section 002. Read this before starting!

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### Section 001 & 002. Read this before starting!

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### Section 001. Read this before starting!

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