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2 Fall 2 EE457 Instructor: Gandhi Puvvada Final Exam (3%) Date: 2//2, Friday Closed Book, Closed Notes; Time: 8: - :45M SGM23 Calculator and Cadence Verilog Guide allowed Total points: 235 Name: Perfect score: 22 / 235 ( 42 points) 25 min. Pipelining (Lab 7 Part 3 modified): On the next page you find the original lab 7 Part 3 Block Diagram, provided for your information. On the page after, you find a modified diagram for you to complete. Mr. Trojan says that what you intend to do at 2:M (at the beginning of a clock) can easily be done at :59PM of the previous day (at the end of the previous clock, logic wise, assuming timing is not an issue). The original forwarding in EX (controlled by FU, FORW) is now moved to ID (controlled by, ). nd the original forwarding in EX2 (controlled by FU2, FORW2) is now moved to EX (controlled by, ). These changes in forwarding do not cause any change in (a) HDU or generation of STLL T / F (b) generation of SKIP or SKIP2 T / F (c) the internal forwarding logic/mechanism in the register file T / F Draw the logic for the two new FUs (Forwarding Units). If you were to code this new design in RTL coding style, among ID, EX, and EX2, you would code first, and then, and finally. ssume that the register file is negative-edge triggered and the rest of the system is positive-edge triggered. In the RTL coding of Lab 7 Part 3, in the main clocked procedural block, we used ( if(stll) / if (~STLL)) (with / without) an else clause. ee457_final_fall2_r.fm December, 2 3:28 pmee457 Final Exam - Fall 2 / 4

3 Fall 2 EE457 Instructor: Gandhi Puvvada Final Exam (3%) Date: 2//2, Friday Closed Book, Closed Notes; Time: 8: - :45M SGM23 Calculator and Cadence Verilog Guide allowed Total points: 25 Name: Perfect score: 23 / 25 ( 4 points) 25 min. Pipelining (Lab 7 Part 3 modified): On the next page you find the original lab 7 Part 3 Block Diagram, provided for your information. On the page after, you find a modified diagram for you to complete. Mr. Trojan says that what you intend to do at 2:M (at the beginning of a clock) can easily be done at :59PM of the previous day (at the end of the previous clock, logic wise, assuming timing is not an issue). The original forwarding in EX (controlled by FU, FORW) is now moved to ID (controlled by, ). nd the original forwarding in EX2 (controlled by FU2, FORW2) is now moved to EX (controlled by, ). These changes in forwarding do not cause any change in (a) HDU or generation of STLL T / F (b) generation of SKIP or SKIP2 T / F (c) the internal forwarding logic/mechanism in the register file T / F Draw the logic for the two new FUs (Forwarding Units). If you were to code this new design in RTL coding style, among ID, EX, and EX2, you would code first, and then, and finally. ssume that the register file is negative-edge triggered and the rest of the system is positive-edge triggered. In the RTL coding of Lab 7 Part 3, in the main clocked procedural block, we used ( if(stll) / if (~STLL)) (with / without) an else clause. ee457_final_fall2_r.fm December 9, 2 3:56 pm EE457 Final Exam - Fall 2 / 4

4 ee457_final_fall2_r.fm December 9, 2 3:56 pm EE457 Final Exam - Fall 2 2 / 4 PC Reg. File R-Write FOR REFERCE ONLY IF ID EX EX2 WB I-MEM Signals HDU STLL XMEX2XMEX X_Mux FORW EX_ EX_SUB3 EX_DD4 EX_DD EX_ FU SUB3-3 XMEX R_Mux SKIP EX2_XMEX EX2_ X2_Mux EX2_SUB3 EX2_DD4 EX2_DD FORW2 EX2_ FU2 DD4 +4 R2_Mux WB_ SKIP2 Write WB_Write WB_ ID_XMEX= ID_ Matched with EX_ ID_XMEX ID_XMEX2 ID_ EX_ ID_ EX2_ revised 7/8/2. Complete all missing connections to the Reg. File. lso complete the (Result ddreee) connection in ID stage (ID_). 2. Complete all five enable () controls on the pipeline registers (including PC). 3. Complete the forwarding path from EX2 to EX. Should it start from upstream or downstream of the X2_mux? 4. Complete the skip controls(skip,skip2). 5. Draw the logic for the HDU, FU, and FU2, producing STLL,, FORW, FORW2. LB 7 Part 3 Block Diagram FOR REFERCE ONLY Fig.

5 ee457_final_fall2_r.fm December, 2 3:28 pmee457 Final Exam - Fall 2 3 / 4 PC I-MEM COMPLETE THIS IF ID EX EX2 WB Signals ID_ HDU Internally Forwarding Reg. File R-Write STLL XID_Mux ID OUT EX_XMEX EX_ Write a or 2 SUB3-3 EX_ EX_SUB3 EX_DD4 EX_DD EX_ R_Mux XEX_Mux EX2_SUB3 EX2_DD4 EX2_DD +4 R2_Mux EX2_ Write WB_ WB_Write WB_ SKIP EX OUT EX2_ EX2_ DD4 SKIP2 EX2 OUT 2/7/2 ID_XMEX= ID_ Matched with EX_ ID_XMEX ID_XMEX2 ID_ EX_ ID_ EX2_. Connect/label all missing connections to the Reg. File. lso complete the (Result ddreee) connection in ID stage (ID_). 2. Complete all five enable () controls on the pipeline registers (including PC). 3. Complete the forwarding paths into ID. If a path is not needed, write "no connection". 4. Complete the skip controls(skip,skip2). 5. Draw on a separate paper the logic for the, and, producing,,. LB 7 Part 3 Subpart Fig. modified for Fall2 Final Exam

6 ee457_final_fall2_r.fm December 9, 2 3:56 pm EE457 Final Exam - Fall 2 3 / 4 PC I-MEM COMPLETE THIS IF ID EX EX2 WB Signals ID_ HDU Internally Forwarding Reg. File R-Write STLL XID_Mux ID OUT EX_XMEX EX_ Write a or 2 SUB3-3 EX_ EX_SUB3 EX_DD4 EX_DD EX_ R_Mux XEX_Mux EX2_SUB3 EX2_DD4 EX2_DD +4 R2_Mux EX2_ Write WB_ WB_Write WB_ SKIP EX OUT EX2_ EX2_ DD4 SKIP2 EX2 OUT 2/7/2 ID_XMEX= ID_ Matched with EX_ ID_XMEX ID_XMEX2 ID_ EX_ ID_ EX2_. Connect/label all missing connections to the Reg. File. lso complete the (Result ddreee) connection in ID stage (ID_). 2. Complete all five enable () controls on the pipeline registers (including PC). 3. Complete the forwarding paths into ID. 4. Complete the skip controls(skip,skip2). 5. Draw on a separate paper the logic for the, and, producing,,. LB 7 Part 3 Subpart Fig. modified for Fall2 Final Exam

1.3 A Branch Delay Slot is (always advantageous / always disadvantageous / depends on compiler s ability to fill the slot) Explain

1.3 A Branch Delay Slot is (always advantageous / always disadvantageous / depends on compiler s ability to fill the slot) Explain ee57_mt_sp2.fm Spring 2 EE57 Instructor: Gandhi Puvvada Midterm Exam (2%) Date: //2, Friday Time: :M - 2:2PM in THH2 Name: Total points: 28 Perfect score: 9 / 28 ( 23 points) 5 min. Pipelining 5 6 5 3.