DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 2

Transcription

1 DIGITAL LOGIC WITH VHDL (Fall 23) Unit 2 Use of std_logic_vector. CONCURRENT DESCRIPTION with-select, when-else statements Examples: multiplexor, decoder.

2 std_logic_vector In the example, we use the std_logic_vector tpe for an input signal. use ieee.std_logic_64.all; entit test is port ( A: in std_logic_vector (3 downto ); -- A: A3 A2 A A : out std_logic); A = A 3 A 2 A A end test; architecture struct of test is -- The circuit represents an AND gate -- with 4 inputs: A(3), A(2), A(), A() <= A(3) and A(2) and A() and A(); A(3) A(2) A() A()

3 std_logic_vector In the example, we use the std_logic_vector tpe for an output signal. use ieee.std_logic_64.all; entit tst is port ( A,B: in std_logic; F: out std_logic_vector (3 downto ); -- F: F3 F2 F F end tst; architecture struct of tst is A B F = F 3 F 2 F F F(3) F() <= A and B; F() <= A xor B; F(2) <= A or B; F(3) <= not(a); F(2) F() F()

4 CONCURRENT DESCRIPTION In this description, circuits are specified in an structured fashion. The order of the statements is irrelevant: all the statements represent circuits that are working at the same time. This tpe of description is well-suited for combinatorial circuits. The use of sentences with and, or, xor, nand, nor, xnor, and not is a basic instance of the concurrent description. It is sometimes called horizontal description. In Unit 4, the so-called structural description is just a generalization of the concurrent description. Since we alread know how to build circuits based on logic gates, we now present two concurrent assignment statements (with select, when else), which are far more powerful than the statements with logic gates when it comes to describe complex circuits.

5 CONCURRENT ASSIGNMENT STATEMENTS: a b Selected Signal Assignment: WITH-SELECT: This statement allows assigning values to a signal based on certain criterion. MUX 2-to-: s s a b = s(a b + a b) + s(a b + a b) = sa + sb with s select: 's'specifies the selection criterion when specifies the value assigned to '' for each value of 's' when others: we need to include all the possible values of 's', that are 9 according to std_logic tpe. s a b use ieee.std_logic_64.all; entit m_mux2 is port ( a, b, s: in std_logic; : out std_logic); end m_mux2; architecture st of m_mux2 is with s select <= a when '', b when others; end st;

6 Selected Signal Assignment (WITH SELECT): MUX 8-to- use ieee.std_logic_64.all; a b c d e f g h s 3 entit m_mux8 is port ( a,b,c,d,e,f,g,h: in std_logic; s: in std_logic_vector (2 downto ); : out std_logic); end m_mux8; architecture struct of m_mux8 is with s select <= a when "", -- note ',' instead of ';' b when "", c when "", d when "", e when "", f when "", g when "", h when others;

7 a b c d e f Selected Signal Assignment(WITH SELECT): MUX 6-to s 3 Value '-': Don't care output It helps the snthesizer to optimize the circuit use ieee.std_logic_64.all; entit m_mux6 is port ( a,b,c,d,e,f: in std_logic; s: in std_logic_vector (2 downto ); : out std_logic); end m_mux6; architecture struct of m_mux6 is with s select <= a when "", b when "", c when "", d when "", e when "", f when "", '-' when others;

8 bcd leds 7-segment DECODER (outputs >= inputs) use ieee.std_logic_64.all; entit sevenseg is port ( bcd: in std_logic_vector (3 downto ); sevenseg: out std_logic_vector (6 downto ); EN: in std_logic_vector (3 downto )); end sevenseg; EN 4 7-seg decoder architecture struct of sevenseg is signal leds: std_logic_vector (6 downto ); -- a b c d e f g -- leds6 leds5 leds4 leds3 leds2 leds leds with bcd select leds <= "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", " " when others; -- Nexs3: LEDs are active low. -- Each 7-seg displa has an active-low enable EN <= ""; sevenseg <= not(leds);

9 Decoder 2-to-4 with enable: use ieee.std_logic_64.all; w E 2 DECODER 4 entit dec2to4 is port (w: in std_logic_vector ( downto ); E: in std_logic; : out std_logic_vector (3 downto )); end dec2to4; architecture struct of dec2to4 is signal Ew: std_logic_vector (2 downto ); Ew <= E & w; -- concatenation with Ew select <= "" when "", "" when "", "" when "", "" when "", "" when others;

10 CONCURRENT ASSIGNMENT STATEMENTS : Conditional signal assignment: WHEN - ELSE: Similarl to the selected signal assignment, this statement allows a signal to take one out of man values based on a certain condition. The sntax however is different and it allows to describe circuits in a more compact fashion. Example: MUX 2-to- a b If the condition on when is FALSE, we assign a value to after else. This assignment can also be conditioned b another when-else clause (see next example) s use ieee.std_logic_64.all; entit mux2_cond is port ( a, b, s: in std_logic; : out std_logic); end mux2_cond; architecture est of mux2_cond is <= a when s = '' else b; end est;

11 Conditional signal assignment (WHEN - ELSE): Example: MUX 4-to- a b c d s Note that the assignment on b is conditioned b another when else clause. Same for c. Onl the assignemnt of d is not conditioned. There is no limit to the number of nested conditions use ieee.std_logic_64.all; entit mux4_cond is port (a, b, c, d: in std_logic; s: in std_logic_vector ( downto ); : out std_logic); end mux4_cond; architecture est of mux4_cond is <= a when s = "" else b when s = "" else c when s = "" else d; end est;

12 w3 w2 w w w 3 Conditional signal assignment (WHEN - ELSE): Example: Priorit Encoder 4-to-2 PRIORITY ENCODER when-else has a priorit level, thus it is eas to describe a priorit encoder. With with-select, describing this circuit would be ver tedious. z w 2 w w z x x x x x x use ieee.std_logic_64.all; entit m_prienc is port ( w: in std_logic_vector (3 downto ); : out std_logic_vector ( downto ); z: out std_logic); end m_prienc; architecture struct of m_prienc is <= "" when w(3) = '' else "" when w(2) = '' else "" when w() = '' else ""; z <= '' when w = "" else ''; -- If no input is '', z is ''

13 Conditional signal assignment (WHEN - ELSE): Example: 4-bit comparator A B COMPA- RATOR AeqB AgB AlB Note the use of the operators =, >, < to compare numbers Alwas indicate what tpe of numbers we are working with. In the example we are using unsigned numbers. For 2 s complement, use signed. use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; -- unsigned #s entit m_comp is port ( A,B: in std_logic_vector (3 downto ); AeqB, AgB, AlB: out std_logic); end m_comp; architecture struct of m_comp is AeqB <= '' when A = B else ''; AgB <= '' when A > B else ''; AlB <= '' when A < B else '';

14 Conditional Signal Assignment (WHEN - ELSE): Example: Demultiplexor use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; x 2 3 a b c d entit m_demux is port ( s: in std_logic_vector ( downto ); x: in std_logic; a,b,c,d: out std_logic); end m_demux; 2 s architecture struct of m_demux is a <= x when s = "" else ''; b <= x when s = "" else ''; c <= x when s = "" else ''; d <= x when s = "" else '';