Introduction to HDL Design
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- Esmond Marsh
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1 Introduction to HL esign Traditionally, digital design was done with schematic entry. In today s competitive business environment, building costeffective products quickly is best done with a top down methodology utilizing hardware description languages (HLs) and synthesis. Schematic entry still used at the board level, but this will probably also change. s a first example of the power of using HLs, consider the code below. It implements a 8 bit shift register with enable. It is easially changed to about any width with a few quick key strokes. In the amount of time it takes to sneeze, it can be synthesized into the schematic on the next page. LIB ieee; USE ieee.std_logic_1164.ll; USE ieee.std_logic_vector_arith.ll; ENTIT shift_reg IS POT( clk_50 : IN ST_LOGIC; --50Mhz input clock reset_n : IN ST_LOGIC; --reset async active low data_ena : IN ST_LOGIC; --serial data enable serial_data : IN ST_LOGIC; --serial data parallel_data : BUFFE ST_LOGIC_VECTO(7 OWNTO 0) ); EN shift_reg; CHITECTUE struct OF shift_reg IS BEGIN shift_register: POCESS (clk_50, reset_n, data_ena, serial_data, parallel_data) BEGIN IF (reset_n = 0 ) THEN parallel_data <= " "; ELSIF (clk_50 EVENT N clk_50 = 1 ) THEN IF (data_ena = 1 ) THEN parallel_data(7) <= serial_data; --input gets input data FO i IN 0 TO 6 LOOP parallel_data(i) <= parallel_data(i+1); --all other bits shift down EN LOOP; ELSE parallel_data <= parallel_data; EN IF; EN IF; EN POCESS shift_register; Introduction to HL esign 1
2 Introduction to HL esign 2 Synthsized 8-Bit Shift egister 0 clk_50 serial_data parallel_data(7:0) ix178 ix158 ix168 data_ena reset_n ix188 ix126 ix116 ix146 ix136 ix176 ix166 ix156 ix237 ix239 ix186 ix200 ix224 ix128 ix118 ix148 ix138 ix130 ix120 ix140 ix160 ix150 ix180 ix ix
3 HLs - Motivation Increased productivity shorter development cycles, more features, but... still shorter time-to-market, 10-20K gates/day/engineer Flexible modeling capabilities. can represent designs of gates or systems description can be very abstract or very structural esign reuse is enabled. packages, libraries, support reusable, portable code esign changes are fast and easily done convert a 8-bit register to 64-bits... four key strokes, and its done! exploration of alternative architectures can be done quickly Use of various design methodologies. top-down, bottom-up, complexity hiding (abstraction) Technology and vendor independence. same code can be targeted to CMOS, ECL, Gas same code for: TI, NEC, LSI, TMSC same code for:.5um,.35um,.25um,.18um Enables use of logic synthesis which allows a investigation of the area and timing space. ripple adder or CL?, How many stages of look ahead? HLs can leverage software design environment tools. vi, emacs, cvs, lint, grep, make files Using a standard language promotes clear communication of ideas and designs. schematic standards?... what s that... a tower of Babel. Introduction to HL esign 3
4 HLs - What are they? How do we use them? Hardware escription Language (HL) is a programming language used to model the intended operation of a piece of hardware. n HL can facilitate: abstract behavioral modeling -no structural or design aspect involved hardware structure modeling -a hardware structure is explicitly implied In this class we will use an HL to describe the structure of a hardware design. When we use an HL to create hardware by logic synthesis, we will write code at the egister Transfer Language (TL) level. t this level we are implying certain hardware structures when we understand apriori. When programming at the TL level, we are not describing an algorithm which some hardware will execute, we are describing a hardware structure. Without knowing beforehand what the structure is we want to build, use of an HL will probably produce a steaming pile (think manure) of gates which may or may not function as desired. ou must know what you want to build before you describe it in an HL. Knowing an HL does not relieve you of thoroughly understanding digital design. Introduction to HL esign 4
5 We will use VHL as our HL. HL s- VHL or Verilog VHL more capable in modeling abstract behavior more difficult to learn strongly typed 85% of FPG designs done in VHL Verilog easier and simpler to learn weakly typed 85% of SIC designs done with Verilog (1993) The choice of which to use is not based solely on technical capability, but on: personal preferences E tool availability commercial business and marketing issues We use VHL because strong typing keeps students from getting into trouble if you know VHL, Verilog can be picked up in few weeks If you know Verilog, learning VHL will take several months The Bottom line...either language is viable. Employers don t care as long as you know one of them. Introduction to HL esign 5
6 VHL - Origins oots of VHL are in the Very High Speed Integrated Circuit (VHSIC) Program launched in 1980 by the US epartment of efense (O). The VHSIC program was an initiative by the O to extend integration levels and performance capabilities for military integrated circuits to meet or exceed those available in commercial ICs. The project was successful in that very large, high-speed circuits were able to be fabricated successfully. However, it became clear that there was a need for a standard programming language to describe and document the function and structure of these very complex digital circuits. Therefore, under the VHSIC program, the O launched another program to create a standard hardware description language. The result was the VHSIC hardware description language or VHL. The rest is history... In 1983, IBM, TI and Intermetrics were awarded the contract to develop VHL. In 1985, VHL V7.2 released to government. In 1987, VHL became IEEE Standard In 1993, VHL restandardized to clarify and enhance the language resulting in VHL Standard In 1993, development began on the analog extension to VHL, (VHL-MS). Extends VHL to non-digital devices and micro electromechanical components. This includes synthesis of analog circuits. Introduction to HL esign 6
7 Some Facts of Life (For SIC designers) The majority of costs are determined by decisions made early in the design process. Hurry up and make all the mistakes. Get them out of the way! Typical SIC project: concept to first silicon about 9 months. 95% of designs work as the specification states. 60% of designs fail when integrated into the system. The design was not the right one, but it works. Technology is changing so fast, the only competitive advantage is to learn faster than your competitors. To design more stuff faster, your level of abstraction in design must increase. Using HLs will help to make digital designers successful. (and employed!) Introduction to HL esign 7
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