VERILOG CODES //SPECIAL COMBINATIONAL LOGIC CIRCUITS

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1 VERILOG CODES //SPECIAL COMBINATIONAL LOGIC CIRCUITS //VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER (DATAFLOW MODEL) module half_adder(a, b, sum, cout); input a,b; output sum,cout; assign sum=a ^ b; assign cout=a & b; //VERILOG CODE FOR FULL ADDER (STRUCTURAL MODEL). // component ha(half adder). module ha(a, b, s, c); input a, b; output s, c; xor (s, a, b); and (c, a, b); // full adder using two half adders and or gate module full_adder_structural(a,b,cin, sum,cout); input a,b,cin; output sum,cout; wire c1,c2,s1; ha u1(a,b,s1,c1); ha u2(s1,cin,sum,c2); or (cout,c1,c2); //VERILOG CODE FOR FULL ADDER (DATA FLOW MODEL). module full_adder_data_flow(a,b,cin, sum,cout); input a,b,cin; output sum,cout; assign sum=a ^ b ^ cin; assign cout=( a & b ) ( b & cin ) ( cin & a ); //VERILOG CODE FOR FULL-ADDER (BEHAVIORAL MODEL). module full_adder_behavioral(a,b,cin,sum,cout); input a,b,cin; output reg sum,cout; // output are to be declared as registers reg T1,T2,T3,S1; // as variables (internal signals) always@(a,b,cin) T1=a&b; T2=b&cin; T3=cin&a; cout=t1 T2 T3; S1=a^b; sum=s1^cin;

2 //VERILOG CODE FOR FULL-ADDER (MIXED STYLE OF MODEL). module full_adder_mixed(a,b,cin, sum,cout); input a,b,cin; output sum, cout; reg cout; wire s1; reg t1,t2,t3; xor u1(s1,a,b); // structural xor gate assign sum=s1 ^ cin; // data flow model for sum // carry using behavioral description always@(a,b,cin) t1=a & b; t2=a & cin; t3=cin & b; cout=t1 t2 t3; //VERILOG CODE FOR 8:1 MUX module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT); input [2:0] sel; //sel[2], sel[1], sel[0] input A,B,C,D,E,F,G,H; output reg MUX_OUT; always@(a,b,c,d,e,f,g,h,sel) case(sel) 3'd0:MUX_OUT=A; 3'd1:MUX_OUT=B; 3'd2:MUX_OUT=C; 3'd3:MUX_OUT=D; 3'd4:MUX_OUT=E; 3'd5:MUX_OUT=F; 3'd6:MUX_OUT=G; 3'd7:MUX_OUT=H; default:; // indicates null case //VERILOG CODE FOR 2 TO 4 DECODER( SYNCHRONOUS WITH ENABLE). module decoder_2to4(i, en, y); input [1:0] i; //i[1], i[0] input en; output reg [3:0] y; always@(i,en)

3 if(en==1) y=4'd0; case(i) 2'd0: y=4'b0001; 2'd1: y=4'b0010; 2'd2: y=4'b0100; default: y=4'b1000; case //VERILOG CODE FOR 8 TO 3 ENCODER (WITHOUT PRIORITY). module encoder_8to3_without_priority(i, en, y); input [7:0] i; input en; output reg [2:0] y; always@(i,en) if(en==1) //disabled, output=0 y=4'd0; case(i) 8'b :y=3'd0; 8'b :y=3'd1; 8'b :y=3'd2; 8'b :y=3'd3; 8'b :y=3'd4; 8'b :y=3'd5; 8'b :y=3'd6; 8'b :y=3'd7; default:; case //VERILOG CODE FOR 8 TO 3 ENCODER (WITH PRIORITY). module encoder_8to3_with_priority(i, en, y); input [7:0] i; input en; output reg [2:0] y; always@(i,en) if(en==1) y=3'd0; casex(i) 8'b1xxxxxxx:y=3'd7; 8'b01xxxxxx:y=3'd6; 8'b001xxxxx:y=3'd5;

4 8'b0001xxxx:y=3'd3; 8'b00001xxx:y=3'd4; 8'b000001xx:y=3'd2; 8'b x:y=3'd1; default:y=3'd0; case //VERILOG CODE FOR 4 BIT BINARY TO GRAY CONVERTER. module binary_to_gray_4bit(b, g); input [3:0] b; output [3:0] g; assign g[3]=b[3]; assign g[2]=b[3] ^ b[2]; assign g[1]=b[2] ^ b[1]; assign g[0]=b[1] ^ b[0]; //VERILOG CODE FOR 1:8 DEMULTIPLEXER. module demux_1to8(i, sel, y); input i; input [2:0] sel; output reg [7:0] y; always@(i,sel) y=8'd0; case(sel) 3'd0:y[0]=i; 3'd1:y[1]=i; 3'd2:y[2]=i; 3'd3:y[3]=i; 3'd4:y[4]=i; 3'd5:y[5]=i; 3'd6:y[6]=i; default:y[7]=i; case //VERILOG CODE FOR 1 BIT COMPARATOR. module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B);

5 // Make a 4-bit comparator from 4 1-bit comparators module Compare4(A4, B4, Equal, Alarger, Blarger); input [3:0] A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, BI0, Bl1, Bl2, Bl3; Compare1 cp0(a4[0], B4[0], e0, Al0, Bl0); Compare1 cp1(a4[1], B4[1], e1, Al1, Bl1); Compare1 cp2(a4[2], B4[2], e2, Al2, Bl2); Compare1 cp3(a4[3], B4[3], e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 (Al2 & e3) (Al1 & e3 & e2) (Al0 & e3 & e2 & e1)); assign Blarger = (~Alarger & ~Equal); //SEQUENTIAL CIRCUITS. //VERILOG CODE FOR FLIP-FLOPS. // SR FLIP-FLOP module sr_flipflop(s,r,clk, q,qbar); input s,r,clk; output reg q,qbar; reg [20:0] clk_div=21'd0; wire [1:0] temp; always@(clk int_clk=clk_div[20]; always@(int_clk) temp={s,r}; case(temp) 2'b00: q=q; qbar=qbar; 2'b01: q=1,b0; qbar=~q; 2'b10: q=1'b1; qbar=~q; default: q=1'bz; qbar=1'bz; case // D FLIP-FLOP module d_ff(d,clk, q,qb); input d,clk; output reg q,qb; reg [22:0] clk_div=23'd0;

6 int_clk=clk_div[21]; if(d==0) q=1'b0; q=1'b1; qb=~q; //JK FLIP-FLOP. module jk_ff(jk, clk, q,qb); input [1:0] jk; input clk; output reg q,qb; reg [22:0] clk_div=23'd0; int_clk=clk_div[21]; case(jk) 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=~q; default:q=q; case qb=~q; // T FLIP-FLOP. module t_ff(t,clk, q,qb); input t,clk; output reg q,qb; reg [22:0] clk_div=23'd0; int_clk=clk_div[21]; always@(posedge(int_clk)) if(t==0)

7 q=1'b0; q=~q; qb=~q; // VERILOG CODE FOR 8 BIT ALU. module alu_8_bit(x,y, opcode, yout); input [7:0] x,y; input [2:0] opcode; output reg [15:0] yout; always@(x,y,opcode) case(opcode) 3'b000:yout=x+y; 3'b001:yout=x-y; 3'b010:yout=x*y; 3'b011:yout=x&y; 3'b100:yout=x y; 3'b101:yout=~x; 3'b110:yout=x^y; default:yout=~(x&y); case //4 BIT BINARY COUNTER (SYNCHRONOUS RESET). module binary_count_sync(clk,rst, count); input clk,rst; output reg [3:0] count; reg [21:0] clk_div=22'd0; int_clk<=clk_div[20]; always@(posedge(int_clk)) if(rst==1) count=3'd0; count=count+1; //4 BIT BINARY COUNTER WITH ASYNCHRONOUS RESET. module binary_count_ashyn(clk,rst, count); input clk,rst;

8 output reg [3:0] count; reg [21:0] clk_div=22'd0; ) int_clk=clk_div[20]; if(rst==1) count=4'd0; if(int_clk==1) count=count+1; //4 BIT BINARY UP DOWN COUNTER module binary_up_down_counter(clk,up_down, q); input clk,up_down; output reg [3:0] q; reg [21:0] clk_div=22'd0; integer temp=0; int_clk=clk_div[20]; if(up_down==1) if(temp==9) temp=0; temp=temp+1; if(temp==0) temp=9; temp=temp-1; case(temp) 0:q=4'd0; 1:q=4'd1; 2:q=4'd2; 3:q=4'd3; 4:q=4'd4;

9 5:q=4'd5; 6:q=4'd6; 7:q=4'd7; 8:q=4'd8; 9:q=4'd9; default:; case

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It