Hardware description languages (HDL) VHDL - continuation

Transcription

1 Hardware description languages (HDL) VHDL - continuation

2 Synthesizable code in VHDL VHDL is frequently used for elctronic design simulation and its synthesis. Syntess is the process in which the VHDL source is compiled and mapped into FPGA or ASIC technologies. FPGA manufacturers offer cheap or free synthesis tools. ASIC synthesis tools are usually very expensive. Not all VHDL structures are synthesizable (although they can be simulated). For example: constructions which have explicit time, wait for 10 ns VHDL subset synthesizable = IEEE

3 Free packages for simulation and design which use both languages: VHDL/Verilog: ISE can call ModelSim

4 Objects, data types and operators Objecs used for data representation and storage Basic types (used for design description for synthesis or used to create sunctional tests wave tests): signals, variables and constants Each declared object has a specific data type (such as bit or integer) with an unique set of possible values. For example: a bit object can have only two possible values, 0 and 1 Note: VHDL symbol <= - represents assigning operator (assigns the value from the right side for the variable from the left side)

5 IEEE 1164 Standard Logic Standard Logic Data Types The package std_logic_1164 is compiled in a library called ieee, and includes the following data types: Type Std_ulogic represents a single wire which can have different logic values std_ulogic is an enumeration type similar with bit type from 1076 standard. It is an unresolved data type. This type of signal can have only one driver type.

6 Std_ulogic_vector type Represents a wire collection or a bus having an arbitrary size. type std_ulogic_vector is array ( natural range <> ) of std_ulogic; Std_ulogic_vector represents a std_ulogic area, and is analog with the bit_vector standard type. Tipul Std_logic Is a resolved data type based on std_ulogic (it is a subtype), with the follwing declaration: subtype std_logic is resolved std_ulogic; In the multiple drivers case, the nine std_logic values are resolved with values as following: ("std_logic" allows the existence of multiple drivers for a simple signal) Tipul Std_logic_vector type std_logic_vector is array ( natural range <>) of std_logic;

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10 Standard operators: The values, signals and variables of a certain type can be combined in expressions for operators use:

11 Conditional instructions (control ) describe the combinational functions, and indicate priorities in operations, or specify other high-level behaviors. If-Then-Else if first_condition then statements elsif second_condition then statements else statements end if; if outer_condition then statements else if inner_condition then statements end if; end if; procedure Mux(signal A, B, S: in std_logic; signal O: out std_logic) is There can be used more levels of if-then-else declaration. The specified condition in a if-then-else construction must evaluate a Boolean type. begin if S then -- Error: S is not Boolean! O <= B; else O <= A; end if; end Mux; if S = '1' then CORECT! O <= B; else O <= A; end if; end Mux;

12 Case Statements Can be used as an alternative construction to if then- else. case control_expression is when test_expression1 => statements when test_expression2 => statements when others => statements end case; Test expressions must be mutually exclusive and there cannot be two true test expressions at the same time. The difference from if then-else consists in the fact that the lattes implies a priority of the conditions, while for the case instruction this is not true.

13 FOR loops For loop allows the specification of a fixed number of iterations in design description. Example: 8-bit parity generator using a for loop. For loop includes an automatic declaration for the index. library ieee; use ieee.std_logic_1164.all; entity parity10 is port(d: in std_logic_vector(0 to 9); ODD: out std_logic); constant WIDTH: integer := 10; end parity10; architecture behavior of parity10 is begin process(d) variable otmp: Boolean; begin otmp := false; for i in 0 to D'length - 1 loop if D(i) = '1' then otmp := not otmp; end if; end loop; if otmp then ODD <= '1'; else ODD <= '0'; end if; end process; end behavior;

14 Functions and procedures HDL functions and procedures are called subprograms, and represent a direct analogy with the functions and procedures defined in high level programming languages. The procedure subprogram which has an argument list consisting of inputs and outputs and does not return any value. Function subprogram which has only inputs in the list of arguments and returns a value. Subprograms can be defined locally (in an architecture) or in a package. Declarations from subprogram are sequential (as in the process). Can be called from another area of an architecture or a process. Can also be called from another subprogram. Avoid writing recursive functions and procedures, which can not be synthesized. package my_package is package was compiled in a library function my_global_function(...) return bit; end my_package; package body my_package is function my_global_function(...) return bit is begin... end my_global_function; end my_package;... use work.my_package.my_global_function; entity my_design is begin... end my_design; my_global_function() has been declared in my_package It is obtained a global subprogram.

15 Local subprograms Are declared locally, in an arhitecture. architecture my_architecture of my_design is begin my_process: process(...) function my_local_function(...) return bit is begin... end my_local_function; begin... end process my_process; end my_architecture;

16 Functions A subprogram with zero or more input arguments and which returns a single output value. function maxval (arg1, arg2: integer) return integer is variable result: integer; begin if arg1 > arg2 then result := arg1; else result := arg2; end if; return result; end maxval; function rising_edge (signal s: std_logic) return boolean is begin return (s'event and (To_X01(s) = '1') and (To_X01(s'last_value) = '0')); end;

17 Procedures Do not return values, the arguments include both inputs and outputs. Are used to modularize a complex description of a design. Are used in another area from an architecture or a process. Ex: JK flip-flop cu reset asincron: procedure jkff (signal Rst, Clk: in std_logic; signal J, K: in std_logic; signal Q,Qbar: inout std_logic) is begin if Rst = 1 then Q <= '0'; elsif Clk = 1 and Clk event then if J = '1' and K = '1' then Q <= Qbar; elsif J = '1' and K = '0' then Q <= '1'; elsif J = '0' and K = '1' then Q <= '0'; end if; end if; Qbar <= not Q; end jkff; Variables declared in a procedure are not stored between different executions of the procedure. In processes, the variables keep their values between executions.

18 Test Benches VHDL used in the simulation process There are applied sequences of stimuli at the input of the circuit which must be tested (the Unit Under Test, or UUT). Test waveforms represent the values of the signals at different moments in time.

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20 Using Project Navigator For Simulation and Modeling (generating Testbench and Modelsim call) To a VHDL module (or another description) can have associated a testbench :

21 There can be prescribed some timing information

22 In the blue zone can be programmed the test signals In the yellow zone the desired output can be specified Typing save and verifying that is actually generated a VHDL file Which is a description of the testbench (waveforms+associated module)

23 It is emphasized this bench (wotkbench) there can be more And are automatically opened the associated simulation tools

24 Can be observed that a VHDL module corresponds to a bench This will be transmitted and analysed by Modelsim which has more sophisticated tools for viewing waveforms etc.

25 A minimal observation can be directly observed in Project Navigator By activating Generate Expected Simulation Results

26 Simulations can be associated with different stages in the design process (behavioral, translate). But the one with the most accurate information is post place and route Window opened by Modelsim Here can be clearly observed the effects when takng into account certain propagation times specific to placing and routing made in place and route plus the temporal information specific to the device used in the project (FPGS/CPLD).

27 "Bench2" is actually a hierarchy of VHDL modules that contain embedded timing information that "Project Navigator" tool provides. In this case VHDL is used assimulation language

28 VHDL code examples Describing a comparator using IEEE 1164 standard logic comment declarare library IEEE library is loaded. Use - specifies what is available from ieee library for the design (declared by entity and arhitecture). The general form inclues 3 fields, seperates by point. std_logic and std_logic_vector, are standard data types from IEEE 1164 standard and in the associated IEEE library. Describes the functionality of the comparator

29 Example: counter with asynchronous reset, parallel loading and configurable dimension. (using 'unsigned' type and generics. )

30 4-bit synchronous up counter. active high, synchronous reset. Active high enable.

31 Verilog is a harware description language similar from the in syntax point of view to the C programming language.

32 Modules described in Verilog module toggle(q, clk, reset); <functionality of module> endmodule reset clk toggle q Each module can be defined on four levels of abstraction: Behavioral or on the algorithmic level Dataflow level Gate level Switch level Verilog allows the introduction of different abstraction levels in the same module.

33 Basic concepts Comments by introducing // or /* - */ for a block or more lines Number specification. <size> <base format><number> Number of bits Examples: 4 b habc 16 d h13x 6 d3 12 b1111_0000_1010 d or D for decimal h or H for hexadecimal b or B for binary o or O for octal X or x: don t care Z or z: high impedence _ : used for clarity Number which depends on the base

34 Nets represent connections between elements. Are declared using the keyword wire. wire a; wire b, c; wire d=1 b0; Registers represent the data storage elements. They have the same value until a new value is entered. In Verilog, un register is more a variable which can store a value. Does not require a clock as hardware registers do. reg reset; initial begin reset = 1 b1; #100 reset=1 b0; end

35 A net or a register can be declared as a vector. Declaration examples: wire a; wire [7:0] bus; wire [31:0] busa, busb, busc; reg clock; reg [0:40] virt_address; It is possible to address bits or parts of the vector busa[7] bus[2:0] virt_addr[0:2] For counting is used integer. Example: integer counter initial counter = 1;

36 Real real delta; initial begin delta = 4e10; delta = 2.13; end integer i; initial i = delta; Arrays. Can define real, integer or register tables. integer count[0:7]; reg [4:0] port_id[0:7]; integer matrix[4:0][0:255];

37 Memory. Used for modeling RAM and ROMs. Are modeled using tables on unidimensional registers. Examples. reg mem1bit[0:1023]; reg [7:0] membyte[0:1023]; membyte[511]; Parameters. Defining constants which cannot be used as variables. parameter port_id=5; Arrays can be stored in registers. The width of the register variable must be sufficiently high to store the whole array. reg [8*19:1] string_value; initial string_value = Hello Verilog World ;

38 Modules and ports module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; input c_in; endmodule Declaration of ports (input, output, inout) are implicitly declared wire. if the output stores the value, they have to be declared reg module DFF(q, d, clk, reset); output reg q; input d, clk, reset; endmodule

39 Declaring modules (ANSI C Style) module fulladd4(output reg[3:0] sum, output reg c_out, input [3:0] a, b, input c_in); endmodule

40 module Top; reg [3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT; // one way Modules instantiation fulladd4 FA1(SUM, C_OUT, A, B, CIN); // another possible way fulladd4 FA2(.c_out(C_OUT),.sum(SUM),.b(B),.c_in(C_IN),.a(A)); endmodule external, the inputs can be reg or wire; internal must be wire External must be wire module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; input c_in; endmodule

41 Gate level modeling (structural). wire Z, Z1, OUT, OUT1, OUT2, IN1, IN2; and a1(out1, IN1, IN2); nand na1(out2, IN1, IN2); xor x1(out, OUT1, OUT2); not (Z, OUT); buf final (Z1, Z);. All instantiations are executed concurrently as in hardware. The name of the instantiation is not required

42 Instantiation tables for gates wire [7:0] OUT, IN1, IN2; // array of gates instantiations nand n_gate [7:0] (OUT, IN1, IN2); // which is equivalent to the following nand n_gate0 (OUT[0], IN1[0], IN2[0]); nand n_gate1 (OUT[1], IN1[1], IN2[1]); nand n_gate2 (OUT[2], IN1[2], IN2[2]); nand n_gate3 (OUT[3], IN1[3], IN2[3]); nand n_gate4 (OUT[4], IN1[4], IN2[4]); nand n_gate5 (OUT[5], IN1[5], IN2[5]); nand n_gate6 (OUT[6], IN1[6], IN2[6]); nand n_gate7 (OUT[7], IN1[7], IN2[7]);

43 Dataflow Modeling The module is defined in order to specify data communication between hardware registers and how data is processed in design Continuous assignment the main construction in data communication modeling assign out = i1 & i2; assign addr[15:0] = addr1[15:0] ^ addr2[15:0]; assign {c_out, sum[3:0]}=a[3:0]+b[3:0]+c_in; Continuous assignment is always active and the assignment expression is evaluated when the variable on the right-hand side is modified. Left-hand side must be a scalar or a vector. The right-hand side must be either a register, wire, integer or real.

44 Types of operators The operators are similar to the ones in C. Arithmetic: *, /, +, -, % and ** Logical:!, && and Relational: >, <, >= and <= Equality: ==,!=, === and!== Bitwise: ~, &,, ^ and ^~ Reduction: &, ~&,, ~, ^ and ^~ Shift: <<, >>, >>> and <<< Concatenation: { } } Replication: {{}}}} Conditional:?:

45 Example: module mux4(out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; output s1, s0; assign out = (~s1 & ~s0 & i0) (~s1 & s0 & i1) (s1 & ~s0 & i2) (s1 & s0 & i3); // OR THIS WAY assign out = s1? (s0? i3:i2) : (s0? i1:i0); endmodule

46 Behavioral modeling The design is expressed at an algorithmic level (is not required anymore an analysis which includes gates and data communication). At this level the design is similar with C programming. The algorithm is implemented between 2 declarations: always and initial. Each always and initial represents a different activity. Note that they run in parallel. There can be more initial and always declarations but they can not be interlaid... reg a, b, c; initial a=1 b0;.. always begin b = a ^ 1 b1; c = a + b; end..

47 initial initial the block starts at time 0, and is executed only once If there are more initial blocks, each one starts to be executed at time 0, each block finishes independently. Multiple behavioral declaration are grouped using begin and end. reg x, y, m; initial m=1 b0; initial begin x=1 b0; y=1 b1; end

48 always always starts at time 0 and executes the instructions continuously in the always block (as in loops). It models a block in which the activity of the digital circuit repeats continuously. integer count; count=0; always begin count=count+1; end

49 Events An event modifies the values of the register or the net. Is used to start the execution in a block is used to specify the control of a certain event The declarations can be executed when modifying the values of the signals, or on the positive or negative transitions of the signals (posedge) (negedge). input clock; integer count; count=0; begin count=count+1; end input clock; integer count; count=0; begin count=count+1; end input clock1, clock 2; integer count; count=0; or clock2) begin count=count+1; end

50 Procedural assignments modifies the values of the variables for reg, integer, or real. The values are not modified until another assignment is used There are 2 types of procedural assignments: blocking si nonblocking. Blocking statements, use the operator=, are executed in the same order in which they are specified in the sequential block reg x, y; initial begin x=1 b1; y=1 b0; end Nonblocking statements, use the operator <=, are executed without blocking the declarations in a sequential block. reg x, y; initial begin x<=1 b1; y<=1 b0; end

51 clock) begin a = b; b = a; end clock) begin a <= b; b <= a; end Nonblocking removes the passing conditions. On the rising edge of the clock, are read the values from the righthand side, the expressions are evaluated and assigned to the left-hand side.

52 Similar to C Appear every time in always and initial blocks. if(x) begin y= 1 b1; z= 1 b0; end. expression if (count < 10) count = count+1; else count = 0;.. if(alu_control == 0) y = x + z; else if (alu_control == 1) y = x z; else if (alu_control == 2) y = x * z; else y = x;. reg [1:0] alu_control;.. case (alu_control) 2 d0 : y = x + z; 2 d1 : y = x z; 2 d2 : y = x * z; default: y=x; endcase

53 integer count; integer y=1; integer x=2; initial for (count = 0; count < 128; count = count + 1) begin x <= x + y; y <= x; end initial count = 0; while (count < 128) begin.. count = count +1; end initial count = 0; repeat(128) begin.. count = count +1; end Must contain a number or a signal value, is evaluated once at the beginning

54 module mux4x1(out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0; reg out; or s0 or i0 or i1 or i2 or i3) begin case({s1, s0}) 2 d0: out = i0; 2 d1: out = i1; 2 d2: out = i2; 2 d3: out = i3; endcase endmodule

55 Example: 1 sec blinking LED module sec (input CLOCK_50, output reg [8:0] LEDG); integer count=0; initial LEDG[0]=1'b0; CLOCK_50) begin count=count+1; if(count == 50_000_000) begin count=0; if(ledg[0]) LEDG[0]=1'b0; else LEDG[0]=1'b1; end end endmodule

56 VHDL-AMS

57 Is derived from VHDL ((IEEE standard ). Includes mix-signal extensions (AMS) to define analogic and mix signal systems (IEEE ). Code example: Describing a diode in VHDL-AMS

58 VHDL_AMS papers in IEEE Xplore !!

59 Entity VHDL-AMS Basic tructure Describes the interface of a physical device or system Specifies the inputs and outputs of the model (ports) Can specify the input parameters of the model (A =, B =, C =..) Architecture Describes the model Can have not only analogic signals (continuous) but also digital ones (discrete) Exemple: DC/DC convertor modeling Components (R, L, C, Diode, Switch, opamp, etc) Digital components modeling from the modulation circuit Defining the specifications of the power converter Input/Output Voltage, Power Operating mode (CCM, DCM, Current or Voltage mode) Current specifications Commutation frequency Load/line regulation

60 VHDL-AMS Digital Modeling

61 ANEXE SystemC CAD development tools example (Computer Aided Design)

62 SystemC SystemC is a library of classes developed for C++. Is used for electronic systems design SystemC library : assures parallel work (needed for hardware systems) Clocks (time) Hardware data types (bit vectors, 4-valued logic, fixed-point types, arbitrary precision integers) Modules, ports, signals (for hierarchies)

63 SystemC - synthesizable OR gate example #include "systemc.h" SC_MODULE(or_gate) { sc_in<sc_bit> a; sc_in<sc_bit> b; sc_out<sc_bit> c; a b c OR_GAT E Celoxica SystemC compiler void prc_or_gate() { c=a b; } SC_CTOR(or_gate) { SC_METHOD(prc_or_gate); sensitive << a << b; } };

64 Synthesis and compilation flow Synthesizab le subset Launch your executable (simulator) Celoxica agility synthesize r Quartus II Verilog/edif Rest of code (testbenches, SW code) Syste mc library Visual C++ executable Verilog file is used, compiled with Celoxica Agility and Quartus II software Visual C++ compiler along SystemC library The system is simulated by execution in the command window (command prompt)

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67 Quartus from Altera = ISE Project Navigator from Xilinx

68 Simulation programs Behavioral Simulation: ModelSimis an industrial strength high level VHDL/Verilog simulator from Mentor Graphics. A light version of it (ModelSim XE II) is included with Xilinx's ISE WebPACK and a free license can be obtained from Xilinx. Dolphin SMASH: Multi-domain simulator, a version of SPICE with support for VHDL, VHDL-AMS and other simulation extensions - free download with limited abilities-. HAMSTER site: VHDL-AMS simulation environment -free download-. The Hamburg site for VHDL provides a wealth of information on high level behavioral modeling and synthesis tools. Behavioral Synthesis: FPGA vendors such as Xilinx and Altera have their own tools for synthesis from VHDL. For ASIC design, Synopsys and LeonardoSpectrum from Mentor Graphics can be used with the Tanner libraries to synthesize custom layout from VHDL.

69 Ansoft Simplorer - System Simulation Software for Multi-Domain Design Simplorer is a multi-domain system simulation software program. It is used for the design, modeling, analysis and optimization of high-performance systems that include electrical, thermal, electromechanical, electromagnetic, and hydraulic designs. These complex systems are commonly found in the automotive, aerospace/defense, and industrial automation industries. Simplorer provides a wide range of modeling techniques, analysis capabilities, and post processing. This enables the engineer to investigate system functionality, performance, and overall design verification. The result is a dramatic reduction in development time and cost, increased system reliability and system optimization. New in Simplorer v8 Next generation User Interface Advanced Model Editing Characterization tools Enhanced Spice and Pspice model import New component library concept Expanded VHDL-AMS functionality Enhanced Solver Performance Enhanced Transient Co-simulation with Maxwell New Dynamic Coupling with Maxwell/RMxprt/Q3D Extractor 3rd Party Co-simulation Coupling

70 VHDL-AMS mix-signal modeling language (analog/digital) but also for projects which include mixed technologies (Electric, Mecanic, Termic, Magnetic, etc.).

71 Simplorer example

72 Simplorer example Digital VHDL-AMS Modulator block modeling

73 References: [1] Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 Reconfigurable Computing [2] [3] [4] - Accolade VHDL Reference Guide - [5] Steve Chwirka - Applying VHDL-AMS and other Advanced Modeling Techniques [6] - [7]

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