Digital Design with VHDL. By Benjamin Abramov

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1 Digital Design with VHDL By Benjamin Abramov

3 Preface Very High Speed Hardware Description Language is a language for describing digital electronic systems. It was subsequently developed further under the auspices of the Institute of Electrical and Electronic Engineers IEEE and adopted in the form of the IEEE standard All rights reserved to Abramov B. 4

5 VHDL History The American Department Of Defense (DOD) signs a development contract with IBM, TI & Intermatics for a standard HDL The IEEE VHDL Standard is signed The first simulation programs in VHDL go out to market The Israeli Ministry Of Defense initiates projects using VHDL in some military companies VITAL 95 standard is signed to include detailed timing data in VHDL models. All rights reserved to Abramov B. 6

6 VHDL standards Standard VHDL Language Reference Manual in This first standard version of the language is often referred to as VHDL-87. Like all IEEE standards, the VHDL standard is subject to review every five years. Next version of the language, giving us VHDL-93. A seconds round of revision of the standard was started in That process was completed in The current version of the language VHDL All rights reserved to Abramov B. 9

7 VHDL Design Tools Simulator : functional testing. Provides a waveform diagram. The designer has to check whether the design indeed behaves as it is supposed to. Synthesizer: provides a net list design block diagram from the highest level (the whole design as one block) to the lowest level (single logic gates). Fitter: software tool that is used to configure a programmable chip according to special design. The received result will be a chip that we designed. All rights reserved to Abramov B. 20

8 Lexical Elements Identifiers. Identifiers are used to name items in a VHDL model. A basic identifier May only contain alphabetic letters ( A to Z and a to z ), decimal digits ( 0 to 9 ) and the underline character ( _ ) Must start with an alphabetic character May not include two successive underline characters. All rights reserved to Abramov B. 27

9 Lexical Elements (cont) Valid identifiers example. Count_enable; Shift_reg_8bit; Invalid identifiers example. 8bit_shift_reg; -- start with digit count enable; -- two successive underlines All rights reserved to Abramov B. 28

10 Lexical Elements (cont) Special symbols: VHDL uses a number of special symbols to denote operators, to delimit parts of language constructs and as punctuation. One character symbols: # & ( ) * + -,. / : ; < = > [ ] Two characters symbols must be typed next to each other, with no intervening space. => ** := /= >= <= <> VHDL is non case sensitive language! a and A, decoder and DEcoder are the same names. All rights reserved to Abramov B. 29

11 Lexical Elements (cont) Comments: A comments can be added to a line by writing two dashes together, followed by the comment text. For example: --this is example of comment All rights reserved to Abramov B. 30

12 Lexical Elements (cont) Reserved words: abs disconnected label package sla access downto library port sll after else linkage postponed sra alias elsif literal procedure srl all end loop process subtype and entity map protected then architecture exit mod pure to array file nand range transport assert for new record type attribute function next register unaffected begin generate nor reject units block generic not rem until body group null report use buffer guarded of return variable bus if on rol wait case impure open ror when component in or select while configuration inertial others severity with constant inout out shared xnor is signal xor All rights reserved to Abramov B. 31

15 Entity The first basic building block in VHDL is entity. Entity describes the boundaries of the logic block. The entity part provides system interface specification. All rights reserved to Abramov B. 34

16 Entity (cont) Entities in VHDL can describe different complexity leveled systems: Gates Discrete components (multiplexor,decoder ). Complex digital designs as controllers and processors (DMAC, Pentium IV, 68000). A full system (PCI card, motherboard, ). Each of these will be described by their outer world interface: X y AND GATE z In 0 In 1 In2 MUX 4-1 In3 s1s0 All rights reserved to Abramov B. 35

17 Entity (cont) Entity Parameters Connections The entity part is generally comprised of two elements: Parameters of the system as seen from the outside (such the bus width or maximum clock frequency) - generics Connections that are transferring information to and from the system (system s inputs and outputs) - ports All rights reserved to Abramov B. 36

18 Entity (cont) Its ports and its generics are declared within the entity. Syntax: entity entity_name is generic(generic_list); port(port_list); end entity entity_name; optionally optionally All rights reserved to Abramov B. 37

20 Entity (cont) We call the module frequency_divider entity, and the inputs and outputs are ports. entity frequency_divider is port ( rst : in bit; sel : in bit_vector(1 downto 0); freq_in : in bit; freq_out : out bit ); end entity frequency_divider; All rights reserved to Abramov B. 39

22 Entity (cont) A buffer mode port behaves in the similar way to an inout mode port, in that the port can be both read and assigned in the entity or block. The source of a buffer port determines the driving value of the port in the normal way. However, when the port is read, the value read is the driving value. All rights reserved to Abramov B. 41

28 Boolean (cont) The relational operators equality ( = ) and inequality ( /= ) can be applied to operands of any types, including the composite types. For example: 10=10; 010 = 010 ; 3 ns = 3 ns; all yield the value true All rights reserved to Abramov B. 48

30 Boolean (cont) The relational operators less-than ( < ), less-than or equal-to ( <= ), greater-than ( > ), greater-than or equal-to ( >= ), can only be applied to values of types that are ordered, including all of the scalar types. As with the equality and inequality operators, the operands must be of the same type, and result is a Boolean value. All rights reserved to Abramov B. 50

32 Bit Since VHDL is used to model digital systems, it is useful to have a data type to represent bit values. The predefined enumeration type bit serves this purpose. It is defined as type bit is ( 0, 1 ); All rights reserved to Abramov B. 52

33 Bit (cont) The logical operators for Boolean values can also be applied to values of type bit, and they produce result of type bit. The 0 corresponds to false, and 1 to true. 0 and 1 = 0 ; 1 or 0 = 1 ; The operands must still be of the same type. All rights reserved to Abramov B. 53

34 Bit (cont) The difference between types Boolean and bit is that values are used to model abstract conditions,whereas bit value is used to model hardware logic level. Thus, 0 represents a low logic level and 1 represent a high logic level. Note: Logical values for object of the type bit must be written in quotes my_bit<= 1 ; All rights reserved to Abramov B. 54

35 Bit Vector The bit_vector type is predefines as standard one-dimensional array type with each element being of type bit. The bit_vector type is an unconstrained vector of elements of the bit type. The size of a particular vector is specified during its declaration. The way the vector elements are indexed depends on the defined range, and can be either ascending or descending. All rights reserved to Abramov B. 55

36 Bit Vector (cont) Little endian: (high downto low) where high>=low my_vector : bit_vector(7 downto 0); Defined bus of 8 bit width and bit with index 7 is MSB bit with index 0 is LSB (descending range). Big endian: (low to high) where high>=low your_vector : bit_vector(0 to 7); Defined bus of 8 bit width and bit with index 7 is LSB bit with index 7 is LSB (ascending range). Note! The first bit and last bit index numbers define the number of bits in the vector (i.e. high -low + 1). Little endian form is preferred!!! All rights reserved to Abramov B. 56

37 Bit Vector (cont) msb register lsb If bit number 7 is msb, then its is declared in VHDL as bit_vector(7 downto 0) and the decimal value of the register is 188. If bit number 0 is msb, then its is declared in VHDL as bit_vector(0 to 7) and the decimal value of the register is 61. All rights reserved to Abramov B. 57

38 Bit Vector (cont) Assignment to an object of bit_vector type can be performed using single element of array (by index), concatenation, aggregates, slices or any combination of them. Logical value for objects of bit_vector type must be written in double quotes. my_bit_vector <= 1001 ; All rights reserved to Abramov B. 58

39 Bit Vector (cont) A slice is a part of a vector accessed by a range clause vec(high downto low) or vec(low to high) indexes cannot go out of bounds of original declaration range direction must be the same as the original vector a single index is use to access a single bit e.g. vec(4); All rights reserved to Abramov B. 59

40 Integer In VHDL, integer type used for the whole numbers. An example of an integer type is the predefined type integer, which includes all whole numbers re-presentable on a particular host computer. integer from (-(2**31) + 1) to ((2 **31) 1). All rights reserved to Abramov B. 60

41 Integer (cont) Each integer in VHDL represented by synthesizer like bus. my_int : integer range 15 downto 0; -- declared range 4 bit; my_int : integer range 10 downto 0; -- declared range 4 bit!!! When integer range not declared, then by default the range is 32 bit. port( ); my_int : in integer ; -- range 32 bit All rights reserved to Abramov B. 61

42 Integer (cont) An integer type can be defined either in ascending or descending range. my_int : integer range 15 downto 0; -- descending range 4 bit; my_int : integer range 0 to 15; --ascending range 4 bit The operations that can be performed on values of integer types include the familiar arithmetic operations. It is an error to assign to an integer object a value, which is from outside its range! All rights reserved to Abramov B. 62

43 Integer (cont) Subtypes natural and positive are predefined subtypes of integer. natural >=0; positive >=1; subtype natural is integer range 0 to integer high; subtype positive is integer range 1 to integer high; All rights reserved to Abramov B. 63

44 Integer (cont) Use Integers with Care!!! Synthesis tools create a 32-bit wide resources for unconstrained integers Do not use unconstrained integers for synthesis signal Y_int,A_int, B_int : integer ; Y_int <= A_int + B_int ; Specify a range with integers signal A_int,B_int: integer range -8 to 7; signal Y_int : integer range -16 to 15 ; Y_int <=A_int + B_int ; Recommendation: Use integers only as constants or literals Y_uv <=A_uv + 17 ; All rights reserved to Abramov B. 64

46 Architecture (cont) The secondary unit in the library is architecture. Syntax: architecture arc_entity_name of entity_name is architecture declaration area begin concurrent statements end architecture arc_entity_name; All rights reserved to Abramov B. 66

48 Architecture (cont) architecture arc_entity_name of entity_name is component component_name is generic(generic_list); port (port_list); endcomponent component_name ; type some_type; subtype subtype_name is base_type range range_constrain; constant constant_name : type :=value; signal signal_name : type; attribute middle : integer; attribute middle of signal_name: signal is signal_name'length/2; alias my_alias : std_logic_vector(7 downto 0) is my_bus(31 downto 24); begin All rights reserved to Abramov B. 68

49 Architecture (cont) Items declared in the architecture are visible in any process or block within it. An architecture can contain mix of component instances, processes or other concurrent statements. An entity can have one or more architectures. (Which one is used depends on the configuration) An architecture cannot be analyzed unless the entity it refers to exists in the same design library. The architecture contents starts after the begin statement. This is called the dataflow environment. All statements in the dataflow environment are executed concurrently!!! Assignment of a value to a port (signal) is done with the <=. All rights reserved to Abramov B. 69

50 Architecture (cont) architecture arc_parity_check of parity_check is begin parity_bit <=((din(7) xor din(6)) xor (din(5) xor din(4))) xor ((din(3) xor din(2)) xor (din(1) xor din(0))); end architecture arc_parity_check; All rights reserved to Abramov B. 70

52 Signal If we need a wire to transport data from one element of the design to another, we call it signal. signal Signals are declared at the architecture before BEGIN. Declaration example: SIGNAL my_signal: BIT; All rights reserved to Abramov B. 72

53 Signal (cont) Signals are the primary object describing a hardware system and are equivalent to wires. Represent communication channels among concurrent statements of system s specification. Signals and associated mechanisms of VHDL ( signal assignment statements, resolution function, delays, etc.) are used to model inherent hardware features such as concurrency, inertial characters of signal propagation, buses with multiple driving sources, etc. All rights reserved to Abramov B. 73

54 Signal (cont) Each signal has a history of values and may have multiple drivers, each of which has a current value and projected future values. Signal can be explicitly declared in the declarative part of: Package declaration; signals declared in a package are visible in all design entity s using the package. Architecture: signal is visible inside the architecture only. Block: the scope of such signals is limited to the block itself; Subprogram (function and procedure); All rights reserved to Abramov B. 74

55 Signal (cont) The signals can be classified as either internal or external. External signals are signals that connect the system to the outside world, they form the system s interface (ports). Internal signals, which are not visible from the outside, are completely embedded inside the system and are part of its internal architecture, providing signals between internal circuits. All rights reserved to Abramov B. 75

57 Signal (cont) The architecture within signal declaration: architecture arc_full_adder of full_adder is --signal declaration signal sig1 : bit; signal sig2 : bit; signal sig3 : bit; begin s<= a xor b xor ci; co<= sig1 or sig2 or sig3 ; --signal assignment sig1<= a and b; sig2<= a and ci; sig3<= b and ci; end architecture arc_full_adder; All rights reserved to Abramov B. 79

58 Constant Used to holding a value that can not be changed during design description. Constants value is assigned during declaration Used for readability and modification reasons. Syntax: constant constant_name : type :=value; All rights reserved to Abramov B. 83

59 Constant (cont) constant byte_width : integer:=8; constant num_of_bytes : integer:=4; constant num_of_bits : integer:= num_of_bytes * bus_width; signal my_dword : bit_vector( (num_of_bits 1) downto 0); signal my_bus : bit_vector( (byte_width 1) downto 0); signal my_sig : bit_vector(15 downto 0); constant all_ones : bit_vector( 15 downto 0):=x ffff ; constant VCC : bit:= 1 ; constant GND : bit:= 0 ; my_sig <= all_ones; -- the constant used to set of default value All rights reserved to Abramov B. 84

60 Component Components: Previously coded,simulated, synthesized and placed in design library Structural VHDL: Possibility of creating hierarchical designs built from a set of interconnected components. Design refinement : Simplification of debugging process The smaller, less complex circuit, the easier debugging process Component representation: In terms of other, smaller components (structural VHDL) Logic expressions Using behavioural VHDL (mixed style coding) All rights reserved to Abramov B. 91

61 Component (cont) Structural VHDL: Entity implementation by specifying its composition from subsystems Structural architectural body system composed only of interconnected subsystems Elements of structural architecture: 1. Signal declaration 2. Component declaration -specification of external interface to component in terms of generic constants and ports. Component declaration uses the same name of component as entity of the component module. The same port declaration as module entity declared as component. 3. Component instantiation specifies usage of module in design All rights reserved to Abramov B. 92

62 Hierarchical Project (cont) The port list must define the name, the mode, and the type of each port on the component. component half_adder is port( a : in std_logic; b : in std_logic; s : out std_logic; co: out std_logic ); end component half_adder ; All rights reserved to Abramov B. 93

63 Hierarchical Project (cont) A component declaration doest not define the entity-architecture pair to be bound to each instance, or even the ports on the entity. In an architecture, components must be declared before the begin statement: All rights reserved to Abramov B. 94

64 Hierarchical Project (cont) architecture arc_hierarchy_design of hierarchy_design is --signals and others resources of architecture component half_adder is port( a : in bit b : in bit; s : out std_logic; co: out std_logic ); end component half_adder ; begin --the architecture contents end architecture arc_hierarchy_design; All rights reserved to Abramov B. 95

66 Hierarchical Project (cont) entity half_adder is port( a : in std_logic; b : in std_logic; s : out std_logic; co: out std_logic ); end entity half_adder; architecture arc_half_adder of half_adder is begin s<= a xor b; co<= a and b; end architecture arc_half_adder; All rights reserved to Abramov B. 97

67 Hierarchical Project (cont) entity full_adder is port( a : in std_logic; b : in std_logic; ci: in std_logic; s : out std_logic; co: out std_logic ); end entity full_adder; All rights reserved to Abramov B. 98

68 Hierarchical Project (cont) architecture arc_full_adder of full_adder is component half_adder is port( a : in std_logic; b : in std_logic; s : out std_logic; co: out std_logic ); end component half_adder ; signal co1,co2 : std_logic; signal a_xor_b : std_logic; All rights reserved to Abramov B. 99

69 Hierarchical Project (cont) begin u1: half_adder -- instantiation by name port map( a => a, b => b, s => a_xor_b, co => co1); u2: half_adder -- instantiation by name port map( a => a_xor_b, b => ci, s => s, co => co2); co<=co1 or c02; end architecture arc_full_adder; All rights reserved to Abramov B. 100

70 Hierarchical Project (cont) Rules: The instance label is compulsory. The component name must match the relevant component declaration. The association list defines which local signals connect to which component ports. The instantiation by name, where ports are explicitly referenced and order is not important through it s preferred. The instantiation by name are the pairs of signals where each pair consists of two parts: The left part of the expression serve as name of port of the relevant component The right part of the expression serves as name of connected signal (or port of other component) All rights reserved to Abramov B. 101

71 Hierarchical Project (cont) The alternative is named association instantiation by position. The signals are connected up in the order in which the port were declared. For example : u2: half_adder port map (a_xor_b, ci, s, co2); This way of describe is more compact, but not readably. All rights reserved to Abramov B. 102

73 Hierarchical Project (cont) In VHDL-93 standard, an entity-architecture pair may be directly instantiated, i.e. component need not declared. This is more compact, but not readably. architecture arc_full_adder of full_adder is signal co1,co2 : std_logic; signal a_xor_b : std_logic; begin u1: entity work.half_adder(arc_1) port map(a,b,a_xor_b,co1); u2: entity work.half_adder(arc_2) port map(a_xor_b,ci,s,co2); co<= co1 or c02; end architecture arc_full_adder; All rights reserved to Abramov B. 104

74 Self Work component fa is port ( a_in : in bit; b_in : in bit; c_in : in bit; c_out : out bit; s_out : out bit); end component fa; architecture arc_ripple_adder4 of ripple_adder4 is --component declaration comes here signal c : bit_vector(2 downto 0); begin fa0: fa port map (a_in =>a(0),b_in=>b(0),c_in=>c_in_r, c_out=>c(0),s_out=>s(0)); fa1: fa All rights reserved to Abramov B. 105

77 Data Assignment For assignment VHDL uses the combination of symbols <= An assignment to a port defines a driver to that port. A standard port has only one source (driver). Assignment can t be done between different types! All rights reserved to Abramov B. 116

78 Data Assignment (cont) Examples: my_sig,any_sig : bit; my_int : integer range 15 downto 0; my_boolean : boolean; my_bus, any_bus : bit_vector(15 downto 0); my_sig<= 1 ; any_sig<=my_sig; -- any_sig= 1 my_int<=12; my_int<= 30; --wrong, to large value, over the range my_boolean<=true; my_bus<= ; my_bus(15 downto 8)<= x ff ; -- now my_bus is ; my_bus(0)<=my_sig; --now my_bus is ; any_bus<=my_bus; All rights reserved to Abramov B. 117

79 Data Assignment (cont) For bus assignment VHDL supports two different forms of assignment: aggregate and concatenation. Aggregate is a grouping of values in order to form an array. signal a,b,c,d : bit; nibble : bit_vector(3 downto 0); a<= 1 ; b<= 0 ; c<= 1 ; d<= 0 ; All rights reserved to Abramov B. 118

82 Data Assignment (cont) Positional association where the values are associated with elements from left to right. nibble<=( 0, 1, 0, 1 ); -- direct assignment in positional association. --nibble= 0101 Named association where elements are explicitly referenced and order is not important. nibble<=(2=>a,1=> b,0=>d,3=>c); -- nibble= 1100 All rights reserved to Abramov B. 121

83 Data Assignment (cont) With positional association, elements may be grouped together using the (pipe) symbol or a range. The keywords others may be used to refer to all elements. nibble<= (3 2 => 1, others=> 0 ); -- nibble = 1100 ; nibble <=(3 downto 1 => 0,0=> 1 ); -- nibble = 0001 ; nibble<=(others=> 0 ); --nibble= 0000 ; All rights reserved to Abramov B. 122

84 Data Assignment (cont) Another kind of aggregate is grouped assignment, i.e. assigning value to a number of elements of the same type: signal a,b,c,d : bit; (a,b,c,d)<= bit_vector (x 5 ); Equivalent assignment is : a<= 0 ; b<= 1 ; c<= 0 ; d<= 1 ; All rights reserved to Abramov B. 123

85 Data Assignment (cont) Aggregate example: signal A : bit_vector(7 downto 0); signal Asel: bit; We want to build the following circuit: The elegant deciding of this task by using aggregate looks so: signal Asel_vector: bit_vector(7 downto 0); Asel_vector<=(others=>Asel); T<=A and Asel_vector; All rights reserved to Abramov B. 124

86 Data Assignment (cont) Concatenation The concatenation operator (denoted as &) composes two onedimensional arrays into one larger array of the same type. my_bus : bit_vector(7 downto 0); nibble <=a & b & c & d; -- nibble= 1010 ; my_bus<= nibble(2 downto 1) & nibble(0) & nibble(3) & 0010 ; All rights reserved to Abramov B. 125

87 Data Assignment (cont) Constant values my_bus : bit_vector(7 downto 0); your_bus : bit_vector(5 downto 0); my_bus<= ; --binary value by default your_bus<=b ; --explicit binary value my_bus<= 0111_0101 ; --binary value with nibble separator your_bus<=o 67 ; --octal base of value presentation my_bus<=x a5 ; -- hexadecimal base Be Careful! b bit with value 0 o bits with value 0, same as B 000 x bits with value 0, same as B 0000 b 0 o 0 x 0 All rights reserved to Abramov B. 126

88 Self Work Write entity and architecture for the following design using signals. Use a. concatenation b. aggregate For constructing out_bus port. In_bus (2) (1) (0) sig3 sig5 sig4 y a sig1 (2) sig2 (1) Out_bus b sig6 (0) Smart_box All rights reserved to Abramov B. 128

89 Scalar types Next scalar type (integer type is first) is floating point type. A floating point type is approximation to the set of real numbers in a specified range. The precision of the approximation is not defined by the VHDL language standard, however it must be at least six decimal digits. The values may be within the range from -1E38 to +1E38. All rights reserved to Abramov B. 129

90 Scalar types (cont) A floating point type is declared using the syntax: floating_type_definition := range_constraint Some examples are: type signal_level is range to ; type probability isrange 0.0 to 1.0; All rights reserved to Abramov B. 130

91 Scalar types (cont) There is a predefined floating point type called real. The range of this type is implementation defined, though it is guaranteed that its value is within -1E38 to +1E38 range. Note: This type is not supported by synthesis tools. All rights reserved to Abramov B. 131

92 Scalar types (cont) The predefined physical type time is very important in VHDL, as it used extensively to specify delay. Its definition is implementation defined type time is range (2**31) to (2**31) ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; All rights reserved to Abramov B. 132

93 Scalar types (cont) VHDL provides a predefined function now that returns the current simulation time. pure function now return delay_length; delay_length is predefined subtype of the physical type time, constrained to non-negative time value. The time type is not supported by synthesis tools. It is used in test_benches and modeling. For example: if (now < 100 ns) then wait for (100 ns now); do something end if; All rights reserved to Abramov B. 133

94 Scalar types (cont) The character data type enumerates the ASCII character set. Nonprinting characters are represented by a three-letter name, such as NUL for the null character. Printable characters are represented by themselves, in single quotation marks, as follows: CHARACTER_VAR: character;... CHARACTER_VAR <= A ; All rights reserved to Abramov B. 134

95 Scalar types (cont) type character is ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', ' ', '}', '~', DEL); All rights reserved to Abramov B. 135

96 Scalar types (cont) Type character is an example of an enumeration type containing a mixture of identifiers and characters. Also, the characters '0' and '1' are members of both bit and character types. When '0'or '1' occur in a program, the context will be used to determine which type is being used. All rights reserved to Abramov B. 136

97 String The string data type is an unconstrained array of characters. string value is enclosed in double quotation marks as follows: signal header: string(1 to 10); header <= start_time ; The string index always starts from 1 and should be ascending only!!! All rights reserved to Abramov B. 137

98 User defined types The next type of VHDL is the user defined enumeration type. type my_type is (idle,st_start,st_1,st_2); This type is very useful to encoding state machine description. idle St_start St_2 St_1 All rights reserved to Abramov B. 138

99 User defined types (cont) Enumeration (literal values enumerated in a list) Example : type octal_digit is ( 0, 1, 2, 3, 4, 5, 6, 7 ); signal curr_digit : octal_digit;. curr_digit <= 2 ; All rights reserved to Abramov B. 139

100 User defined types (cont) Different enumeration types may include the same identifier as a literal (overloading). To illustrate this, consider the following declarations: type level is (unknown,low,medium,high); type temperature_level is (dangerously_high,high,ok); signal logic_level : level; signal temp_level : temperature_level; logic_level<=high; temp_level<=high; Note: logic_level /= temperature_level!!! These are different types!!! All rights reserved to Abramov B. 140

101 User defined types (cont) logic_level<=high; temperature_level<=high; Solution for this problem is qualified expression. We can distinguish between the common literal values by writing: logic_level<=level (high); All rights reserved to Abramov B. 141

102 User defined types (cont) The hardware implementation of the above types is bus. Width of bus depends on encoding style. For example : type my_type is (idle,st_start,st_1,st_2); State Encoding style name Binary Gray One_Hot idle St_start St_ St_ All rights reserved to Abramov B. 142

103 Resolved type (cont) STD_LOGIC and STD_ULOGIC can be assigned to each other: sl : std_logic; sul : std_ulogic; sl<=sul; --correct; sul<=sl; --correct; STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR can not be assigned to each other: slv : std_logic_vector(7 downto 0); sulv : std_ulogic_vector(7 downto 0); slv<=sulv; --wrong; sulv<=slv; --wrong; All rights reserved to Abramov B. 155

104 Resolved type (cont) The package STD_LOGIC_ARITH defines two new data types, Both arrays of STD_LOGIC: UNSIGNED => Positive only SIGNED => Positive and Negative ( twos compliment) All rights reserved to Abramov B. 156

105 Resolved type (cont) STD_LOGIC_ARITH containing arithmetic and logical operators for combinations of vectors and integers, along with useful function for converting between them using overloading. The STD_LOGIC_ARITH package do not contain arithmetic operation For std_logic_vectors and std_ulogic_vectors! Only for signed and unsigned types. All rights reserved to Abramov B. 157

106 Resolved type (cont) A : std_logic_vector(3 downto 0); B : unsigned(3 downto 0); b<=a +7; -- wrong b<=unsigned(a) +7; -- correct Casting a into an unsigned vector enable the adding operation. All rights reserved to Abramov B. 158

107 Resolved type (cont) STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED Includes a set of signed/unsigned arithmetic and conversion function for std_logic_vectors. These 2 packages are automatically performing casting into unsigned or signed types. Only one package STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED May be used for a specific design! Designs that have only positive vectors will use the std_logic_unsigned package. Designs that have positive and negative vectors will use the std_logic_signed package. All rights reserved to Abramov B. 159

108 Resolved type (cont) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comp is port (a,b : in std_logic_vector(7 downto 0); comp_out : out boolean); end entity comp; architecture arc_comp of comp is begin comp_out <= (a>b); end architecture arc_comp where: a=x 07 b=x 82 comp_out is false All rights reserved to Abramov B. 160

109 Resolved type (cont) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity comp is port (a,b : in std_logic_vector(7 downto 0); comp_out : out boolean); end entity comp; architecture arc_comp of comp is begin comp_out <= (a>b); end architecture arc_comp; where: a=x 07 b=x 82 comp_out is true All rights reserved to Abramov B. 161

110 Subtypes Subtype defines a new type contains parts of the values of a previously defined type. subtype subtype_name is base_type range range_constraint; Example ( user-defined subtypes): subtype nibble is std_logic_vector( 3 downto 0); subtype byte is std_logic_vector(7 downto 0); All rights reserved to Abramov B. 162

111 Subtypes (cont) A subtype object can be assigned to its base type object: subtype byte is std_logic_vector(7 downto 0); subtype short is integer range (2**16 1) downto 0; signal my_byte : byte; signal new_byte : std_logic_vector(7 downto 0); signal new_word : std_logic_vector(15 downto 0); signal my_natural : natural; signal my_int : integer; my_byte<= x ff ; new_byte<= my_byte; new_word<= my_byte & my_byte; -- concatenation my_int<= my_natural; my_natural<=my_int ; --WRONG All rights reserved to Abramov B. 163

114 Subtypes (cont) Pre-defined subtypes: subtype natural is integer range 0 to integer high;--(0 to MAX_INTEGER) subtype positive is integer range 1 to integer high;--(1 to MAX_INTEGER) subtype delay_lengt is time range 0 fs to time high; For modeling and simulations only!!! All rights reserved to Abramov B. 166

115 Type conversions Type conversions change an expression s type. The syntax of a type conversion is type_name( expression) The expression must evaluate to a value of a type that is convertible into type type_name. Type conversions can convert between integer types or between similar array types. Two array types are similar if they have the same length and have convertible or identical element types. All rights reserved to Abramov B. 167

116 Type conversions (cont) Type conversions can convert between integer types or between similar array types. Two array types are similar if they have the same length and have convertible or identical element types. Enumerated types are not convertible. All rights reserved to Abramov B. 168

117 Expressions and Operators Expressions in VHDL are much like expressions in other programming languages. An expression is a formula combining primaries with operators. Primaries include: names of objects literals, function calls parenthesized expressions. All rights reserved to Abramov B. 172

118 Expressions and Operators and or nand nor xor xnor not The above logical operators operate on values of types bit, boolean, std_ulogic, std_logic and also on one-dimensional arrays of these types. For array operands, the operation is applied between corresponding elements of each array, yielding an array of the same length as the result. All rights reserved to Abramov B. 173

120 Expressions and Operators Problem: Describe the 3 input NAND logic gate. D<= A nand B nand C; -- Syntax wrong!!! This is not logic gate NAND 3 D<= not (A and B and C); -- Correct All rights reserved to Abramov B. 175

121 Expressions and Operators Hierarchy with parentheses: parity_bit <= ((din(7) xor din(6)) xor (din(5) xor din(4))) xor ((din(3) xor din(2)) xor (din(1) xor din(0))); All rights reserved to Abramov B. 176

122 Expressions and Operators As your known, the logical operators of VHDL has binary operators: What is happening at this circuit? S<= A or B or (not B); If this function is degrades to constant, or the compiler builds it? All rights reserved to Abramov B. 177

123 Expressions and Operators Simple Arithmetic Expression Z <= A + B + C + D; The parser performs each addition in order, as though parentheses were placed within the expression as follows: Z <= ((A + B) + C) + D; All rights reserved to Abramov B. 178

125 Expressions and Operators If the arrival times of all the signals are the same, the length of the critical path of the expression equals three adder delays. The critical path delay can be reduced to two adder delays if you insert parentheses as follows: Z <= (A + B) + (C + D); All rights reserved to Abramov B. 180

127 Expressions and Operators The relational operators : = /= < <= > >= must have both operands of the same type, and yield boolean results. The equality operators (= and /=) can have operands of any type. For composite types, two values are equal if all of their corresponding elements are equal. The remaining operators must have operands which are scalar types or one-dimensional arrays of discrete types. All rights reserved to Abramov B. 182

128 Expressions and Operators The sign operators (+ and -) and the addition (+) and subtraction (-) operators have their usual meaning on numeric operands. The concatenation operator (&) operates on one-dimensional arrays to form a new array with the contents of the right operand following the contents of the left operand. It can also concatenate a single new element to an array, or two individual elements to form an array. The concatenation operator is most commonly used with strings. All rights reserved to Abramov B. 183

129 Expressions and Operators entity adder is port( a : in integer range 31 downto 0; b : in integer range 31 downto 0; c : out integer range 63 downto 0 ); end entity adder; architecture arc_adder of adder is begin c<= a + b; end architecture arc_adder; All rights reserved to Abramov B. 184

130 Expressions and Operators entity bus_conc is port( ); end entity bus_conc ; a : in std_logic_vector (7 downto 0); b : in std_logic_vector (7 downto 0); c : out std_logic_vector (15 downto 0) architecture arc_ bus_conc of bus_conc is begin c<= a & b; end architecture bus_conc ; All rights reserved to Abramov B. 185

131 Expressions and Operators The absolute value (abs) operator works on any numeric type. entity alarm is port( temp_level : in integer; critical _level : in integer; alarm_sig : out boolean ); end entity alarm; architecture arc_ alarm of alarm is begin -- the temperature should be in the range from critical_level to +critical_level alarm_sig <= ( (abs temp_level) >= critical_level); endarchitecture arc_ alarm; All rights reserved to Abramov B. 186

132 Expressions and Operators The multiplication (*) and division (/) operators work on integer, floating point and physical types (time for example). Be careful!!! The multiplication and division operations are source of hardware overhead. The synthesis tools supports division operation only for constants (one from two operands). All rights reserved to Abramov B. 187

133 Expressions and Operators The modulus (mod) and remainder (rem) operators only work on integer types. The exponentiation (**) operator can have an integer or floating point left operand, but must have an integer right operand. A negative right operand is only allowed if the left operand is a floating point number. All rights reserved to Abramov B. 188

134 Expressions and Operators A mod B = A B * N (in which N is an integer) the sign of (A mod B) is the same as the sign of B abs (A mod B) < abs (B) c<= (c + 1) mod 16 ; -- c would never be more then 15 6 mod mod mod (-4) (-6) mod For synthesis the modulo operator supports when the right operand is 2**n All rights reserved to Abramov B. 189

135 Expressions and Operators The remainder operation is defined such that the relation: a=(a/b)*b +(a rem b) or (a rem b)= a (a/b)*b and abs (a rem b)< abs (b), The result of the rem operator has the sign of its first operand, while the result of the mod operators has the sign of the second operand. 6 rem rem rem (-4) -- 2 (-6) rem For synthesis the remainder operator supports when the right operand is 2**n All rights reserved to Abramov B. 190

136 Expressions and Operators Typical using of power operator by integer range declaration entity mul is port( a : in integer range ((2**8) 1) downto 0; b : in integer range ((2**8) 1) downto 0; res : out integer range ((2**16) 1) downto 0 ); end entity mul; architecture arc_mul of mul is begin res<= a * b; end architecture arc_mul; All rights reserved to Abramov B. 191

138 Expressions and Operators VHDL-93 has a wide set of shift operators. The table bellow list the shift operators. Name sll srl sla sra rol ror Operation Shift left logical Shift right logical Shift left arithmetic Shift right arithmetic Rotate left logical Rotate right logical All rights reserved to Abramov B. 193

139 Expressions and Operators The shift operators are defined for the one-dimensional array with the elements of type bit. For the shift operator an array is the left operant L and the integer is the right operand R. The right operand R represents the number of position the left operant L should be shifted. As the result of shifting, the value of the same type as the left operand is returned. All rights reserved to Abramov B. 194

140 Expressions and Operators signal source : bit_vector(3 downto 0); signal dest : bit_vector(3 downto 0); source<= 1011 ; dest<= source sll 1; -- dest= 0110 the 0 is inserted dest<= source srl 1; --dest= 0101 dest<= source sll 3; --dest= 1000 dest<= source sll 3; -- dest<= source srl 3 ( 0001 ) dest<= source sla 1; -- dest= 0111 the 1 is inserted dest<= source sra 1; --dest= 1101 dest<= source rol 1; --dest= 0111 dest<= source ror 1; --dest= 1101 All rights reserved to Abramov B. 195

141 Expressions and Operators The shift operators are defined for one-dimensional array with the elements of type bit (bit_vector) However it also can be used for std_logic_vector, but only along with type conversion function. signal source : std_logic_vector(3 downto 0); signal dest : std_logic_vector(3 downto 0); dest<= to_stdlogicvector(to_bitvector(source) sll 2); All rights reserved to Abramov B. 196

143 Expressions and Operators As we saw VHDL strictly demands conformity of the size of operands. This excessive severity can sometimes be an obstacle, for example at realization of addition operation. As is known at addition the size of result on one bit is more than the size of biggest from operands. How it is possible to overcome this contradiction? One of possible variants : signal a, b : std_logic_vector(n downto 0); signal sum : std_logic_vector((n+1) downto 0); sum<=( 0 & a) + ( 0 & b); All rights reserved to Abramov B. 198

144 Expressions and Operators Problem : perform the next operation -> A + B + cin Where A and B is two buses of 8 bit width and cin is carry input bit. Solution: signal temp_a, temp_b, temp_sum : std_logic_vector(9 downto 0); signal sum : std_logic_vector(8 downto 0); temp_a <= 0 & a & 1 ; temp_b <= 0 & b & cin; temp_sum <=temp_a + temp_b; sum <= temp_sum(9 downto 1); 0 a7 a6 a5 a4 a3 a2 a1 a0 1 0 b7 b6 b5 b4 b3 b2 b1 b0 cin Where each node of the scheme is relevant bit of temp_sum All rights reserved to Abramov B. 199

146 Topic Three Process.207 Wait statements..217 Combinatorial Process 225 Synchronous Process.239 Sequential Statements 255 NULL Statements.301 Processes Guidelines.303 Behavioral Description.307 Wait statements All rights reserved to Abramov B. 202

Processes Process a behavioral region in the architecture were

150 Processes Syntax of process declaration: label: process ( sensitivity list) is --declaration of process resources begin sequential statements; end process label; All rights reserved to Abramov B. 206

151 Processes (cont) The process declarative part defines local items for the process and may contain declaration of: subprograms types subtypes constants variables files aliases use clauses groups All rights reserved to Abramov B. 207

153 Processes (cont) Asynchronous processes: describe a combinatorial logic hardware (muxes,decoders,encoders,arithmetic devices). Synchronous processes: describe a clocked logic (FF,registers,shift registers,counters). All rights reserved to Abramov B. 209

154 Processes (cont) A process declaration may content optional sensitivity list. The list contains identifiers of signals to which the process is sensitive. A change of a value of any those signals causes the suspended process to resume. Sensitivity list and explicit wait statements may not be specified in the same process. The process description style with sensitivity list is preferable for synthesis. All rights reserved to Abramov B. 210

156 Processes (cont) Process activation and suspension may be controlled via the wait statement: process begin warning_level<= ( curr_value=critical_value); wait on curr_value,critical_value; end process; All rights reserved to Abramov B. 212

157 Wait statements The wait statement is a statement that causes suspension of a process or a procedure. Syntax: wait; wait on signal_list; wait until condition; wait for n time_units; All rights reserved to Abramov B. 213

158 Wait statements (cont) The wait statement suspends the execution of the process or procedure in which it is specified. Resuming the process or procedure depends on meting the condition(s) specified in the wait statement. There are three types of conditions supported with wait statements: sensitivity clause, condition clause, and timeout clause. The most often used is the sensitivity clause. A sensitivity list defines a set of signals to which the process is sensitive and causes the process to resume. Example: signal S1, S2 : std_logic; process begin wait on S1, S2; end process; All rights reserved to Abramov B. 214

159 Wait statements (cont) If a process does not contain a sensitivity list, then an implicit sensitivity list is assumed, one which contains all the signals that are present in that condition. If a process is resumed but no condition is met, then the process will not execute any other statements. wait until enable = '1'; this is equivalent to: loop wait on enable; exit when enable = '1'; end loop; All rights reserved to Abramov B. 215

160 Wait statements (cont) The second type of a condition supported with the wait statement is the condition clause. A process is resumed when the logical condition turns true due to a change of any signal listed in the condition. The timeout clause defines the maximum time interval during which the process is not active. When the time elapses, the process is automatically resumed. Example : wait for 50 ns; A process containing this statement will be suspended for 50 ns. All rights reserved to Abramov B. 216

161 Wait statements (cont) A single wait statement can have several different conditions. In such a case the process will be resumed when all the conditions are met. Example : process begin wait on a, b until clk = '1';... end process; The process is resumed after a change on either a orb signal, but only when the value of the signal clk is equal to '1'. All rights reserved to Abramov B. 217

162 Wait statements (cont) process begin wait until a /= b for 4 us;... end process; The process is resumed when 4 us delay is ended, or after a change of either a or b signal, when a is not equal to b. All rights reserved to Abramov B. 218

163 Wait statements (cont) The syntax of the wait statement allows to use it without any conditions. Such a statement is equivalent to wait until true, which suspends a process forever and will never resume. While in simulation of normal models this is a disadvantage, this particular feature of a wait statement is widely used in testbenches. The followed example shows an example of a testbench section. process is begin G0 <= '0' ; waitfor 100 ns; wait until clk event and clk= 1 ; G0 <= '1' ; wait until clk event and clk= 1 ; G0 <= '0' ; wait; end process ; All rights reserved to Abramov B. 219

164 Wait statements (cont) Important notes: The wait statement can be located anywhere between begin and end process. A process with a sensitivity list may not contain any wait statements. All rights reserved to Abramov B. 220

165 Processes (cont) Process activation and suspension may be controlled via the wait statement or alternatively by sensitivity list process begin warning_level<= ( curr_value=critical_value); wait on curr_value,critical_value; end process; process ( curr_value, critical_value )is begin warning_level<=(curr_value=critical_value); end process; All rights reserved to Abramov B. 221

167 Processes (cont) concurrent sequential sequential architecture arc_sample of sample is begin P1: process (Rst, Clk) begin... end process P1; P2: process (Rst, Clk) begin... end process P2; end architecture arc_sample; All rights reserved to Abramov B. 223

169 Processes (cont) Acceptable VHDL code! architecture arc_test of test is begin and_gate:process(a,b,c,d) is begin sig<= a and b; sig<=c and d; end process and_gate; end architecture arc_test; All rights reserved to Abramov B. 225

170 Processes (cont) Decoder behavioral with multiple assignment signal din : std_logic_vector( n downto 0); signal dout: std_logic_vector(((2**din length)-1) downto 0); begin decoder : process (din) is begin dout <= (others => 0 ); dout (conv_integer (din)) <= 1 ; end process decoder ; All rights reserved to Abramov B. 226

171 Processes (cont) Don t use the signal that driven by combinatorial process, for reading inside of this process. process (a, b, c) is begin temp<= a xor b; s<= temp xor c; end process ; If temp is used inside of the process, then temp should be included into sensitivity list, but if temp is signal from sensitivity list, it feeds itself!?? process (a, b) is begin temp<= a xor b; end process ; process (temp, c) is begin s<= temp xor c; end process ; All rights reserved to Abramov B. 227

172 Processes (cont) A combinatorial processes, aka asynchronous processes must have a sensitivity list containing all the signals which it reads ( inputs), and must always update the signals which it assigns ( outputs). A missing signal in the sensitivity list can lead to a transparent latch! All rights reserved to Abramov B. 228

173 Processes (cont) architecture arc_and_gate of and_gate is begin process (d) is begin sig<= c and d; end process; end architecture arc_and_gate; Signal c is not included into sensitivity list, therefore the process does not respond when c changes its value. So what get is the following circuit: All rights reserved to Abramov B. 229

174 Processes (cont) Another kind of uncompleted sensitivity list is when output values are not included into sensitivity list. process(a,b) is begin if(a=b) then Sig<=c; else Sig<=d; end if; end process; All rights reserved to Abramov B. 231

177 Processes (cont) Most commons mistakes in asynchronous processes: Uncompleted sensitivity list. Redundant signals included into sensitivity list. Redundant logic is described. All rights reserved to Abramov B. 234

178 Processes (cont) Synchronous process current output is sequenced by a clock (rising edge or falling edge) and depends on past inputs as well as current inputs. This has a memory (flip-flops, registers, counters, shift registers, state machines). Sensitivity list include only clock and asynchronous reset/preset All the logic must be assigned after clock edge ( rising or falling) All rights reserved to Abramov B. 235

179 Processes (cont) Clock change detecting: by event predefined attribute: clk event and clk= 1 -- rise detect clk event and clk= 0 -- fall detect by library functions: rising_edge(arg : std_logic) return boolean falling_edge(arg : std_logic) return boolean At simulation with type std_logic use of functions rising_edge and falling_edge is more preferable. All rights reserved to Abramov B. 236

180 Processes (cont) DFF with asynchronous reset (active high); entity dff is port( clk: in std_logic; rst : in std_logic; d : in std_logic; q : out std_logic ); end entity dff; All rights reserved to Abramov B. 240

181 Processes (cont) architecture arc_dff of dff is begin process(clk,rst) is begin if (rst= 1 ) then q<= 0 ; elsif rising_edge(clk) then q<=d; end if; end process; endarchitecture arc_dff; All rights reserved to Abramov B. 241

182 Processes (cont) DFF with synchronous reset (active high) process (clk) is -- only clock signal should be declared in the sensitivity list begin if rising_edge(clk) then if (rst= 1 ) then q<= 0 ; else q<=d; end if; end if; end process; All rights reserved to Abramov B. 242

183 Processes (cont) set_rst_dff:process(clk,set,rst) is begin if (rst= 0 ) then q<= 0 ; elsif (set= 0 ) then q<= 1 ; elsif rising_edge(clk) then q<=d; end if; end process set_rst_dff; All rights reserved to Abramov B. 243

184 Processes (cont) The typical errors of synchronous processes: Using different signals as clock instead of the global clock Both set and reset assigned to the same signal and can be active at the same time. Signal do not have a reset value. Two edges of clock are used in the process. Gated clock is created. More then one clock is used in a process. All rights reserved to Abramov B. 244

186 FF coding rules Mixed Synchronous and Asynchronous processes bad_style: process (clk, rst, ld, load_val) is begin if (rst= 0 ) then cnt <= 0; elsif rising_edge(clk) then cnt <= cnt + 1; elsif (ld= 1 ) then cnt <= load_val; end if; end process bad_style; Legal VHDL but non-deterministic synthesis result!!! All rights reserved to Abramov B. 250

187 FF coding rules Asynchronous load in synchronous process dangerous_style: process (clk, ld) is begin if (ld= 0 ) then cnt <= load_val; elsif rising_edge (clk) then cnt <= cnt + 1; end if; end process dangerous_style; Legal VHDL when load_val is constants value. Otherwise non-deterministic synthesis result!!! All rights reserved to Abramov B. 251

188 FF coding rules process (clk) is if rising_edge (clk) and (en= 1 ) then --Signal assignment clk_internal <= clk and en; process (clk_internal) is if risind_edge (clk_internal) then --Signal assignment Gated clocks are more complicated then this Gated clock is the source of clock skew Avoid them!!! All rights reserved to Abramov B. 254

190 FF coding rules Is the following a register or a latch? reg_or_latch_proc : process (clk) is begin if (clk= 1 ) then q<=d; end if; end process reg_or_latch_proc; All rights reserved to Abramov B. 256

191 FF coding rules Cannot be a latch since it has an incomplete sensitivity list Cannot be a register since has no clock edge specification Resolution : Synthesis tool should produce an error and not produce any results All rights reserved to Abramov B. 257

C-Based Hardware Design

C-Based Hardware Design LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples