Introduction to VHDL. Main language concepts

Transcription

1 Introduction to VHDL VHSI (Very High Speed Integrated ircuit) Hardware Description Language urrent standard is IEEE (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab support VHDL-93 D like syntax, strictly typed language, concurrent Feature rich language for modeling digital systems at system level down to gate level. Only a subset of the language is supported for synthesis. Only RTL VHDL code is synthesizable with most tools The goal with this course is not that you should learn the complete language. You should learn how to write RTL VHDL code, but also some behavioral stuff for test benches SMD098 omputation Structures Lecture 2 1 Main language concepts oncurrency VHDL can describe activities that are happening in parallel Structure, hierarchy VHDL allows to structure a design in a hierarchical manner Sequential statements VHDL also allows sequential execution of statements. Just like any other programming language Time VHDL allows modeling of time SMD098 omputation Structures Lecture 2 2

2 VHDL design units Entity declaration Specifies the interface of a design unit rchitecture body Describes the function of a design unit. n entity can have more than one architectures. onfiguration declaration Used to bind entity statements to particular architecture bodies. Primary design units Secondary design units entity ENT1 is }... }... end entity ENT1; Design entity (component) architecture RH3 of ENT1 is }... architecture RH2 of ENT1 is }... }... architecture RH1end of ENT1 architecture is RH3; }... }... end architecture RH2; }... end architecture RH1; configuration FG1 of ENT1 is }... end configuration FG1; ommon design data Package declaration Used to store a set of common declarations such as components, types, procedures and functions Package body Used to store the definition of functions and procedures declared in the package declaration package PKG1 is }... end package PKG1; package body PKG1 is }... end package body PKG1; SMD098 omputation Structures Lecture 2 3 Packages package MyPackage is subtype Byte is std_logic_vector(7 downto 0); constant ZeroByte : std_logic_vector(7 downto 0) := (others => 0 ); function IsZero( : Byte) return boolean; end MyPackage; package body MyPackage is function IsZero( : Byte) return boolean is if = ZeroByte then return true; return false; end IsZero; end MyPackage; ssume the package MyPackage has been compiled into a design library MyLib. The library clause makes the the name MyLib visible. The use clause imports all declarations in package MyPackage into the entity Foo library MyLib; -- library clasue use MyLib.MyPackage.all; -- use clasue entity Foo is... end Foo; Selective import of declarations library MyLib; use MyLib.MyPackage.Byte; entity Foo is... end Foo; SMD098 omputation Structures Lecture 2 4

3 Libraries and compilation VHDL libraries stores analyzed (compiled) VHDL design units Working library There is only one working library for a design. Design units are compiled into this library. No library or use clause is needed to make the design units visible. Resource library Unlimited libraries for a design. Must be referenced with library and use clauses. ModelSim commands reates the library work vlib work ompile design units in dder.vhd into library work vcom dder.vhd ompile design units in X.vhd into library MyLib vcom -work MyLib X.vhd ompilation order 1. Packages 2. Entities 3. rchitectures 4. onfigurations SMD098 omputation Structures Lecture 2 5 Data types (some of them) Enumeration data type: ontains a set of user defined values type MyBit is ( 0, 1 ); type Beer is (Pripps, Falcon, KeyBeer, Guiness); Integer data type: Defines a range of integer numbers. Default is a 32-bit integer type ountvalue is range 0 to 10; rray data type: type MyBitVector is array (natural range <>) of MyBit; -- unconstrained array type MyByte is array (natural range 7 downto 0) of MyBit; -- constrained array Record data type: type FloatType is record Sign : Mybit; Exponent : MyBitVector(7 downto 0); Fraction : MyBitVector(15 downto 0); end record; Subtype: subtype Byte is std_logic_vector(7 downto 0); SMD098 omputation Structures Lecture 2 6

4 Predefined types package STNDRD is type boolean is (false, true); type bit is ( 0, 1 ); type character is ( SII chars... ); type severity_level is (note, warning, error, failure); type integer is range to ; type real is range -1.0E308 to 1.0E308; type time is range to units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; subtype delay_length is time range 0 fs to time high; impure function now return delay_length; subtype natural is integer range 0 to integer high; subtype positive is integer range 1 to integer high; type string is array (positive range <>) of character; type bit_vector is array (natural range <>) of bit; type file_open_kind is ( read_mode, write_mode, append_mode); type file_open_status is ( open_ok, status_error, name_error, mode_error); attribute foreign : string; end STNDRD; SMD098 omputation Structures Lecture 2 7 Data objects onstant: an hold a single value of a given type constant Femton : integer := 15; Variable: an hold a single value of a given type, but different values can be assigned to the variable at different times using a variable assignment statement variable Dummy : bit; Signal: Holds a list of values, which include the current value, past value and a set of possible future values that are to appear on the signal. Future values can be assigned to the signal using the signal assignment operator signal Reg, RegB : std_logic_vector(7 downto 0); File: Refers to a system file and contains a sequence of values of a specified type. file TestVectorFile: text open read_mode is "stim.txt"; SMD098 omputation Structures Lecture 2 8

5 ttributes There are many predefined attributes defined in VHDL. Not all can be used for synthesis. ttributes not supported for synthesis either relate to timing or are not necessary to model the physical structure of logic. Some examples: clock event returns true if an event occurred on the signal clock signal : unsigned(3 downto 0) left returns 3 right returns 0 See text book for further information! SMD098 omputation Structures Lecture 2 9 The std_logic_1164 package The predefined type bit is defined as type bit is ( 0, 1 ); an not model, high impedance, don t cares etc. So in std_logic_1164 a new type, std_ulogic, is defined: type std_ulogic is ( U, -- Uninitialized X, -- Forcing Unknown 0, -- Forcing 0 1, -- Forcing 1 Z, -- High Impedance W, -- Weak Unknown L, -- Weak 0 H, -- Weak Don t care ); std_ulogic_vector is defined as type std_ulogic_vector is array ( natural range <> ) of std_ulogic; SMD098 omputation Structures Lecture 2 10

6 The resolved type: std_logic signal that has multiple drivers must be of a resolved type. std_ulogic is not resolved but std_logic is a resolved typed that is derived from std_ulogic. The resolved vector type is called std_logic_vector Resolution table for std_logic U X 0 1 Z W L H ( U, U, U, U, U, U, U, U, U ), -- U ( U, X, X, X, X, X, X, X, X ), -- X ( U, X, 0, X, 0, 0, 0, 0, X ), -- 0 ( U, X, X, 1, 1, 1, 1, 1, X ), -- 1 ( U, X, 0, 1, Z, W, L, H, X ), -- Z ( U, X, 0, 1, W, W, W, W, X ), -- W ( U, X, 0, 1, L, W, L, W, X ), -- L ( U, X, 0, 1, H, W, W, H, X ), -- H ( U, X, X, X, X, X, X, X, X ) -- - Driver 1 Driver 2 1 Z Resolution function 1 SMD098 omputation Structures Lecture 2 11 Functions in std_logic_1164 set of overloaded logic functions and conversion functions are defined in std_logic_1164. The logic functions are overloaded so they can be used for the std_logic and std_ulogic (and vector) types Logic functions: ND, NND, OR, XOR, XNOR, NOT onversion functions: To_bit, To_bitvector, To_StdULogic, To_StdULogicVector, ToStdLogicVector lso in the package, edge detecting functions: rising_edge() and falling_edge() The std_logic_1164 package does not contain any functions for arithmetic operations SMD098 omputation Structures Lecture 2 12

7 The numeric_std package In the IEEE synthesis package, numeric_std, the types unsigned and signed are defined. type unsigned is array (natural range <>) of std_logic; type signed is array (natural range <>) of std_logic; In the package a set of arithmetic functions are defined as well as conversion functions. Both std_logic_1164 and numeric_std will be used in the labs. You will see examples in the first lab. The source for the packages may be found in the appendix of the text book, and is also available as files in the ModelSim and Synplify installation directories. SMD098 omputation Structures Lecture 2 13 Type conversions Because VHDL is a strongly typed language type conversions are unavoidable. losely related types may be converted using the syntax: target_type_name(expression) Types that are not closely related need a type conversion function architecture Y of X is signal S : std_logic_vector(7 downto 0); signal, B : unsigned(7 downto 0); signal MyInt : integer; -- This will cause type error S <= B; -- Type conversion, target is a std_logic_vector S <= std_logic_vector(); -- The + operator is defined for unsigned, -- signed and integer in numeric_std B will result in unsiged since the -- operators are of unsigned type S <= std_logic_vector( + B); -- to_integer is a type conversion fucntion -- in numeric_std. Note that integer( + B) -- will result in type error. MyInt <= to_integer( + B); -- The + operator is overloaded in -- numeric_std. <= unsigned(s) + MyInt; end Y; SMD098 omputation Structures Lecture 2 14

8 The entity The entity specifies the interface of a design unit. May be seen as a black box description Entity name use ieee.std_logic_1164. all ; Library statement and use clause entity dder is, B : in std_ulogic_vector(3 downto 0); in : in std_ulogic; Sum : out std_ulogic_vector(3 downto 0); out : out std_ulogic); end dder; Port signal name Port mode Port type dder [3:0] B[3:0] Sum[3:0] out in SMD098 omputation Structures Lecture 2 15 Port modes Three most often used port modes: in out inout Entity Driver S Entity Driver I S Signal can not be read inside entity Port signal I Signal I can be read inside entity Port signal Mode out Mode out with internal signal I, The port signal S is assigned to the internal Signal I Entity Entity Driver S Driver S Driver Port signal Signal can be read inside entity Port signal Mode in Mode inout SMD098 omputation Structures Lecture 2 16

9 The architecture The architecture defines the contents of the black box Port declarations entity dder is end dder; Entity name rchitecture declarations rchitecture body architecture Demo of dder is end Demo; rchitecture name SMD098 omputation Structures Lecture 2 17 oncurrent statements The architecture body contains concurrent statements. Sequential statements are not allowed in the architecture body. use ieee.std_logic_1164. all ; B Y entity Test is, B : in std_logic; X, Y : out std_logic); end Test; X architecture oncurrent of Test is Two concurrent statements. Order is unimportant X <= xor B; with select Y <= B when 1, Z when 0, - when others ; Signal assignment operator end oncurrent; overs all cases SMD098 omputation Structures Lecture 2 18

10 Internal signals Internal signals can be declared in the declarative region of the architecture use ieee.std_logic_1164. all ; entity Test is, B : in std_logic; X, Y : out std_logic); end Test; B Int Y Signal declaration architecture Internal of Test is signal Int : std_logic; X Int <= xor B; X <= not Int ; Y <= Int and ; end Internal; Internal signal can be read and be assigned new values. X and Y is not readable! SMD098 omputation Structures Lecture 2 19 Processes and sequential statements use ieee.std_logic_1164. all ; entity Test is, B : in std_logic; X, Y : out std_logic); end Test; B 0 1 Y X Process label Process declarative region Process body architecture Proc of Test is P1: process (, B) -- signal declarations not allowed if = 1 and B = 0 then X <= ; Y <= 1 ; X <= B; Y <= 0 ; end if ; end process P1; end Proc; Sensitivity list Process is activated whenever an event occurs on signal or B Statements in the process body are executed sequentially! SMD098 omputation Structures Lecture 2 20

11 Multiple processes interact concurrently entity Test is, B : in std_logic; X, Y : out std_logic); end Test; B 0 1 Y architecture Proc of Test is signal Internal : std_logic; 0 1 X P1: process (, B) if = 1 and B = 0 then X <= ; Internal <= 0 ; X <= B; Internal <= 1 ; end process P1; P2 : process(, B, Internal) if Internal = 1 then Y <= ; Y <= B; end process P2; end Proc; Process 1 Process 2 Each process execute its statements sequentially. Each process execute when there is an event on one of the signals on its sensitivity list. This may cause an event on another signal that triggers another process SMD098 omputation Structures Lecture 2 21 oncurrent vs. sequential execution architecture oncurrent of Test is Y <= or B; Y <= and D; end oncurrent; architecture Sequential of Test is process (, B,, D) Y <= or B; Y <= and D; end process ; end Sequential; B D? Y Resolution function D Y Synplify will report errors! Multiple non-tristate drivers for net Y The signal is updated with the last value assigned to it signal that is assigned to within a process is not updated until the process is suspended. SMD098 omputation Structures Lecture 2 22

12 Sensitivity lists For a process that models combinational logic, the sensitivity list must be complete! What does this process model? process() Y <= or B or or D; Synplify will assume that the sensitivity list is complete. The function of the synthesized logic will not match the function of the VHDL model you simulated. SMD098 omputation Structures Lecture 2 23 Variables in processes variable is declared inside the process and is not visible outside the process. variable is updated immediately. Retains its value through the simulation Variable declaration process (, B,, D) variable Temp : std_logic; temp := 0 ; temp := temp xor ; temp := temp xor B; temp := temp xor ; temp := temp xor D; Y <= temp; end process ; D B Y SMD098 omputation Structures Lecture 2 24

13 ssigning values to arrays architecture assign of Examples is -- Initial value, not supported for synthesis signal Byte : std_logic_vector(7 downto 0) := " "; signal Word : std_logic_vector(15 downto 0); -- ssign a string literal Byte <= " "; -- Positional association Byte <= ( 1, 0, 1, 0, 1, 0, 1, 0 ); -- ssign hexadecimal value (octal is also supported) Byte <= X"0F"; -- Set all to ones Byte <= (others => 1 ); -- Named association Byte <= (7 6 => 1, others => 0 ); Byte <= (7 => 1, 4 => 1, 3 downto 1 => 0, others => 0 ); -- oncatenation Word <= X"FF" & Byte; -- Signextend Word(15 downto 0) <= (others => Byte(7)); Word(7 downto 0) <= Byte; end Examples; SMD098 omputation Structures Lecture 2 25 Event based simulation Simulation delta cycle Delta Signal Update Process Execution Time Delta "time" is orthogonal to simulation time dvance in time when no more processes are scheduled to execute at current simulation time SMD098 omputation Structures Lecture 2 26

14 Simulation - an example architecture sim of Test is signal, B,, D : std_logic := 0 ; signal S1, S2, Y : std_logic; <= 0 after 5 ns, 1 after 10 ns; B <= 1 after 5 ns; <= 0 after 5 ns, 1 after 10 ns; D <= 1 after 5 ns; S1 <= xor B; S2 <= xor D; Y <= S1 and S2; B S1 1 10ns 1 10ns Y 0 5ns 1 5ns 0 5ns 1 5ns B D end Sim; D S2 t (ns) B D S1 S2 Y U U U U SMD098 omputation Structures Lecture 2 27 ombinational feedback loops In a synchronous design combinational feedback loops should ( must ) be avoided. There are some rare exceptions though. ssume S = 0 and = 1. What will happen in simulation? Simulation will never advance in time! S <= S xor ; S ModelSim will report: # Iteration limit reached. Possible zero delay oscillation. See the manual. SMD098 omputation Structures Lecture 2 28

15 Structure, component instantiation entity Fulldder is, B, in : in std_logic; S, out : out std_logic ); end Fulldder; architecture logic of Fulldder is S <= xor B xor in; out <= ( and B) or ( and in) or (B and in); end logic; use ieee.std_logic_1164. all ; entity dder is, B : in std_logic_vector(3 downto 0); in : in std_logic; Sum : out std_logic_vector(3 downto 0); out : out std_logic); end dder; architecture Structure of dder is component Fulldder, B, in : in std_logic; S, out : out std_logic); end component ; signal Ripple : std_logic_vector(0 to 2); Bit0: Fulldder port map ( => (0), B => B(0), in => in, S => Sum(0), out => Ripple(0)); Bit1: Fulldder port map ( => (1), B => B(1), in => Ripple(0), S => Sum(1), out => Ripple(1)); Bit2: Fulldder port map ( => (2), B => B(2), in => Ripple(1), S => Sum(2), out => Ripple(2)); Bit3: Fulldder port map ( => (3), B => B(3), in => Ripple(2), S => Sum(3), out => out); omponent Instantiations omponent Declaration [3:0] B[3:0] in Bit3 Fulldder out B S in Bit2 Fulldder out B S in Bit1 Fulldder out B S in Bit0 Fulldder out B S in out Sum[3:0] end Structure; SMD098 omputation Structures Lecture 2 29 Generate and generic parameters Generic parameters and the generate statement allows scalable designs architecture InstGen of Main is component Scalabledder generic ( N : integer);, B : in std_logic_vector(n-1 downto 0); in : in std_logic; Sum : out std_logic_vector(n-1 downto 0); out : out std_logic); end component; 32Bitdder: Scalabledder generic map ( N => 32) port map ( => _i, B => B_i, in => in_i, Sum => Sum_i, out => out_i); end InstGen; use ieee.std_logic_1164. all ; entity Scalabledder is Generic parameter generic ( N : integer := 8); -- N > 0, B : in std_logic_vector(n-1 downto 0); in : in std_logic; Sum : out std_logic_vector(n-1 downto 0); out : out std_logic); end Scalabledder; architecture Structure of Scalabledder is component Fulldder, B, in : in std_logic; S, out : out std_logic); end component ; Generic parameter signal Ripple : std_logic_vector(0 to N-1); MainGen: for i in 0 to N-1 generate G1: if i = 0 generate Bit0: Fulldder port map ( => (0), B => B(0), LSB full adder in => in, S => Sum(0), out => Ripple(0)); end generate G1; G2: if (i > 0 and i<(n-1) ) generate BitI : Fulldder port map ( => (i), B => B(i), in => Ripple(i-1), S => Sum(i), out => Ripple(i)); end generate G2; G3 : if (i =(N-1)) generate BitHigh: Fulldder port map ( => (N-1), B => B(N-1), in => Ripple(N-2), S => Sum(N-1), out => out); end generate G3; MSB full adder Main generate loop Full adders between MSB and LSB end generate MainGen; end Structure; SMD098 omputation Structures Lecture 2 30

16 Some sequential statements SSERT, REPORT WIT IF SE NULL LOOP, NEXT, EXIT SMD098 omputation Structures Lecture 2 31 SSERT, REPORT hecks if a specified boolean expression is true during simulation. If it is not true an error message and a severity expression may be given. Not supported for synthesis, only useful for simulation assert false report "This is always reported!"; assert ctual = Expected report "Simulation error! ctual value is not equal to expected value" severity error; severity_level is defined in the standard package type severity_level is (note, warning, error, failure); ModelSim simulation options SMD098 omputation Structures Lecture 2 32

17 WIT process may be suspended by means of a sensitivity list. When a process have a sensitivity list it always suspends after executing the last sequential statement and then the signals that have been assign to new values are updated. The wait statement provides an alternative form for suspending a process. Only wait until is supported for synthesis but it should be avoided. -- Generate reset waveform process Reset <= 0 ; wait for 15 ns; Reset <= 1 ; wait; -- Generate pushbutton waveform process Spare_n <= 1 ; wait for 200 ns; Spare_n <= 0 ; wait for 8 ms; Spare_n <= 1 ; wait; -- Generate clock process lk <= 0 ; wait for 10 ns; lk <= 1 ; wait for 10 ns; -- pply stimulus on falling -- edge of clock process wait until lk = 0 ; <= Stimulus; end process -- Wait for an event on --, B or process wait on, B, ; X <= and b and ; SMD098 omputation Structures Lecture 2 33 IF - some examples if ount = 1 then OutPut <= 1 ; OutPut <= 0 ; if ount = 1 then := 10; elsif State = Idle then := 20; := 30; if = B then if = D then S <= 1 ; S <= 0 ; S <= 1 ; SMD098 omputation Structures Lecture 2 34

18 SE - some examples case PresentState is when Idle => Output <= 1 ; NexState <= S1; when S1 => Output <= 0 ; NexState <= S2; when S2 => Output <= 1 ; NexState <= S1; end case; case OPode is when "0000" "0001" "0010" "0011" => Result <= ; when "1000" "1001" "1010" "1011" "1100" "1101" "1110" "1111" => Result <= B; when "0100" "0101" => Result <= ; when others => -- ll possible cases must be covered null; -- do nothing end case; SMD098 omputation Structures Lecture 2 35 LOOP, NEXT, EXIT NEXT statement results in skipping the remaining statements in the current iteration of the loop. Execution resumes with the next iteration of the loop. EXIT statement jumps out of the loop := 0; for i in 0 to 10 loop := + B(i); end loop; for i in 0 to 10 loop next when i = 1; := + B(i); end loop; while > B loop B := B * 2; end loop; i := 0; loop i := i + 1; exit when i = 10; end loop; L1 : for i in 10 downto 0 loop -- Statements section 1 L2 : loop -- Statements section 2 next L1 when Done = 1 ; -- Statements section 3 end loop L2; -- statements section 4 end loop L1; When Done = 1 becomes true statements section 3 and 4 are skipped. Execution jumps to next iteration of L1. While loops are not supported for synthesis and the range needs to be statically defined SMD098 omputation Structures Lecture 2 36

19 Sub programs subprogram defines a sequential algorithm that performs a certain computation. re declared in packages or the declarative region of an architecture. Functions Executes in zero simulation time. Must not contain timing. Returns a single value Procedures May contain timing Returns zero or more values SMD098 omputation Structures Lecture 2 37 Example function rising_edge() in std_logic_1164 package std_logic_1164 is function rising_edge (signal s : std_ulogic) return boolean; end std_logic_1164; package body std_logic_1164 is function rising_edge (signal s : std_ulogic) return boolean is return (s event and (To_X01(s) = 1 ) and (To_X01(s last_value) = 0 )); end; end std_logic_1164; SMD098 omputation Structures Lecture 2 38

20 Example procedure package MyPackage is procedure MyProcedure ( signal, B : in bit; signal S : out bit); end MyPackage; package body MyPackage is procedure MyProcedure ( signal, B : in bit; signal S : out bit) is S <= xor B; end procedure; end MyPackage; alling the procedure MyProcedure(S1, S2, R2); -- Positional MyProcedure(S => R2, => S1, B => S2); -- By name SMD098 omputation Structures Lecture 2 39 Modeling combinational logic Simple Logic Multiplexers Encoders Priority encoders Decoders omparators rithmetic SMD098 omputation Structures Lecture 2 40

21 Simple logic For std(u)_logic you find the logic functions in ieee.std_logic_1164 and for unsigned and signed the corresponding functions are in ieee.std_numeric. architecture Examples of Logic is O1_vec <= _vec and B_vec; _vec[3:0] B_vec[3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] O2_vec[3:0] o2_vec[3:0] P1 : process(_vec, B_vec) O2_vec <= _vec and B_vec; end process P1; [3:0] O1_vec[3:0] with B select O1 <= 1 when 0, 0 when 1, - when others; B O2 O2 O2 <= not B; O1 P2 : process(_vec) variable temp : std_logic; temp := 0 ; for i in _vec range loop temp := temp xor _vec(i); end loop; O3 <= temp; end process P2; _vec[3:0] O1 [2] [3:0] P2.2_temp_3 [1] P2.1_temp_4 [0] O3 O3 P3 : process(, _vec) variable temp : std_logic_vector(3 downto 0); temp := ( others => ); [3:0] O3_vec <= temp and _vec; _vec[3:0] end process P3; end Examples; [3:0] [3:0] [3:0] O3_vec[3:0] O3_vec[3:0] SMD098 omputation Structures Lecture 2 41 architecture Examples of Muxes is M1 : process(, B,, D, Sel) if Sel = "00" then Y1 <= ; elsif Sel = "01" then Y1 <= B; elsif Sel = "10" then Y1 <= ; Y1 <= D; end process M1; Multiplexers Four ways of modeling a 4-1 multiplexer Y2 <= when Sel = "00" B when Sel = "01" when Sel = "10" D; M2 : process(, B,, D, Sel) case Sel is when "00" => Y3 <= ; when "01" => Y3 <= B; when "10" => Y3 <= ; when "11" => Y3 <= D; when others => Y3 <= - ; end case; with Sel select Y4 <= when "00", B when "01", when "10", D when "11", - when others; end Examples; B D Sel[1:0] Y SMD098 omputation Structures Lecture 2 42

22 Encoders Truth table for a 8-3 binary encoder Inputs Outputs Y2 Y1 Y n-1 Yn-1 n 2 inputs Binary Encoder Y1 Y0 n outputs SMD098 omputation Structures Lecture 2 43 architecture Logic1 of Encoder is P1: process() if = " " then Y <= "000"; elsif = " " then Y <= "001"; elsif = " " then Y <= "010"; elsif = " " then Y <= "011"; elsif = " " then Y <= "100"; elsif = " " then Y <= "101"; elsif = " " then Y <= "110"; elsif = " " then Y <= "111"; Y <= "---"; end process P1; architecture Logic2 of Encoder is P1: process() if = 1 then Y <= "000"; elsif = 2 then Y <= "001"; elsif = 4 then Y <= "010"; elsif = 8 then Y <= "011"; elsif = 16 then Y <= "100"; elsif = 32 then Y <= "101"; elsif = 64 then Y <= "110"; elsif = 128 then Y <= "111"; Y <= "---"; end process P1; end Logic2; architecture Logic3 of Encoder is Y <= "000" when = 1 "001" when = 2 "010" when = 4 "011" when = 8 "100" when = 16 "101" when = 32 "110" when = 64 "111" when = 128 "---"; 8-3 binary encoder use ieee.numeric_std.all; entity Encoder is : in unsigned(7 downto 0); Y : out unsigned(2 downto 0)); end Encoder; end Logic1; architecture Logic4 of Encoder is P1 : process() case is when " " => Y <= "000"; when " " => Y <= "001"; when " " => Y <= "010"; when " " => Y <= "011"; when " " => Y <= "100"; when " " => Y <= "101"; when " " => Y <= "110"; when " " => Y <= "111"; when others => Y <= "---"; end case; end process P1; architecture Logic5 of Encoder is end Logic3; architecture Logic6 of Encoder is P1 : process() Y <= "---"; L1: for i in 0 to 7 loop if = 2**i then Y <= to_unsigned(i, 3); end loop L1; end process P1; with select Y <= "000" when " ", "001" when " ", "010" when " ", "011" when " ", "100" when " ", "101" when " ", "110" when " ", "111" when " ", "---" when others; end Logic5; end Logic6; end Logic4; SMD098 omputation Structures Lecture 2 44

23 Priority encoders If two or more single bit inputs are at logic 1, then the input with highest priority will take precedence. Truth table for a 8-3 binary encoder Inputs Outputs Y2 Y1 Y0 Valid SMD098 omputation Structures Lecture 2 45 use ieee.numeric_std.all; entity PriEncoder is : in unsigned(7 downto 0); Y : out unsigned(2 downto 0); Valid : out std_logic); end PriEncoder; 8-3 priority encoder architecture Logic1 of PriEncoder is P1: process() Valid <= 1 ; if (7) = 1 then Y <= "000"; elsif (6) = 1 then Y <= "001"; elsif (5) = 1 then Y <= "010"; elsif (4) = 1 then Y <= "011"; elsif (3) = 1 then Y <= "100"; elsif (2) = 1 then Y <= "101"; elsif (1) = 1 then Y <= "110"; elsif (0) = 1 then Y <= "111"; Valid <= 0 ; Y <= "---"; end process P1; end Logic1; architecture Logic2 of PriEncoder is P1: process() variable Temp : integer; Valid <= 1 ; Temp := to_integer(); case Temp is when 128 to 255 => Y <= "111"; when 64 to 127 => Y <= "110"; when 32 to 63 => Y <= "101"; when 16 to 31 => Y <= "100"; when 8 to 15 => Y <= "011"; when 4 to 7 => Y <= "010"; when 2 to 3 => Y <= "001"; when 1 => Y <= "000"; when others => Y <= "---"; Valid <= 0 ; end case; end process P1; end Logic2; architecture Logic3 of PriEncoder is P1 : process() Y <= "---"; Valid <= 0 ; for i in 7 downto 0 loop if (i) = 1 then Y <= to_unsigned(i, 3); Valid <= 1 ; exit; end loop; end process P1; end Logic3; SMD098 omputation Structures Lecture 2 46

24 Decoders Truth table for a 8-3 binary decoder Inputs Outputs Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y n-1 Yn-1 n inputs 1 0 Binary Decoder Y2 Y1 Y0 n 2 outputs SMD098 omputation Structures Lecture binary decoder Two examples shown. See Smith pages for alternative VHDL models. use ieee.numeric_std.all; entity Decoder is : in unsigned(2 downto 0); Y : out unsigned(7 downto 0)); end Decoder; architecture Logic1 of Decoder is type TableType is array (0 to 7) of unsigned(7 downto 0); constant Table : TableType := ( " ", " ", " ", " ", " ", " ", " ", " ") ; Y <= Table(to_integer()); architecture Logic2 of Decoder is P1 : process() Y <= (others => 0 ); Y(to_integer()) <= 1 ; end process P1; end Logic2; end Logic1; SMD098 omputation Structures Lecture 2 48

25 Don t cares The don t care for std_logic is defined as -. So you might think that this will work fine... variable ddress : std_logic_vector(5 downto 0);... case ddress is when "-11---" =>... when "-01---" =>... when others =>... end case; but it doesn t! For instance the adress will match the others clause. Here is one solution: if (address(4 downto 3)="11") then... elsif (address(4 downto 3)="01") then Or you can use the "std_match" functions defined in the numeric_std package. if (std_match(address, "-11---") then... elsif (std_match(address, "-01---") then Extracted from comp.lang.vhdl FQ. SMD098 omputation Structures Lecture 2 49 omparators comparator compares two or more inputs. The output is a single bit. VHDL model of comparator use an if statement with an clause. use ieee.numeric_std.all; entity omparators is, B, : in unsigned(2 downto 0); Y1, Y2 : out std_logic); end omparators; architecture Logic of omparators is Equality and relational = /= < <= > >= P1 : process(, B) if < B then Y1 <= 1 ; Y1 <= 0 ; end process P1; P2 : process(, B, ) if ( < B) and (B > ) then Y2 <= 1 ; Y2 <= 0 ; end process P2; end Logic; [2:0] B[2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] Logical < P1_a < P2_un3_a not and or [2:0] Y2 P2_un2_a Y1 SMD098 omputation Structures Lecture 2 50

26 rithmetic The built-in operators for integer and real is shown in the box. numeric_std defines all the operators, except **, for the unsigned and signed types. Synthesis of arithmetic operators have its limitations. Synplify does not support the exponential operator, also the right argument for division, modulus and reminder must evaluate to a constant integer power of 2. Exponential Multiplication Division ddition Subtraction Modulus Reminder bsolute value ** * / + - mod rem abs Generally complex arithmetic models should be modeled structurally. See Smith chapter 9. The Xilinx oregenerator contains various arithmetic modules that are optimized for Xilnx FPGs. It is beyond the scope of this course to cover computer arithmetic in detail, but you should read chapter 9. If you want to learn more about computer arithmetic you can choose a mini project that deals with this subject. SMD098 omputation Structures Lecture 2 51 rithmetic use ieee.std_logic_1164. all ; use ieee.numeric_std. all ; entity rith is, B : in unsigned(7 downto 0); : in signed(7 downto 0); Y1, Y2 : out unsigned(15 downto 0); Y3, Y4, Y5, Y6, Y7, Y8 : out unsigned(7 downto 0)); end rith; architecture NoSynth of rith is Y1 <= * B; Y2 <= to_unsigned(to_integer()**2, 16); Y3 <= / B; Y4 <= + B; Y5 <= - B; Y6 <= mod B; Y7 <= rem B; Y8 <= unsigned( abs ()); end NoSynth; Not supported by Synplify SMD098 omputation Structures Lecture 2 52

27 dder with carry in and carry out use ieee.numeric_std.all; entity dder is, B : in unsigned(7 downto 0); in : in std_logic; Sum : out unsigned(7 downto 0); out : out std_logic); end dder; architecture RTL of dder is dd : process(, B, in) variable SumTemp : unsigned(8 downto 0); variable intemp : integer; if in = 1 then intemp := 1; intemp := 0; [7:0] SumTemp := ( 0 & ) + B + intemp; B[7:0] out <= SumTemp(8); Sum <= SumTemp(7 downto 0); in end process dd; end RTL; The width of the result from + operator in numeric_std is the width of the widest operand. In order to get the carry out we pad the widest operand with a 0 if the operands are unsigned. For signed operators the widest operand is sign extended one bit. [7:0] [7:0] [7:0] [7:0] + [0:7] Sum[7:0] [1] out SMD098 omputation Structures Lecture 2 53 Modeling sequential logic Latches Flip-flops Shift registers Pipelined structures ounters ccumulators State machines SMD098 omputation Structures Lecture 2 54

28 use ieee.std_logic_1164. all ; entity Latches is, B,, D, E, F, G : in std_logic; En1, En2, En3 : in std_logic; X, Y, Z : out std_logic); end Latches; architecture RTL of Latches is Latches void using latches. We ll talk about this in later lecture. signal S1 : std_logic; P1 : process (En1, ) if En1 = 1 then X <= ; end if ; end process ; One latch P2 : process (En2, B,, D, S1) if En2 = 1 then S1 <= B or ; Two latches Y <= S1 and D; end if ; end process ; B D En2 P2_s1_1 lat D Q s1 En1 P2_y_1 lat D Q X lat D Q Y X Y P3 : process (En3, E, F, G) variable S2 : std_logic; if En3 = 1 then S2 := E or F; Z <= S2 and G; One latch end if ; end process ; En3 E F G P3_s2_1 P3_z_1 lat D Q Z Z end RTL; SMD098 omputation Structures Lecture 2 55 Unintentional inference of latch use ieee.std_logic_1164. all ; entity BadLatch is, B, : in std_logic; X, Y : out std_logic); end BadLatch; lways check if latches are inferred. ombinational logic should never have latches architecture RTL of BadLatch is P1 : process (, B, ) variable Temp : std_logic_vector(2 downto 0); Temp := & B & ; case Temp is when "000" => X <= 1 ; Y <= 0 ; when "001" "010" => X <= 0 ; Y <= 1 ; when "100" "110" => X <= 1 ; when others => X <= - ; Y <= - ; end case ; end process ; Missing assignment of Y. Latch will be infered. B B e d e d e d lat D Q Y X Y end RTL; SMD098 omputation Structures Lecture 2 56

29 Positive edge triggered flip-flops entity FFs is D1, D2, D3, D4, lk : in std_logic; Q1, Q2, Q3, Q4 : out std_logic); end FFs; architecture RTL of FFs is Note that for a synchronous process only the clock and asynchronous reset/preset need to be present in the sensitivity list. P1 : process(lk) if lk = 1 and lk event then Q1 <= D1; lk D2 D Q Q2 Q2 P2 : process(lk) if rising_edge(lk) then Q2 <= D2; D1 D Q Q1 Q1 P3 : process wait until lk = 1 ; Q3 <= D3; P4 :process wait until rising_edge(lk); Q4 <= D4; end RTL; D4 D3 D Q Q4 D Q Q3 Q4 Q3 SMD098 omputation Structures Lecture 2 57 Flip-flops with reset Synchronous reset The Reset signal should not be in the sensitivity list. synchronous reset The Reset signal must be in the sensitivity list. Synch : process(lk) if rising_edge(lk) then if Reset = 1 then Q2 <= 0 ; Q2 <= D2; Synch : process(lk, Reset) if Reset = 1 then Q1 <= 0 ; elsif rising_edge(lk) then Q1 <= D1; lk Reset D D Q Q2 lk D1 Reset D Q R Q1 Be careful when using asynchronous resets! SMD098 omputation Structures Lecture 2 58

30 Flip-flops with enable entity FFs is D1, D2, Reset, lk, Enable : in std_logic; Q1, Q2 : out std_logic); end FFs; architecture RTL of FFs is signal Gatedlock : std_logic; Gatedlock <= lk and Enable; void gating the clock! Glitches may cause undesired behavior. Gating will introduce skew. Low power designs may use gated clocks, but this require quite advanced design techniques. Bad : process(gatedlock, Reset) if Reset = 1 then Q1 <= 0 ; elsif rising_edge(gatedlock) then Q1 <= D1; Good : process(lk, Reset) if Reset = 1 then Q2 <= 0 ; elsif rising_edge(lk) then if Enable = 1 then Q2 <= D2; end RTL; D1 lk Enable Reset lk Enable D2 Reset gatedclock 0 1 D Q R D Q R Q1 Q2 Use clock enable! feedback mux will enable or disable the flip-flop SMD098 omputation Structures Lecture 2 59 Logic between flip-flops entity FFLogic is lk,, B,, D : in std_logic; Y1, Y2 : out std_logic); end FFLogic; Because variables are updated immediately, variables V1 and V2 does not infer flip-flop architecture RTL of FFLogic is signal S1, S2 : std_logic; process(lk) variable V1, V2 : std_logic; if rising_edge(lk) then S1 <= and B; V1 := xor B; S2 <= and D; V2 := xor D; Y1 <= S1 or S2; Y2 <= V1 xor V2; lk B B lk D s1_1 v1_1 v2_1 D Q s1 y2_1 y1_1 D Q Y2 D Q Y1 Y2 Y1 end RTL; D s2_1 D Q s2 SMD098 omputation Structures Lecture 2 60

31 Shift registers entity ShiftReg is generic ( N : positive := 4); lk, Reset : in std_logic; Shift, Input : in std_logic; Output : out std_logic); end ShiftReg; generic shift register with asynchronous reset and synchronous shift enable. Registers are modeled with a variable. architecture RTL of ShiftReg is Shifter : process(lk, Reset) variable Reg : std_logic_vector(1 to N); if Reset = 1 then Reg := (others => 0 ); elsif rising_edge(lk) then if Shift = 1 then Reg(2 to N) := Reg(1 to N-1); Reg(1) := Input; Output <= Reg(N); end process Shifter; end RTL; Input lk Reset Shift FDE D Q LR E Shifter_reg[1] [1] FDE [1] D [2] Q LR E Shifter_reg[2] FDE [2] D Q LR E Shifter_reg FDE D Q LR E Shifter_reg[4] Output SMD098 omputation Structures Lecture 2 61 entity Shifter is lk, Reset : in std_logic; ShiftLeft, ShiftRight : in std_logic; Data : in std_logic_vector (7 downto 0); Mode : in std_logic_vector (1 downto 0); Qout : out std_logic_vector (7 downto 0)); end Shifter; architecture RTL of Shifter is signal Qout_i : std_logic_vector(7 downto 0); Shift : process(lk) if rising_edge(clk) then if Reset = 1 then Qout_i <= (others => 0 ); case Mode is when "01" => -- Shift right Qout_i <= ShiftRight & Qout_i(7 downto 1); when "10" => -- Shift left Qout_i <= Qout_i(6 downto 0) & ShiftLeft; when "11" => -- Parallel load Qout_i <= Data; when others => null; end case; end process Shift; Qout <= Qout_i; end RTL; Shift registers n 8-bit shift register with shift right, shift left, load and synchronous reset. Register modeled with a signal. Internal signal Qout_i is used because a port of mode out can not be read inside the module. SMD098 omputation Structures Lecture 2 62

32 use ieee.numeric_std.all; entity Pipeddder is lk, Reset : in std_logic;, B : in unsigned(15 downto 0); Sum : out unsigned(15 downto 0); out : out std_logic); end Pipeddder; architecture RTL of Pipeddder is signal Reg1, RegB1 : unsigned(15 downto 0); signal Reg2, RegB2 : unsigned(7 downto 0); signal arrypipe : std_logic; signal SumPipe : unsigned(7 downto 0); process(lk, Reset) variable Sum_v : unsigned(8 downto 0); variable arrypipe_v : integer; if Reset = 1 then Reg1 <= (others => 0 ); Reg2 <= (others => 0 ); RegB1 <= (others => 0 ); RegB2 <= (others => 0 ); Sum <= (others => 0 ); SumPipe <= (others => 0 ); arrypipe <= 0 ; out <= 0 ; elsif rising_edge(lk) then Reg1 <= ; RegB1 <= B; Sum_v := ( 0 & Reg1(7 downto 0)) + RegB1(7 downto 0); arrypipe <= Sum_v(8); SumPipe <= Sum_v(7 downto 0); Reg2 <= Reg1(15 downto 8); RegB2 <= RegB1(15 downto 8); Sum(7 downto 0) <= SumPipe; [15:0] if arrypipe = 1 then arrypipe_v := 1; arrypipe_v := 0; Sum_v := ( 0 & Reg2 + RegB2 + arrypipe_v); Sum <= Sum_v(7 downto 0) & SumPipe; out <= Sum_v(8); B[15:0] pipelined adder ritical path is the carry chain. Pipelining increases speed but adds latency Reg1 RegB1 [7:0] [7:0] [15:8] [15:8] Reg2 RegB2 arrypipe SumPipe out Sum out Sum[15:0] end RTL; SMD098 omputation Structures Lecture 2 63 use ieee.numeric_std.all; entity ounter is port( lk : in std_logic; Reset : in std_logic; Enable : in std_logic; ount : out unsigned(7 downto 0)); end ounter; ounters binary counter with enable and asynchronous reset architecture RTL of ounter is lk nt : process(lk, Reset) variable ountreg : unsigned(7 downto 0); if Reset = 1 then ountreg := (others => 0 ); elsif rising_edge(lk) then if Enable = 1 then ountreg := ountreg + 1; ount <= ountreg; end process nt; Enable Reset [7:0] + un1_count[0:7] [0:7] [0:7] D[7:0] Q[7:0] R ount[7:0] [7:0] [7:0] ount[7:0] end RTL; SMD098 omputation Structures Lecture 2 64

33 Homework! It was my intention to prepare questions related to lab 1-2. Unfortunately I haven t had the time to do so Instead I want you to write three VHDL models: a 4-bit Gray counter, an 8-bit Johnson counter and a 16-bit one-hot counter. The counters should have asynchronous reset and a count enable. No. Binary Gray Johnson One-hot Encoding formats SMD098 omputation Structures Lecture 2 65 use ieee.numeric_std.all; entity ccumulator is lk, Reset : in std_logic; : in signed(3 downto 0); Load : in std_logic; cc : out signed(15 downto 0)); end ccumulator; architecture RTL of ccumulator is process(lk, Reset) variable cc_v : signed(15 downto 0); if Reset = 1 then cc_v := ( others => 0 ); elsif rising_edge(lk) then if Load = 1 then cc_v(15 downto 4):= (others => (3)); cc_v(3 downto 0) := ; lk Load Reset cc_v := cc_v + ; cc <= cc_v; end RTL; [3:0] [3:0] [3:0] [15:0] un36_acc_v[1:16] ccumulators n accumulator is a common building block in DSP applications. The shown accumulator is 16 bits wide and adds a 4-bit number each clock cycle to the accumulated value. The accumulator register is loadable. + [1:16] [3:0] [1:16] 0 1 [15:0] acc_v_5[15:0] [15:0] D[15:0] Q[15:0] R cc[15:0] [15:0] [15:0] cc[15:0] SMD098 omputation Structures Lecture 2 66

34 Finite State Machines - FSM Moore FSM: Outputs are a function of the current state Inputs Next State Logic State Register Output Logic Moore outputs Moore Mealy FSM: Outputs are a function of the current state and inputs. We have combinational paths through the FSM. Inputs Next State Logic State Register Output Logic Mealy outputs Mealy SMD098 omputation Structures Lecture 2 67 State machines ombined Mealy / Moore FSM Inputs Next State Logic State Register Output Logic Mealy outputs ombined Mealy / Moore Output Logic Moore outputs Registered output FSM. Outputs are registered, which prevents output glitches. Inputs Next State Logic State Register Next Output Logic Output Register Registered outputs Registered output FSM SMD098 omputation Structures Lecture 2 68

35 State encoding State encoding - the way binary numbers are assigned to states. You may define your own encoding or let the synthesis tool define it ommon encoding formats: No. Binary Gray Johnson One-hot Encoding formats SMD098 omputation Structures Lecture 2 69 State encoding in VHDL Using an enumerated type, synthesis tool will decide encoding: architecture Enc1 of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State;... end architecture Enc1; Using constants to represent states architecture Enc2 of StateMachine is -- Binary encoding constant Idle : std_logic_vector(2 downto 0) := "000"; constant S1 : std_logic_vector(2 downto 0) := "001"; constant S2 : std_logic_vector(2 downto 0) := "010"; constant S3 : std_logic_vector(2 downto 0) := "011"; constant S4 : std_logic_vector(2 downto 0) := "100"; constant S5 : std_logic_vector(2 downto 0) := "101"; signal PresentState, NextState : std_logic_vector(2 downto 0);... end Enc2; architecture Enc2 of StateMachine is -- One-hot constant Idle : std_logic_vector(2 downto 0) := "000001"; constant S1 : std_logic_vector(2 downto 0) := "000010"; constant S2 : std_logic_vector(2 downto 0) := "000100"; constant S3 : std_logic_vector(2 downto 0) := "001000"; constant S4 : std_logic_vector(2 downto 0) := "010000"; constant S5 : std_logic_vector(2 downto 0) := "100000"; signal PresentState, NextState : std_logic_vector(2 downto 0);... end Enc2; SMD098 omputation Structures Lecture 2 70

36 Synplify and FSM encoding Synplify have a FSM compiler. It automatically detects state machines in the source code. The FSMs are implemented with either sequential, gray or one-hot encoding. architecture Synplify of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State; attribute syn_encoding : string; attribute syn_encoding of PresentState : signal is "onehot";... end architecture Synplify; To implement safe FSMs the attribute should be changed to... architecture SynplifySafe of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State; attribute syn_encoding : string; attribute syn_encoding of PresentState : signal is "onehot, safe";... end architecture SynplifySafe; SMD098 omputation Structures Lecture 2 71 Example Moore FSM 000 Idle 000 S5. B 101 S1 entity StateMachine is lk, Reset : in std_logic;, B : in std_logic; Y : out std_logic_vector(2 downto 0)); end StateMachine; architecture Moore of StateMachine is 110 S4. B S2. B type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State; end architecture Moore;. B S3 011 SMD098 omputation Structures Lecture 2 72

37 architecture Moore1 of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); end architecture Moore1; architecture Moore2 of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State; signal PresentState, NextState : State; StateFFs: process(lk, Reset) StateFFs: process(lk, Reset) if Reset = 1 then if Reset = 1 then PresentState <= Idle; PresentState <= Idle; elsif rising_edge(lk) then elsif rising_edge(lk) then PresentState <= NextState; PresentState <= NextState; end process StateFFs; end process StateFFs; NxtStateLogic: process(, B, PresentState) omblogic: process(, B, PresentState) case PresentState is case PresentState is when Idle => when Idle => NextState <= S1; NextState <= S1; when S1 => Y <= "000"; if = 1 then when S1 => NextState <= S2; if = 1 then NextState <= S2; NextState <= S3; NextState <= S3; when S2 => if = 0 and B = 1 then Y <= "101"; NextState <= S3; when S2 => elsif = 1 and B = 1 then if = 0 and B = 1 then NextState <= S4; NextState <= S3; elsif = 1 and B = 0 then elsif = 1 and B = 1 then NextState <= S5; NextState <= S4; elsif = 1 and B = 0 then NextState <= S2; NextState <= S5; when S3 => NextState <= S2; NextState <= S4; when S4 => Y <= "111"; NextState <= S5; when S3 => when S5 => NextState <= S4; NextState <= Idle; Y <= "011"; end case; when S4 => NextState <= S5; Y <= "110"; OutputLogic : process(presentstate) when S5 => NextState <= Idle; case PresentState is Y <= "000"; when Idle => end case; Y <= "000"; when S1 => Y <= "101"; end architecture Moore2; when S2 => Y <= "111"; when S3 => Y <= "011"; when S4 => Y <= "110"; when S5 => Y <= "000"; end case; oding styles for Moore FSM architecture Moore3 of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState : State; StateFFs: process(lk, Reset) if Reset = 1 then PresentState <= Idle; elsif rising_edge(lk) then case PresentState is when Idle => PresentState <= S1; when S1 => if = 1 then PresentState <= S2; PresentState <= S3; when S2 => if = 0 and B = 1 then PresentState <= S3; elsif = 1 and B = 1 then PresentState <= S4; elsif = 1 and B = 0 then PresentState <= S5; PresentState <= S2; when S3 => PresentState <= S4; when S4 => PresentState <= S5; when S5 => PresentState <= Idle; end case; end process StateFFs; OutputLogic : process(presentstate) case PresentState is when Idle => Y <= "000"; when S1 => Y <= "101"; when S2 => Y <= "111"; when S3 => Y <= "011"; when S4 => Y <= "110"; when S5 => Y <= "000"; end case; end architecture Moore3; SMD098 omputation Structures Lecture 2 73 Example Mealy FSM / Y / Y / Y S1 S2 S3 / Y / Y / Y entity StateMachine is lk, Reset : in std_logic; : in std_logic; Y : out std_logic); end StateMachine; architecture Mealy of StateMachine is type State is ( S1, S2, S3); signal PresentState, NextState : State; StateFFs: process(lk, Reset) if Reset = 1 then PresentState <= S1; elsif rising_edge(lk) then PresentState <= NextState; end process StateFFs; omblogic: process(, PresentState) case PresentState is when S1 => if = 1 then NextState <= S2; Y <= 1 ; NextState <= S1; Y <= 0 ; when S2 => if = 0 then NextState <= S3; Y <= 1 ; NextState <= S1; Y <= 0 ; when S3 => if = 1 then NextState <= S2; Y <= 1 ; NextState <= S3; Y <= 0 ; end case; end architecture Mealy; SMD098 omputation Structures Lecture 2 74

38 Three-state buffers The output of a three-state or tri-state buffer may be left floating, or put in high impedance. This is modeled as Z in std_logic. Multiple tri-state outputs can be wired together to to create a tristate bus. Only one buffer must be enabled at any time! Possible MOS implementation Truth table Symbol Vcc En I O En 0 - Z I O En I O _En Tri-state bus B_En B _En O SMD098 omputation Structures Lecture 2 75 Modeling tri-state buffers in VHDL entity TriStateBus is, B, : in std_logic; En, EnB, En : in std_logic; Y : out std_logic ); end TriStateBus; architecture RTL of TriStateBus is Y <= when En = 1 Z ; Y <= B when EnB = 1 Z ; Y <= when En = 1 Z ; end RTL; En EnB B En Y SMD098 omputation Structures Lecture 2 76