W78C438C 8-BIT MICROCONTROLLER GENERAL DESCRIPTION FEATURES

Transcription

1 W GENERL ERITION -BIT MIROONTROLLER The W is a high-performance single-chip MO -bit microcontroller that is a derivative of the W microcontroller family The W is functionally compatible with the W except that it provides either a KB program MB data memory address or memory-mapped chip select logic five general IO ports and four external interrupts In the W two IO ports ort and ort are available for general-purpose use (ort also supports alternative functions) and ort and ort are used as the address bus and data bus respectively To enable ort and ort to also be used as general purpose IO ports the W provides two dedicated address ports ( and ) that serve as address output for KB of memory and one addressdata port () that serves as ROM code input and external RM data inputoutput Unlike the W this product does not require an external latch device for multiplexing low byte addresses The W also provides four pins ( ) to support either KB program MB data memory space or memory-mapped chip select logic one parallel IO port (ort ) without bit addressing mode and two additional external interrupts (INT INT ) The W is programmed in a manner fully compatible with that used to program the W except that the external data RM is accessed by the instruction ddress paging is performed by loading page addresses into the HB (high byte) register which is not a standard register in the W before execution of the instruction FETURE -bit MO microcontroller Fully static design to MHz operation ROM-less operation -byte on-chip scratchpad RM Either KB program MB data memory address space or memory-mapped chip select pins One -bit dataaddress port Two -bit and one -bit (optional) address ports Five -bit bidirectional IO ports Four -bit bit-addressable IO ports and one -bit parallel IO port Eight-source two-level interrupt capability Three -bit timercounters Four external interrupts One full-duplex serial channel Built-in power management Idle mode ower-down mode ackages: -pin L: W- -pin QF: WF- ublication Release ate: July Revision

2 W - - IN ONFIGURTION W INT REET INT RX V TX INT INT T T 9 N V N 9 R X T L X T L V N W R E EN LE V V -pin L

3 W in onfigurations continued N T E X T V N REET INT INT RX V TX INT INT T T WR WF -pin QF E V V LE EN X T L R X T L V N ublication Release ate: July Revision

4 W IN ERITION - IO ort These pins function the same as those in the W except that a multiplexed addressdata bus is not provided during accesses to external memory - IO ort Functions are the same as in the W - IO ort Functions are the same as in the W except that an upper address bus is not provided during accesses to external memory - IO ort Functions are the same as in the W - ataddress Bus provides multiplexed low-byte addressdata during access to external memory - ddress Bus outputs the <:> address of the external ROM multiplexed with the <:> address of the external data RM - ddress Bus outputs the <:> address of the external ROM multiplexed with the <:> address of the external data RM uring the execution of the output of comes from the HB register which is the page register for the high byte address and its address is H - ddress Buship elect ins et bit of the EM (Extended rogram Memory ddress) register to determine the functions of port When this bit is "" (default value) allows the external memory data to be accessed by outputting the <9:> address of the external memory from bits<:> of the EM register during the execution of or "MOVX dest src" t all other times <:> will output H When this bit is "" <:> ( ) are the chip select pins which support memory-mapped peripheral device select and only one pin is active low at any one time These pins are decoded by <:> For details see the table below ERITION : low; others: high : low; others: high : low; others: high : low; others: high - -

5 W - IO ort Functions are the same as those of ort in the W except that they are mapped by the register and not bit-addressable The register is not a standard register in the W Its address is at H INT INT External Interrupt Input Functions are similar to those of external INT INT in the W except that the functionsstatus of these interrupts are determinedshown by the bits in the XION (External Interrupt ontrol) register The XION register is bit-addressable but is not a standard register in the W Its address is at H For details see the Functional escription below E External ddress Input Functions same as W RT XTL XTL EN LE Functions same as W BLOK IGRM FR ort ort RM Bytes U ata Bus Timer ort lternate ort ort lternate ORE erial ort INT Interrupt INT Timer Timer lternate INT INT ublication Release ate: July Revision

6 W FUTIONL ERITION The W is a functional extension of the W microcontroller It contains a RM KB program MB data memory address or memory-mapped chip select logic two -bit address ports one -bit data port five general IO ports four external interrupts three timerscounters and one serial port edicated ata and ddress ort The W provides four general-purpose IO ports for W applications; the address and data bus are separated from ort and ort so that these ports can be used as general-purpose IO ports In this product is the data bus for external ROM and RM <:> are the low byte address <:> are the high byte address EN enables the external ROM to and ( WR ) and (R ) are the writeread control signals for the external RM The external latch for multiplexing the low byte address is no longer needed in this product The W uses and to support KB external program memory and KB external data memory just as a standard W does The W provides four pins ( ) to support either KB program MB data memory space or memory-mapped chip select logic Bit of the EM (Extended rogram Memory ddress) register which is described in Table below determines the functions of these pins When this bit is "" (the default value) <:> support external programdata memory addresses up to KB MB for applications which need additional external memory to store large amounts of data lthough there is M bytes memory space instructions stored here can not be run at full range of this area except the first Kbytes It is owing to the fact that during the instruction fetch cycle <:> always output s to address lines 9 This limits the program code to store at address FFFFH (K) The rest of the area (H FFFFFH) can be treated as ROM data storage which can be read by instruction When is executed to read the external ROM data or "MOVX dest src" is executed to access the external RM data <:> output address <9:> from bits <:> of the EM (Extended rogram Memory ddress) register t other times <:> always output H to ensure the instruction fetch is within the K program memory address ifferent banks can be selected by modifying the content of the EM register before the execution of or "MOVX dest src" [Example] ccess the external ROMRM data from external memory space LR ; lear ccumulator MOV TR #H ; lear TR MOV H # ; Initialize EM(H) EM = : extended memory space ; EM<:> = B the address range: FFFFH ; Read the external ROM data from location H ; Read the external RM data from location H LR MOV H #H ; EM<:> = B the address range: H FFFFH ; Read the external ROM data from location H ; Write the contents of ccumulator to external RM data ; location H - -

7 W () EM = W EN \ \ \ \ R (-bit) OE EROM K ROGRM T RE INT INT INT INT RM R MB (-bit) R WR T WE OE When bit of the EM is "" <:> are the output pins that support memory-mapped peripheral chip select logic which eliminates the need for glue logic These pins are decoded by <:> Only one pin is active low at any time That is they are active individually with K address resolution For example is active low in the address range from H to FFFH is active low in the address range from H to FFFH and so forth (B) EM = W R (-bit) \ \ EROM K ROGRM EN \ OE T RE INT INT INT INT R WR \ \ RM R (-bit) h T FFFh (k) WE OE evice h FFFh (k) evice h BFFFh (k) evice h FFFFh (k) ublication Release ate: July Revision

8 W The EM register is a nonstandard -bit FR at address H in the standard W To readwrite the EM register one can use the "MOV direct" instruction or "read-modify-write" instructions Bits <:> of the EM register are reserved bits and their output values are B if they are read The content of EM is H after a reset The EM register does not support bitaddressable instructions dditional IO ort BIT NME FUTION EM EM = : KB program MB data memory space mode EM = : memory-mapped chip select mode EM Reserved EM Reserved EM Reserved EM Value of EM Value of EM Value of EM Value of Table Functional escription of EM Register The W provides one parallel IO port ort Its function is the same as that of ort in the W except that it is mapped by the register and is not bit-addressable The register is not a standard register in the standard W Its address is at H To readwrite the register one can use the "MOV direct" instruction or "read-modify-write" instructions [Example]: MOV H ; Output data via ort MOV H ; Input data via ort dditional External Interrupt The W provides two additional external interrupts INT and INT whose functions are similar to those of external interrupts and in the W The functions (or the status) of these interrupts are determined by (or shown by) the bits in the XION (External Interrupt ontrol) register For details see Table The XION register is bit-addressable but is not a standard register in the standard Its address is at H To setclear the bit of the XION register one can use the "ETB(LR) bit" instruction For example "ETB H" sets the EX bit of XION The interrupt vector addresses and the priority polling sequence within the same level are shown in Table [Example] ETB H ; INT is falling-edge triggered ETB H ; INT is high-priority ETB H ; Enable INT LR H ; INT is low-level triggered - -

9 W BIT R NME FUTION H X Highlow priority level for INT is specified when this bit is setcleared by software H EX Enabledisable interrupt from INT when this bit is setcleared by software H IE If IT is "" IE is setcleared automatically by hardware when interrupt is detectedserviced H IT INT is falling-edgelow-level triggered when this bit is setcleared by software H X Highlow priority level for INT is specified when this bit is setcleared by software H EX Enabledisable interrupt from INT when this bit is setcleared by software H IE If IT is "" IE is setcleared automatically by hardware when interrupt is detectedserviced H IT INT is falling-edgelow-level triggered when this bit is setcleared by software Table Functions of XION Register INTERRUT OURE VETOR RE RIORITY EQUEE External Interrupt H (Highest) Timerounter BH External Interrupt H Timerounter BH erial ort H Timerounter BH External Interrupt H External Interrupt BH (Lowest) Newly dded pecial Function Registers Table riority of Interrupts The W uses four newly defined special function registers which are described in Table To readwrite these registers use the "MOV direct" or "read-modify-write" instructions REGITER R FUTION LENGTH RW TYE HB H uring the execution of the content of HB is output to EM H EM determines functions of EM EM determine values of <:> when EM is "" VLUE FTER REET RW H RW H H The content of is output to port RW FFH XION H The bits of XION determineshow the functionsstatus of INT INT Bit-addressable Table Newly dded pecial Function Registers of the W RW H ublication Release ate: July Revision

10 W Notes: The instructions used to access these nonstandard registers may cause assembling errors with respect to the assembler but these errors can be ignored by adding directive "RMHK OFF" ahead these instructions In the newly added FR of W only XION register is bit-addressable ower Reduction Function The W supports power reduction just as the W does The following table shows the status of the external pins during the idle and power-down modes FUTION LE EN - Idle ort ata Floating ddress Note ower own ort ata Floating ddress Note Note: is either or a value decoded by <:> depending on the value of EM rogramming ifference The W is programmed in the same way as the W except that the external data RM is accessed by a instruction To support address paging there is an additional -bit FR "HB" (high byte) which is a nonstandard register at address H uring execution of the instruction the contents of HB are output to The page address is modified by loading the HB register with a new value before execution of the instruction To readwrite the HB register one can use the "MOV direct" instruction or "read-modify-write" instructions The HB register does not support bit-addressable instructions [Example] MOV R #H ; R = MOV H #FFH ; HB contents FFH ; Read the contents of external RM location FFH into ; ccumulator MOV H #H ; HB contents H ; opies the contents of ccumulator into external RM ; location H BOLUTE MXIMUM RTING RMETER YMBOL MIN MX UNIT ower upply V V - + V Input Voltage VIN V - V + V Operating Temperature TOR torage Temperature TTG - + Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device - -

11 W HRTERITI V V = V ±% T = FO = MHz unless otherwise specified RMETER YM TET ONITION MIN TY MX UNIT Oper Voltage V V Oper urrent I * No load - - m Idle urrent IILE rogram idle mode - - m wdn urrent IWN rogram power-down mode - - µ Input Leakage urrent Input Leakage urrent Input Leakage urrent Input Leakage urrent ILK ILK INT INT Internal pull-high Notes REET Internal pull-low Notes µ µ ILK E ort Note µ ILK Note µ Output Low Voltage VOL IOL = m (ort ) - - V Output High Voltage VOH IOH = - µ (ort ) - - V Output Low Voltage VOL IOL = m Note (LE EN ) Output High Voltage VOH IOH = - µ Note (LE EN ) - - V - - V Output Low Voltage VOL IOL = m ( ) - - V Output High Voltage VOH IOH = - µ ( ) - - V Input Voltage VILT V = V ±% - V Input Voltage VIHT V = V ±% - Note V Input Voltage VIL V = V ±% XTL Note - V Input Voltage VIH V = V ±% XTL Note - Note V Input Voltage VILR V = V ±% REET Note - V Input Voltage VIHR V = V ±% REET Note - Note V Notes: < VIN < V for INT INT REET E ort and inputs in leakage Using an internal pull lowhigh resistor (approx K) LE EN and in external program or data access mode The maximum input voltage is V +V XTL is a MO input and REET is a chmitt trigger input ublication Release ate: July Revision

12 W HRTERITI specifications are a function of the particular process used to manufacture the product the ratings of the IO buffers the capacitive load and the internal routing capacitance Most of the specifications can be expressed in terms of multiple input clock periods (T) and actual parts will usually experience less than a ± n variation lock Input Waveform RMETER YMBOL MIN TY MX UNIT NOTE Operating peed FO - MHz lock eriod T - - n lock High TH - - n lock Low TL - - n Notes: The clock may be stopped indefinitely in either state The T specification is used as a reference in other specifications There are no duty cycle requirements on the XTL input rogram Fetch ycle RMETER YMBOL MIN TY MX UNIT ddress Valid to EN Low TL T - - n EN Low to ata Valid TV - - T n ata Memory ReadWrite ycle RMETER YMBOL MIN TY MX UNIT ddress Valid to R Low TRL T - T + n R Low to ata Valid TRV - - T n ata Hold fter R High TRQ - T n R ulse Width TR T - T - n ddress Valid to WR Low TWL T - T + n ata Valid to WR Low TWL T - - n ata Hold fter WR High TWQ T - - n WR ulse Width TW T - T - n Note: " " (due to buffer driving delay and wire loading) is n - -

13 W TIMING WVEFORM rogram Fetch ycle XTL EN <:> <:> T L T V address <:> address code ata Memory ReadWrite ycle XTL 9 EN <:> addr <9:> out (When bit of EM is ) <:> H or HB FR out GM address <:> L or Ri out GM address T RL R T R <:> addr T RV data T RQ addr WR T W T WL <:> addr T OUT T WL T WQ ublication Release ate: July Revision

14 W TYIL LITION IRUIT Using K bit External EROM (WE) V U K 9 INT INT 9 RX V TX INT INT T T WR N REET V 9 9 V LE EN 9 R X T L X T L V N W V 9 9 E N GN E OE WE O O O O O O 9 O O Vpp Vcc GM Vss R Figure - -

15 W RYTL R MHz MHz MHz K MHz K bove table shows the reference values for crystal applications Notes: For R components refer to Figure It is recommended that the crystals be replaced with oscillators for applications above MHz KGE IMENION -pin L H e b eating lane y E HE E ymbol imension in inches imension in mm Min Nom Max Min Nom Max 9 b b c E e G G E H H E L y θ Notes: imension & E do not include interlead flash imension b does not include dambar protrusionintrusion ontrolling dimension: Inches General appearance spec should be based on final visual inspection spec G ublication Release ate: July Revision

16 W ackage imensions continued -pin QF H E H E ymbol b c E e H H E L L y θ imension in inches imension in mm Min Nom Max Min Nom Max e b c Notes: imension & E do not include interlead flash imension b does not include dambar protrusionintrusion ontrolling dimension: Millimeters General appearance spec should be based on final visual inspection spec ee etail F eating lane y L L θ etail F Headquarters Winbond Electronics (HK) Ltd No reation Rd III Rm World Trade quare Tower II cience-based Industrial ark Hoi Bun Rd Kwun Tong Hsinchu Taiwan Kowloon Hong Kong TEL: -- TEL: - FX: --9 FX: - Voice & Fax-on-demand: --9 Taipei Office F No ec Min-heng East Rd Taipei Taiwan TEL: --9 FX: --9 Winbond Electronics North merica orp Winbond Memory Lab Winbond Microelectronics orp Winbond ystems Lab N First treet an Jose 9 U TEL: -9 FX: -9 Note: ll data and specifications are subject to change without notice - -