Next Generation Package on Package
|
|
- Russell Curtis
- 6 years ago
- Views:
Transcription
1 Next Generation Package on Package Alternative PoP with Routable Substrate Interposer for Stacking Solution Steven(Jui Cheng) Lin, Siliconware Precision Industries Co., Ltd
2 Outline High IO / Wide IO Market Trend Alternative PoP for Wide IO Approach HBW PoP Cu Core Solder Ball Development Status HBW PoP Cu Stud Development Status Summary 2
3 IC Market Overview by Product Applications Source: PRISMARK AUG 2013 >>> Compared with other product applications, Smart Phones and Tablets have much higher growth rates. 3
4 Mobile Memory Technology Trend Mobile DRAM has evolved in a way to support higher bandwidth and power efficiency for Smart devices. Mobile DDR 4
5 SMART Phone AP Package Trend LPDDR LPDDR2 LPDDR3 LPDDR4 or Wide I/O 64Mb~2Gb 64Mb~3.2Gb 4Gb~16Gb 8Gb~32Gb PKG Ht <1.0 (mm) 3D IC Clock Speed 1.1 (mm) Bare Die MEP 2.5GHz 1.5GHz 1.2~1.5 (mm) Exposed Die Molded PoP Thermal 1.2GHz epop PoP Tj 105C 1.0GHz 5
6 PoP Development Trend PoP Roadmap -- Thin Low Cost High Band Width Enhanced PoP Exposed Die PoP Bare Die PoP HBW PoP Structure Application Bottom Digital: APPs+Modem Top Memory: LPDDRx Bottom Digital: APPs + Modem Top: RFA/PMIC/Connectivity Module Package Thickness 0.84mm 0.80mm 0.80mm 0.67mm Target SPIL Readiness 2009 ~ 2012 ~ 2013 ~ 2014 ~ Alternative HBW PoP with routable substrate interposer development for high IO approach. 6
7 Alternative PoP for High IO/Wide IO Alternative LPDDR2/3 LPDDR5 or wide I/O2 Mobile LPDDR2/3 with Peripheral Balls LPDDR4/RFA/PMIC potentially with Full Array Balls Wide I/O2 800~1000 Micro Bumps epop HBW PoP 3D IC Hi IO Memory: LPDDR4 IO Bandwidth 12.8GB/die Estimated Package Ball Count 256~520 7
8 Memory PKG Ball Pitch & Ball Counts Mobile LPDDR2/3 with Peripheral Balls Hi IO Memory if Full Array 2 rows 3 rows Full Array POR Solder Ball or Cu Core Cu Stud PoP PoP Package Size / TBP Top Ball Counts Upper Substrate Top Surafce Top Ball Rows 0.5mm 0.4mm 0.35mm 0.3mm 0.2mm 2 rows 3 rows 4 rows 5 rows Solder Ball Count Full Array
9 HBW PoP: Cu Core Solder Ball & Cu Stud POR Cu Core ~0.3mm TBP (3Rows,I/O-480) Cu Stud <0.3mm TBP (4 rows,i/o-860) Cu Core Solder Ball + Two Side Cu Studs + Stacking Stacking Mold Encapsulation Mold Encapsulation 9
10 HBW PoP Cu Core TV Structure Design Test Vehicle: PKG type: Mold Encapsulated PoP PKG size: 12x12 mm 2 Die size: 8.3x8.7 mm 2 Top substrate: 126 um/2l Bottom substrate: 242 um/4l Structure : CUF + Mold Top/Bottom Ball Pitch: 0.4/0.4mm Top/Bottom Ball Size: 0.2/0.25mm H: 670um 195um Cu Core 25um Sn 190um SRO 10
11 HBW PoP Cu Core TV Evaluation Upper-bottom Substrate Mounting: Ball Standoff Avg: 165um Issue: Non-wetting Root cause: Top sub. warpage/insufficient soldler Action: 1. Reflow jig improvement 2. Increase solder vol. X-ray SEM FA Good joint Non-wetting non-wetting 11
12 HBW PoP Cu Core TV Evaluation Warpage Data with optimized EMC: HBW PoP showed good warpage performance Sign Direction Crying (+) Corners is lower than center Smiling (-) Corners is higher than center Warpage (um) Warpage by temperature change Temperature ( C) 28C 50C 100C 150C 183C 217C 245C 260C 245C 217C 183C 150C 100C 50C 32C #1-1 #1-2 #1-3 Sample 28C 50C 100C 150C 183C 217C 245C 260C 245C 217C 183C 150C 100C 50C 32C # # # Unit: um 12
13 HBW PoP Cu Core TV Evaluation Layer Thickness Verification : Meet design value Layer Thickness Layer( mm) Design Measurement Top SUB / Stand off Bottom SUB / ( Remark :BGA ball & POP Cu ball not at same location ) Final ENG Sample Structure & Package Level Reliability : Workable process shown by reliable profile L3/260 + TCB 500x pass (target to TCB1000x) 13
14 HBW PoP Cu Stud TV Structure Design Test Vehicle: 0.255mm stud pitch (TV1) PKG size: 15x15 mm 2 Die size: 11.3x9.4 mm 2 Top substrate: 126 um/2l Bottom substrate: 242 um/4l Top Cu height: 30 +/-15, Sn : 45 +/-15 Bottom Cu height: 130 +/-20 Mold thickness: 172 um IO count: 864 (4 rows) 255 um > 800 IOs 172 um 14
15 HBW PoP Cu Stud Development Cu stud height 110 um development : The uniformity of +/- 15 um meet the requirement of +/- 20 um on all three legs. Diameter : 110 um Diameter : 130 um Diameter : 150 um 15
16 HBW PoP Cu Stud Development Diameter / Height_150 um / 120 um development result : Cu height: -Min: um ; Max: um -Avg: um ; Stdev: 4.36 Cu height uniformity: -3 *(σ +σ x ) = 3*( ) = +/- 16 um After developing After plating + buffing ~120um 16 Cross-section
17 High Cu Stud with Good Uniformity Merit: Good Cu plating uniformity : By panel plating to approach balanced plating current distribution. Good Cu height uniformity : By grinding process to control Cu height (Capability : +/- 20 um) 1) 2) 17
18 HBW PoP Cu Stud Development Cu Stud pitch / Height_200 um / 130 um development result : 18
19 Summary The high IO development is inevitable based on the functionality increasing on smart phone and tablet. SPIL alternative PoP with routable substrate interposer can approach the high bandwidth/ high IO application. More challenge IO request(>1000) is even under developing by SPIL HBW PoP. 19
20 20 Thank You!
3-D Package Integration Enabling Technologies
3-D Package Integration Enabling Technologies Nanium - Semi Networking Day David Clark - Choon Heung Lee - Ron Huemoeller June 27th, 2013 Enabling a Microelectronic World Mobile Communications Driving
More informationMaterial technology enhances the density and the productivity of the package
Material technology enhances the density and the productivity of the package May 31, 2018 Toshihisa Nonaka, Ph D. Packaging Solution Center Advanced Performance Materials Business Headquarter Hitachi Chemical
More informationAdvanced Flip Chip Package on Package Technology for Mobile Applications
Advanced Flip Chip Package on Package Technology for Mobile Applications by Ming-Che Hsieh Product and Technology Marketing STATS ChipPAC Pte. Ltd. Singapore Originally published in the 17 th International
More informationFine Pitch High Bandwidth Flip Chip Package-on-Package Development
Fine Pitch High Bandwidth Flip Chip Package-on-Package Development by Ming-Che Hsieh, STATS ChipPAC Pte. Ltd. Stanley Lin, MediaTek, Inc. Ian Hsu, MediaTek, Inc. Chi-Yuan Chen, MediaTek, Inc. NamJu Cho,
More informationBringing 3D Integration to Packaging Mainstream
Bringing 3D Integration to Packaging Mainstream Enabling a Microelectronic World MEPTEC Nov 2012 Choon Lee Technology HQ, Amkor Highlighted TSV in Packaging TSMC reveals plan for 3DIC design based on silicon
More informationSMAFTI Package Technology Features Wide-Band and Large-Capacity Memory
SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory KURITA Yoichiro, SOEJIMA Koji, KAWANO Masaya Abstract and NEC Corporation have jointly developed an ultra-compact system-in-package
More informationThermal Management Challenges in Mobile Integrated Systems
Thermal Management Challenges in Mobile Integrated Systems Ilyas Mohammed March 18, 2013 SEMI-THERM Executive Briefing Thermal Management Market Visions & Strategies, San Jose CA Contents Mobile computing
More informationPhysical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis
I NVENTIVE Physical Design Implementation for 3D IC Methodology and Tools Dave Noice Vassilios Gerousis Outline 3D IC Physical components Modeling 3D IC Stack Configuration Physical Design With TSV Summary
More information3D TECHNOLOGIES: SOME PERSPECTIVES FOR MEMORY INTERCONNECT AND CONTROLLER
3D TECHNOLOGIES: SOME PERSPECTIVES FOR MEMORY INTERCONNECT AND CONTROLLER CODES+ISSS: Special session on memory controllers Taipei, October 10 th 2011 Denis Dutoit, Fabien Clermidy, Pascal Vivet {denis.dutoit@cea.fr}
More informationAdvanced Packaging For Mobile and Growth Products
Advanced Packaging For Mobile and Growth Products Steve Anderson, Senior Director Product and Technology Marketing, STATS ChipPAC Growing Needs for Silicon & Package Integration Packaging Trend Implication
More informationPackaging for the. Contents. Cloud Computing Era. DIMM-in-a- Package/xFD. BVA PoP. Conclusions. Ilyas Mohammed January 24, /24/2013
Packaging for the Cloud Computing Era Ilyas Mohammed January 24, 2013 Contents Cloud Computing DIMM-in-a- Package/xFD BVA PoP Conclusions Client-Server Design and Performance Features Roadmaps Trends Assembly
More information3D Integration & Packaging Challenges with through-silicon-vias (TSV)
NSF Workshop 2/02/2012 3D Integration & Packaging Challenges with through-silicon-vias (TSV) Dr John U. Knickerbocker IBM - T.J. Watson Research, New York, USA Substrate IBM Research Acknowledgements IBM
More informationUltra Thin Substrate Assembly Challenges for Advanced Flip Chip Package
Ultra Thin Substrate Assembly Challenges for Advanced Flip Chip Package by Fred Lee*, Jianjun Li*, Bindu Gurram* Nokibul Islam, Phong Vu, KeonTaek Kang**, HangChul Choi** STATS ChipPAC, Inc. *Broadcom
More informationMulti Level Stacked Socket Challenges & Solutions
Multi Level Stacked Socket Challenges & Solutions Mike Fedde, Ranjit Patil, Ila Pal & Vinayak Panavala Ironwood Electronics 2010 BiTS Workshop March 7-10, 2010 Content Introduction Multi Level IC Configuration
More informationInnovative 3D Structures Utilizing Wafer Level Fan-Out Technology
Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology JinYoung Khim #, Curtis Zwenger *, YoonJoo Khim #, SeWoong Cha #, SeungJae Lee #, JinHan Kim # # Amkor Technology Korea 280-8, 2-ga, Sungsu-dong,
More informationComparison & highlight on the last 3D TSV technologies trends Romain Fraux
Comparison & highlight on the last 3D TSV technologies trends Romain Fraux Advanced Packaging & MEMS Project Manager European 3D Summit 18 20 January, 2016 Outline About System Plus Consulting 2015 3D
More informationAdvancing high performance heterogeneous integration through die stacking
Advancing high performance heterogeneous integration through die stacking Suresh Ramalingam Senior Director, Advanced Packaging European 3D TSV Summit Jan 22 23, 2013 The First Wave of 3D ICs Perfecting
More informationPackaging Technology for Image-Processing LSI
Packaging Technology for Image-Processing LSI Yoshiyuki Yoneda Kouichi Nakamura The main function of a semiconductor package is to reliably transmit electric signals from minute electrode pads formed on
More informationSurvey of Circuit Board Warpage During Reflow
Survey of Circuit Board Warpage During Reflow Michael J. Varnau Delphi Electronics & Safety 8/20/07 Table of Contents Overview of Goals & Objectives Overview of uct Initial Circuit Board Characterization
More informationApplication Note 5363
Surface Laminar Circuit (SLC) Ball Grid Array (BGA) Lead-free Surface Mount Assembly Application Note 5363 Introduction This document outlines the design and assembly guidelines for surface laminar circuitry
More informationXilinx SSI Technology Concept to Silicon Development Overview
Xilinx SSI Technology Concept to Silicon Development Overview Shankar Lakka Aug 27 th, 2012 Agenda Economic Drivers and Technical Challenges Xilinx SSI Technology, Power, Performance SSI Development Overview
More informationAdvanced CSP & Turnkey Solutions. Fumio Ohyama Tera Probe, Inc.
Advanced CSP & Turnkey Solutions Fumio Ohyama Tera Probe, Inc. Tera Probe - Corporate Overview 1. Company : Tera Probe, Inc. 2. Founded : August, 2005 3. Capital : Approx. USD118.2 million (as of March
More informationMulti-Die Packaging How Ready Are We?
Multi-Die Packaging How Ready Are We? Rich Rice ASE Group April 23 rd, 2015 Agenda ASE Brief Integration Drivers Multi-Chip Packaging 2.5D / 3D / SiP / SiM Design / Co-Design Challenges: an OSAT Perspective
More informationSYSTEM IN PACKAGE AND FUNCTIONAL MODULE FOR MOBILE AND IoT DEVICE ASSEMBLY
SYSTEM IN PACKAGE AND FUNCTIONAL MODULE FOR MOBILE AND IoT DEVICE ASSEMBLY W. Koh, PhD Huawei Technologies JEDEC Mobile & IOT Forum Copyright 2017 Huawei Technologies, Ltd. OUTLINE Mobile and IoT Device
More informationUltra Fine Pitch RDL Development in Multi-layer ewlb (embedded Wafer Level BGA) Packages
Ultra Fine Pitch RDL Development in Multi-layer ewlb (embedded Wafer Level BGA) Packages Won Kyoung Choi*, Duk Ju Na*, Kyaw Oo Aung*, Andy Yong*, Jaesik Lee**, Urmi Ray**, Riko Radojcic**, Bernard Adams***
More informationIMEC CORE CMOS P. MARCHAL
APPLICATIONS & 3D TECHNOLOGY IMEC CORE CMOS P. MARCHAL OUTLINE What is important to spec 3D technology How to set specs for the different applications - Mobile consumer - Memory - High performance Conclusions
More informationLQFP. Thermal Resistance. Body Size (mm) Pkg. 32 ld 7 x 7 5 x ld 7 x 7 5 x ld 14 x 14 8 x ld 20 x x 8.5
LQFP Low Profile Quad Flat Pack Packages (LQFP) Amkor offers a broad line of LQFP IC packages designed to provide the same great benefits as MQFP packaging with a 1.4 mm body thickness. These packages
More informationAdvanced Heterogeneous Solutions for System Integration
Advanced Heterogeneous Solutions for System Integration Kees Joosse Director Sales, Israel TSMC High-Growth Applications Drive Product and Technology Smartphone Cloud Data Center IoT CAGR 12 17 20% 24%
More information----- Meeting Notes (10/8/13 10:34) The mobile market is driving growth and inovation in packaging.
----- Meeting Notes (10/8/13 10:34) ----- The mobile market is driving growth and inovation in packaging. 2 Mobile drives growth and the future of computing Dynamic of industry is quickly changing Devices
More informationNAN YA PCB CORPORATION COMPANY BRIEFING. March 2015 PAGE NYPCB, All Rights Reserved.
COMPANY BRIEFING March 2015 PAGE 1 Safe Harbor Notice Nan Ya PCB s statements of its current expectations are forward-looking statements subject to significant risks and uncertainties and actual results
More informationE-tec Socketing solutions for BGA, LGA, CGA, CSP, MLF & Gullwing chips
E-tec Socketing solutions for BGA, LGA, CGA, CSP, MLF & Gullwing chips Available contact styles: Elastomer interposers (10 Ghz & more) Probe pin sockets (generally below 5 Ghz) Other interposer styles
More information3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA
3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion
More informationChallenges of Integration of Complex FHE Systems. Nancy Stoffel GE Global Research
Challenges of Integration of Complex FHE Systems Nancy Stoffel GE Global Research Products drive requirements to sub-systems, components and electronics GE PRODUCTS CTQs: SWaP, $$, operating environment,
More informationNew Era of Panel Based Technology for Packaging, and Potential of Glass. Shin Takahashi Technology Development General Division Electronics Company
New Era of Panel Based Technology for Packaging, and Potential of Glass Shin Takahashi Technology Development General Division Electronics Company Connecting the World Connecting the World Smart Mobility
More informationBGA SSD with EMI Shielding
BGA SSD with EMI Shielding Jong-ok Chun Senior Managing Director Sun System Co.,Ltd www.sunsystem.kr rfjob@sunsysm.com, OCT-2017 Trend of SSD Form-Factor Form Factor - 2.5 Inch - Slim SATA 100x70mm 54x39mm
More informationPackaging Innovation for our Application Driven World
Packaging Innovation for our Application Driven World Rich Rice ASE Group March 14 th, 2018 MEPTEC / IMAPS Luncheon Series 1 What We ll Cover Semiconductor Roadmap Drivers Package Development Thrusts Collaboration
More informationTechnology Platform and Trend for SiP Substrate. Steve Chiang, Ph.D CSO of Unimicron Technology
Technology Platform and Trend for SiP Substrate Steve Chiang, Ph.D CSO of Unimicron Technology Contents Unimicron Introduction SiP Evolution Unimicron SiP platform - PCB, RF, Substrate, Glass RDL Connector.
More informationR R : R packaged in reel of 2000 couplers SMT HYBRID COUPLER GHZ Series : Coupler TECHNICAL DATA SHEET 1 / 5
TECHNICAL DATA SHEET 1 / 5 R41.211.502 R41.211.502 : R41.211.500 packaged in reel of 2000 couplers All dimensions are in mm. TECHNICAL DATA SHEET 2 / 5 R41.211.502 ELECTRICAL CHARACTERISTICS Specified
More informationAssembly Considerations for Linear Technology Module TM BGA Packages. July
Assembly Considerations for Linear Technology Module TM BGA Packages July 2012 Package Construction PCB Design Guidelines Outline Moisture Sensitivity, Pack, Ship & Bake Board Assembly Process Screen Print
More informationFrom Advanced Package to 2.5D/3D IC. Amkor Technology : Choon Lee
From Advanced Package to 2.5D/3D IC Amkor Technology : Choon Lee History says Low pin High pin & Integration As Multi-function pager City phone / PCS Feature Phone Smart Phone SOIC QFP PBGA Package-on-Package
More informationNear Term Solutions for 3D Memory Stacking (DRAM) Wael Zohni, Invensas Corporation
Near Term Solutions for 3D Memory Stacking (DRAM) Wael Zohni, Invensas Corporation 1 Contents DRAM Packaging Paradigm Dual-Face-Down (DFD) Package DFD-based 4R 8GB RDIMM Invensas xfd Technology Platform
More informationTechSearch International, Inc.
On the Road to 3D ICs: Markets and Solutions E. Jan Vardaman President TechSearch International, Inc. www.techsearchinc.com High future cost of lithography Severe interconnect delay Noted in ITRS roadmap
More informationLTCC (Low Temperature Co-fired Ceramic)
LTCC (Low Temperature Co-fired Ceramic) Design Guide Line. 381, Wonchun-Dong, Paldal-Ku, Suwon City, Kyung Ki-Do, Republic of Korea Tel : 82-31-217-2500 (Ext. 470) Fax : 82-31-217-7316 Homepage : http://www.pilkorcnd.co.kr
More informationOptimizing Flip Chip Substrate Layout for Assembly
Optimizing Flip Chip Substrate Layout for Assembly Pericles Kondos, Peter Borgesen, Dan Blass, and Antonio Prats Universal Instruments Corporation Binghamton, NY 13902-0825 Abstract Programs have been
More informationPatented socketing system for the BGA/CSP technology
Patented socketing system for the BGA/CSP technology Features: ZIF handling & only 40 grams per contact after closing the socket Sockets adapt to all package styles (at present down to 0.40mm pitch): Ceramic
More informationARCHIVE 2008 COPYRIGHT NOTICE
Keynote Speaker ARCHIVE 2008 Packaging & Assembly in Pursuit of Moore s Law and Beyond Karl Johnson Ph.D. Vice President and Senior Fellow Advanced Packaging Systems Integration Laboratory Freescale Semiconductor
More information2.5D FPGA-HBM Integration Challenges
2.5D FPGA-HBM Integration Challenges Jaspreet Gandhi, Boon Ang, Tom Lee, Henley Liu, Myongseob Kim, Ho Hyung Lee, Gamal Refai-Ahmed, Hong Shi, Suresh Ramalingam Xilinx Inc., San Jose CA Page 1 Presentation
More informationE. Jan Vardaman President & Founder TechSearch International, Inc.
J Wednesday 3/12/14 11:30am Kiva Ballroom TRENDS IN WAFER LEVEL PACKAGING: THIN IS IN! by E. Jan Vardaman President & Founder TechSearch International, Inc. an Vardaman, President and Founder of TechSearch
More informationStacked Silicon Interconnect Technology (SSIT)
Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation
More informationLEADLESS FLIP CHIP PLGA FOR NETWORKING APPLICATIONS
As originally published in the SMTA Proceedings LEADLESS FLIP CHIP PLGA FOR NETWORKING APPLICATIONS Andrew Mawer, Tara Assi, Steve Safai and Trent Uehling NXP Semiconductors N.V. Austin, TX, USA andrew.mawer@nxp.com
More informationFO-WLP: Drivers for a Disruptive Technology
FO-WLP: Drivers for a Disruptive Technology Linda Bal, Senior Analyst w w w. t e c h s e a r c h i n c. c o m Outline Industry drivers for IC package volumes WLP products and drivers Fan-in WLP FO-WLP
More informationWLSI Extends Si Processing and Supports Moore s Law. Douglas Yu TSMC R&D,
WLSI Extends Si Processing and Supports Moore s Law Douglas Yu TSMC R&D, chyu@tsmc.com SiP Summit, Semicon Taiwan, Taipei, Taiwan, Sep. 9 th, 2016 Introduction Moore s Law Challenges Heterogeneous Integration
More informationPackaging Technology of the SX-9
UMEZAWA Kazuhiko, HAMAGUCHI Hiroyuki, TAKEDA Tsutomu HOSAKA Tadao, NATORI Masaki, NAGATA Tetsuya Abstract This paper is intended to outline the packaging technology used with the SX-9. With the aim of
More informationTechSearch International, Inc.
Alternatives on the Road to 3D TSV E. Jan Vardaman President TechSearch International, Inc. www.techsearchinc.com Everyone Wants to Have 3D ICs 3D IC solves interconnect delay problem bandwidth bottleneck
More informationReliability Study of Bottom Terminated Components
Reliability Study of Bottom Terminated Components Jennifer Nguyen, Hector Marin, David Geiger, Anwar Mohammed, and Murad Kurwa Flextronics International 847 Gibraltar Drive Milpitas, CA, USA Abstract Bottom
More informationDirect Imaging Solutions for Advanced Fan-Out Wafer-Level and Panel-Level Packaging
Semicon Europe 2018 Direct Imaging Solutions for Advanced Fan-Out Wafer-Level and Panel-Level Packaging November 16, 2018 by Mark Goeke SCREEN SPE Germany GmbH 1 SCREEN Semiconductor s Target Market Target
More informationIT3D(M)-300S-BGA (37) Lead-Free THERMAL CYCLING TEST REPORT
TR066E-018 ITD(M)-00S-BGA (7) Lead-Free THERMAL CYCLING TEST REPORT - Post 6000 Cycles Report - APPROVED TY.ARAI Nov. 18, 009 CHECKED TM.MATSUO Nov. 17, 009 CHARGED TY.TAKADA Nov. 17, 009 HIROSE ELECTRIC
More informationARCHIVE Brandon Prior Senior Consultant Prismark Partners ABSTRACT
ARCHIVE IC PACKAGE MINIATURIZATION AND SYSTEM IN PACKAGE (SIP) TRENDS by Brandon Prior Senior Consultant Prismark Partners T ABSTRACT his brief packaging market overview presentation will provide a perspective
More informationThermal Management of Mobile Electronics: A Case Study in Densification. Hongyu Ran, Ilyas Mohammed, Laura Mirkarimi. Tessera
Thermal Management of Mobile Electronics: A Case Study in Densification Hongyu Ran, Ilyas Mohammed, Laura Mirkarimi Tessera MEPTEC Thermal Symposium: The Heat is On February 2007 Outline Trends in mobile
More informationHybrid Couplers 3dB, 90º Type PC2025A2100AT00
GENERAL DESCRIPTION The PC2025A2100AT00 is a RoHS compliant low profile wideband 3dB hybrid coupler which can support mobile applications, including PCS and DCS applications. The power coupler series of
More informationOver 5,000 products High Performance Adapters and Sockets Many Custom Designs Engineering Electrical and Mechanical ISO9001:2008 Registration
Overview Company Overview Over 5,000 products High Performance Adapters and Sockets Many Custom Designs Engineering Electrical and Mechanical ISO9001:2008 Registration Adapter Technology Overview Pluggable
More information3D technology evolution to smart interposer and high density 3D ICs
3D technology evolution to smart interposer and high density 3D ICs Patrick Leduc, Jean Charbonnier, Nicolas Sillon, Séverine Chéramy, Yann Lamy, Gilles Simon CEA-Leti, Minatec Campus Why 3D integration?
More informationAdapter Technologies
Adapter Technologies Toll Free: (800) 404-0204 U.S. Only Tel: (952) 229-8200 Fax: (952) 229-8201 email: info@ironwoodelectronics.com Introduction Company Overview Over 5,000 products High Performance Adapters
More informationPROCESSING RECOMMENDATIONS. For Samtec s SEAM8/SEAF8 Vertical Connectors
The method used to solder these high density connectors is the same as that used for many BGA devices even though there are some distinct structural differences. BGA s have spherical solder balls attached
More informationDesign and Assembly Process Implementation for BGAs
ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Design and Assembly Process Implementation for BGAs Developed by the Device Manufacturers Interface Committee of IPC October 25, 2000 Users of this standard
More informationTechSearch International, Inc.
Silicon Interposers: Ghost of the Past or a New Opportunity? Linda C. Matthew TechSearch International, Inc. www.techsearchinc.com Outline History of Silicon Carriers Thin film on silicon examples Multichip
More information3D-IC is Now Real: Wide-IO is Driving 3D-IC TSV. Samta Bansal and Marc Greenberg, Cadence EDPS Monterey, CA April 5-6, 2012
3D-IC is Now Real: Wide-IO is Driving 3D-IC TSV Samta Bansal and Marc Greenberg, Cadence EDPS Monterey, CA April 5-6, 2012 What the fuss is all about * Source : ECN Magazine March 2011 * Source : EDN Magazine
More informationJapanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left?
Japanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left? Liquid Design Systems, Inc CEO Naoya Tohyama Overview of this presentation Those slides
More informationCustom Connectors Overview
Company Overview March 12, 2015 Custom Connectors Overview Tuesday, October 03, 2017 CONNECTOR OVERVIEW Engineering Manufacturing Connector Products HiLo FlexFrame Custom Connectors Standard Connectors
More information>Introduction Ibiden Products Over View and Technology Trend. Embedding technology and Expectation.
Agenda >Introduction Ibiden Products Over View and Technology Trend. Embedding technology and Expectation. >Embedded Device Technology #1. Embedded MLCC in FCCSP Substrate. #2. Embedded Active Device.
More informationPackaging of Selected Advanced Logic in 2x and 1x nodes. 1 I TechInsights
Packaging of Selected Advanced Logic in 2x and 1x nodes 1 I TechInsights Logic: LOGIC: Packaging of Selected Advanced Devices in 2x and 1x nodes Xilinx-Kintex 7XC 7 XC7K325T TSMC 28 nm HPL HKMG planar
More informationSocket Technologies
Socket Technologies Introduction Company Overview Over 5,000 products High Performance Adapters and Sockets Many Custom Designs Engineering Electrical and Mechanical ISO9001:2008 Registration Socket Technology
More informationNon-destructive, High-resolution Fault Imaging for Package Failure Analysis. with 3D X-ray Microscopy. Application Note
Non-destructive, High-resolution Fault Imaging for Package Failure Analysis with 3D X-ray Microscopy Application Note Non-destructive, High-resolution Fault Imaging for Package Failure Analysis with 3D
More informationULL0402FC05C. Description. Mechanical characteristics PIN CONFIGURATION. SMART Phones Portable Electronics SMART Cards
LOW CAPACITANCE unbumped flip chip tvs array Description The ULLC0402FC05C Flip Chip employs advanced silicon P/N junction technology for unmatched board-level transient voltage protection against Electrostatic
More informationKeynote Speaker. Matt Nowak Senior Director Advanced Technology Qualcomm CDMA Technologies
Keynote Speaker Emerging High Density 3D Through Silicon Stacking (TSS) What s Next? Matt Nowak Senior Director Advanced Technology Qualcomm CDMA Technologies 8 Emerging High Density 3D Through Silicon
More informationSolder Reflow Guide for Surface Mount Devices
April 2008 Introduction Technical Note TN1076 This technical note provides general guidelines for a solder reflow and rework process for Lattice surface mount products. The data used in this document is
More information0.635mm Pitch S.O. DIMM Socket
0.635mm Pitch S.O. DIMM Socket SX1 Series Variation in Mounting Height Low Profile Type (Mounting Height: 4.0mm) Standard Type (Mounting Height: 5.5mm) Features 1. 72pos. Small Outline DIMM Socket SX1
More information3D & Advanced Packaging
Tuesday, October 03, 2017 Company Overview March 12, 2015 3D & ADVANCED PACKAGING IS NOW WITHIN REACH WHAT IS NEXT LEVEL INTEGRATION? Next Level Integration blends high density packaging with advanced
More information0.4 mm Contact Pitch Board-to-Board /Board-to-FPC Connectors
.4 mm Contact Pitch Board-to-Board /Board-to-FPC Connectors DF4 Series Decrease in the board-occupied area Smaller width Other HRS connector DF4 3.38mm 5.mm Features 1. Higher density of the board-mounted
More informationTHERMAL EXPLORATION AND SIGN-OFF ANALYSIS FOR ADVANCED 3D INTEGRATION
THERMAL EXPLORATION AND SIGN-OFF ANALYSIS FOR ADVANCED 3D INTEGRATION Cristiano Santos 1, Pascal Vivet 1, Lee Wang 2, Michael White 2, Alexandre Arriordaz 3 DAC Designer Track 2017 Pascal Vivet Jun/2017
More informationInterconnect Challenges in a Many Core Compute Environment. Jerry Bautista, PhD Gen Mgr, New Business Initiatives Intel, Tech and Manuf Grp
Interconnect Challenges in a Many Core Compute Environment Jerry Bautista, PhD Gen Mgr, New Business Initiatives Intel, Tech and Manuf Grp Agenda Microprocessor general trends Implications Tradeoffs Summary
More informationThe Road to the AMD. Fiji GPU. Featuring Die Stacking and HBM Technology 1 THE ROAD TO THE AMD FIJI GPU ECTC 2016 MAY 2015
The Road to the AMD Fiji GPU Featuring Die Stacking and HBM Technology 1 THE ROAD TO THE AMD FIJI GPU ECTC 2016 MAY 2015 Fiji Chip DETAILED LOOK 4GB High-Bandwidth Memory 4096-bit wide interface 512 GB/s
More informationApplication Note AN-1028 Design, Integration and Rework Guidelines for BGA and LGA Packages
Application Note AN-1028 Design, Integration and Rework Guidelines for BGA and LGA Packages Table of Contents Page Design considerations...2 Substrate...2 PCB layout...2 Solder mask openings...3 Terminations...4
More informationDRAM Memory Modules Overview & Future Outlook. Bill Gervasi Vice President, DRAM Technology SimpleTech
DRAM Memory Modules Overview & Future Outlook Bill Gervasi Vice President, DRAM Technology SimpleTech bilge@simpletech.com Many Applications, Many Configurations 2 Module Configurations DDR1 DDR2 Registered
More informationSocket Technologies
Socket Technologies Toll Free: (800) 404-0204 U.S. Only Tel: (952) 229-8200 Fax: (952) 229-8201 email: info@ironwoodelectronics.com Introduction Company Overview Over 5,000 products High Performance Adapters
More informationIoT, Wearable, Networking and Automotive Markets Driving External Memory Innovation Jim Cooke, Sr. Ecosystem Enabling Manager, Embedded Business Unit
IoT, Wearable, Networking and Automotive Markets Driving External Memory Innovation Jim Cooke, Sr. Ecosystem Enabling Manager, Embedded Business Unit JCooke@Micron.com 2016Micron Technology, Inc. All rights
More informationAssembly Considerations for Analog Devices Inc., µmodule TM LGA Packages AUGUST 2018
Assembly Considerations for Analog Devices Inc., µmodule TM LGA Packages AUGUST 2018 1 Outline Outline Package Construction PCB Design Guidelines Moisture Sensitivity, Pack, Ship & Bake Board Assembly
More informationAchieving GHz Speed in Socketed BGA Devices
IC INTERCONNECT TOPIC #102 Technical Information from Ironwood Electronics Achieving GHz Speed in Socketed BGA Devices Ila Pal Director of R&D Ironwood Electronics Background For many products designed
More informationDesigning for the Next Smart Device
Designing for the Next Smart Device Elad Baram Director, Product Marketing, Mobile & Connected Solutions, SanDisk January 9, 2014 JEDEC at CES 2014 Copyright 2014 Forward-Looking Statements.During our
More informationSP5001 Series 4 Channel Common Mode Filter with ESD Protection
Low Capacitance ESD Protection - SP51 Series SP51 Series 4 Channel Common Mode Filter with ESD Protection RoHS Pb GREEN Description The SP51 Series is a highly integrated Common Mode Filter (CMF) providing
More informationLGA vs. BGA: WHAT IS MORE RELIABLE? A2 nd LEVEL RELIABILITY COMPARISON
LGA vs. BGA: WHAT IS MORE RELIABLE? A2 nd LEVEL RELIABILITY COMPARISON Ahmer Syed and Robert Darveaux Amkor Technology 1900 S. Price Road Chandler, AZ 85226 (480)821-5000 asyed@amkor.com ABSTRACT A recent
More informationBGA Socketing Systems
DATA BOOK BGA-TECH04 (REV. 3/04) BGA Socketing Systems Search for a footprint or build a part number online at www.bgasockets.com Solutions for Virtually Any BGA Application BGA Socket Adapter System Designed
More informationSamsung emcp. WLI DDP Package. Samsung Multi-Chip Packages can help reduce the time to market for handheld devices BROCHURE
Samsung emcp Samsung Multi-Chip Packages can help reduce the time to market for handheld devices WLI DDP Package Deliver innovative portable devices more quickly. Offer higher performance for a rapidly
More informationTrend of Advanced SiP Technology Development
Sep. 14 '06 SSCS Kansai Trend of Advanced SiP Technology Development Renesas Technology Corp. System Solution Business Group Takafumi Kikuchi 2006. Renesas Technology Corp., All rights reserved. Rev. 1.00
More informationEM8D-100L EMI FILTER/TVS ARRAY DESCRIPTION DFN-16 PACKAGE FEATURES APPLICATIONS MECHANICAL CHARACTERISTICS CIRCUIT DIAGRAM & PIN CONFIGURATION
EMI FILTER/TVS ARRAY DESCRIPTION The is a DFN-16, 8 line low pass filter array with integrated TVS diodes. The is designed to suppress unwanted EMI/RFI signals and provide ESD protection for high-speed
More informationPCB Assembly System Set Up for Pop. Gerry Padnos. E mail: smt.com
Juki Automation Systems, Inc 507 Airport Blvd. Morrisville, NC 27560 (919) 460 0111 www.jukiamericas.com Gerry Padnos PCB Assembly System Set Up for Pop Gerry Padnos Juki Automation Systems, Inc., 507
More informationAdvanced Wafer Level Technology: Enabling Innovations in Mobile, IoT and Wearable Electronics
Advanced Wafer Level Technology: Enabling Innovations in Mobile, IoT and Wearable Electronics Seung Wook Yoon, *Boris Petrov, **Kai Liu STATS ChipPAC Ltd. 10 #04-08/09 Techpoint Singapore 569059 *STATS
More informationMeet requirements of USB 2.0
NEW Meet requirements of USB.0 UX Series Features 1. Certified to perform as required in USB.0 Standard Tested and certified by USB Association approved laboratory the connectors will perform at transmission
More informationChapter 1 Introduction of Electronic Packaging
Chapter 1 Introduction of Electronic Packaging 1 Introduction of Electronic Packaging 2 Why Need Package? IC Foundry Packaging house Module Sub-system Product 3 Concept of Electric Packaging 4 Moore s
More informationBurn-in & Test Socket Workshop
Burn-in & Test Socket Workshop IEEE March 4-7, 2001 Hilton Mesa Pavilion Hotel Mesa, Arizona IEEE COMPUTER SOCIETY Sponsored By The IEEE Computer Society Test Technology Technical Council COPYRIGHT NOTICE
More information