Assignment For Fresh (Session ) admitted students of Odd Semester PGDCA/M.Sc Computer Science/ MCA (Through Distance Education)
|
|
- Dulcie Wilkins
- 5 years ago
- Views:
Transcription
1 Assignment For Fresh (Session ) admitted students of Odd Semester PGDCA/M.Sc Computer Science/ MCA (Through Distance Education) For session Directorate of Distance Education Guru Jambeshwar University of Science & Technology, Hisar
2 Course: Introduction to IT Semester: 1st. Code: MS-01 Total Marks=20. Q1. How does computer works. Differentiate between software and hardware. Q2. Define programming language and their types with example. Q3. Explain any two: - i. Open source software ii. Projection and Parallelism iii. GUI-Windows I Q1. What is computer network? Explain different types of network protocols? Q2. Write short note on: - i. Ensuring integrity ii. National level weather forecasting Q3. What do you mean by OOPS? Explain functions of OOPS. By: Vinod Goyal Asst. Professor CSE(DDE)
3 Course: Computer Programming and Problem Solving Semester: 1st. Code: MS-02 Total Marks=20 Q1. Explain algorithm and flow chart with an example? Q2. Discuss about preprocessor and input output methods with a suitable example? Q3. Write a program for given structure: - * * * * * * * * * I Q1. Discuss about file handling and their methods. Write a program to count the total no of character in a text file. Q2. What is pointer? Write a program for array of pointer. Q3. Difference between structure and union. By: Vinod Goyal Asst. Professor CSE(DDE)
4 Course: Digital Electronics Code: MS-03 Semester: 1st Total Marks=20 ASSIGNMENT 1 Q 1. Write schematic diagram of various Logic gates with truth tables. Q 2. Minimize and realize the following function using K-Maps ff (A,B,C,D) = m(4,6,8,10,11,12,15) + d(3,5,7,9) Q 3. Explain D/A & A/D converters in details. ASSIGNMENT 2 Q 1. Write short note on the following: a) Encoder & Decoder b) Adder & Subtractor Q 2. What are counters? Explain Synchronous & Asynchronous Counter in details. Q 3. Explain the various characteristics of digital IC s in details. Prepared By: Vinod Kumar Assistant Professor Deptt. of ECE
5 Course: System Analysis and Design Sem.:1st Code: MS-04 Total Marks=20 : Q.1. Draw a DFD diagram of College library system up to level 2. Q.2. State the activities involved in Object-Oriented Development Life Cycle. Q.3. Explain Output Format types: Tabular format, Graphical format, Detailed Reports and Summary Reports with proper diagram and format. I Q.1. What is Output? Explain output objectives, Output types and Key Output questions in detail. Q.2. Differentiate between physical and abstract system. Q.3. What fact-finding techniques would use for investigating the information requirement of a large organization? Prepared By: Sunil Verma Assistant Professor Dept. of CSE
6 Course: Relational Database Management System Semester: 3 rd. Code: MS-11 Total Marks=20 Q1. Explain the followings: - i. Data Model. ii. Data modeling using E-R Model with a suitable example. Q2. Define normalization rules and their types with a proper table. Q3. Difference between the followings with examples: - i. Primary Key. ii. Forgan key. iii. Alternate key. iv. Candidate key. I Q1. Define Client-server Architecture with diagram. Give an example of client server architecture and explain it. Q2. Explain the followings:- i. Fragmentation, Replication and Allocation Techniques ii. Recovery Techniques. iii. Concurrency control Techniques. By: Mohit Asst. Professor(Cont.) Deptt. of CS(DDE)
7 Course: Software Engineering Semester: 3 rd Code: MS-12 Total Marks=20 Q.1 Company needs to develop a strategy for software product development for which it has a choice of two programming languages L1 and L2. The number of lines of code (LOC) developed using L2 is estimated to be twice the LOC developed with Ll. The product will have to be maintained for five years. Various parameters for the company are given in the table below. Parameter Language L1 Language L2 Man years needed for development LOC/10000 LOC/10000 Development cost per man year Rs. 10,00,000 Rs. 7,50,000 Maintenance time 5 years 5 years Cost of maintenance per year Rs. 1,00,000 Rs. 50,000 Total cost of the project includes cost of development and maintenance. What is the LOC for L1 for which the cost of the project using L1 is equal to the cost of the project using L2? Q.2 What is software Metrics. Explain McCabe s Cyclometic Complexity? Q.3 Describe different phases of software development. Explain COCOMO model?
8 I Q.1 A company needs to develop digital signal processing software for one of its newest inventions. The software is expected to have lines of code. The company needs to determine the effort in person-months needed to develop this software using the basic COCOMO model. The multiplicative factor for this model is given as 2.8 for the software development on embedded systems, while the exponentiation factor is given as What is the estimated effort in person-months? Q.2 Explain different type of software testing? Q.3 Describe the concept of software reliability. Explain different types of reliability models? Prepared By: Ashwani Kumar Assistant Professor Deptt.of DDE
9 Course: Computer Graphics Semester: 3 rd. Code: MS-13 Total Marks=20 Q1. List three graphic hard copy devices for each one briefly explain? i. How it works. ii. Its advantages and limitations. Q2. Explain Bresenhan s line algorithm and derivation of algorithm. Q3. Explain mid-point algorithm? Write algorithm in your own words. I Q1. Discuss about geometric transformation. Why we use inverse geometric transformation? Q2. Why The Cohen-Sutherland Line Clipping algorithm is used? And explain it. Q3 Explain projection & their types with example. By:Mohit Asst. Professor(Cont.) Deptt. of CS(DDE)
10 Course: Management information System Semester: 3 rd. Code: MS-14 Total Marks=20 Q1. Explain meaning of MIS. Explain it s different components. Q2. Explain the relationship between MIS and management activities. Q3. How decisions are made in MIS and explain different method of it. I Q1. What are the efficiency criteria for MIS? What do you mean by effectiveness of MIS? Q2. Explain different method and tools to develop information system. How modification are made in MIS. Q3. What are the requirements of MIS and list different need of it? What are the advantages of MIS? By:Mohit Asst. Professor(Cont.) Deptt. of CS(DDE)
11 Course: Data Warehousing and Data Mining Sem.: 5 th. Code: MS-31 Total Marks=20 Q.1 Explain data warehouse implementation process in detail? Q.2 Explain Data mining Architecture. Explain Applications and Issues related to Data mining? Q.3 How we compute ranking cubes for efficient top-k ranking? Can you give example of one application domain where ranking cubes are used? I Q.1 Explain the Data Preparation.Explain the different steps of Data preparation? Q.2Difference between classification of data and clustering of data, you are required to give your opinion about it with any example of your choice Q.3 Can apriori mining algorithm handle convertible constraints? Justify. Prepared By: Ashwani Kumar Assistant Professor Deptt.of DDE
12 Course: C Sharp (C#) Programming Semester: 3 rd Code: MS-32 Total Marks=20 Q1 Explain followings in briefly: - i. Virtual Object System. ii. Next Generation Windows Service. iii. Difference b/w data overriding and over hiding. Q2. Write a Program to Check Whether the Entered Year is a Leap Year or Not. Q3. Write a Program to Find the Frequency of the Word the in any Sentence. I Q1. Discuss about exception handling with proper example which covers these keywords try, catch and finally. Q2. Write a Program to Print a Diamond Using Nested Loop. Q3. Explain followings in briefly with example: - i. Inheritance & Polymorphism. ii. Usage of preprocessor. iii. Code Access Security. By:Mohit Asst. Professor(Cont.) Deptt. of CS(DDE)
13 Course: Advanced Computer Architecture Sem.: 5th. Code: MS-33 Total Marks=20 Q.1 Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3,, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is? Q.2 Explain Page replacement policies with example? Q.3 Explain different Cache addressing modes with example? I Q.1 A computer has a 256 Kbyte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is? Q.2 what is the difference between linear and non-linear pipeline. Explain RISC and CISC? Q.3 Explain Snoopy bus protocol-write back vs. write through policy? Prepared By: Ashwani Kumar Assistant Professor Deptt.of DDE
14 Course: High Speed Networks Sem.: 5th. Code: MS-34 Total Marks=20 Q.1 Determine the maximum length of the cable (in km) for transmitting data at a rate of 500 Mbps in an Ethernet LAN with frames of size 10,000 bits. Assume the signal speed in the cable to be 2,00,000 km/s. Q.2 Describe Protocol mapping. Explain different layer of fibre channel? Q.3Explain the flowing terms (a)dsl (Digital Subscriber Line) (b) ADSL (Asymmetric Digital Subscriber Line) I Q.1 Frames of 1000 bits are sent over a 10^6 bps duplex link between two hosts. The propagation time is 25ms. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the minimum number of bits (i) that will be required to represent the sequence numbers distinctly? Assume that no time gap needs to be given between transmissions of two frames. Q.2 Explain the flowing terms (a)hdsl (High bit rate digital subscriber line) Subscriber Line) (b)vdsl (Very High bit rate Digital Q.3 Explain the Management System for High Speed Network? Prepared By: Ashwani Kumar Assistant Professor Deptt.of DDE
Assignment For Fresh (Session ) admitted students Of MCA 5-year (Through Distance Education)
Assignment For Fresh (Session 2018-2019) admitted students Of MCA 5-year (Through Distance Education) For session 2018-2019 Directorate of Distance Education Guru Jambeshwar University of Science & Technology,
More informationAssignment For Promote (Session ) students Of MCA 5-year (Through Distance Education)
Assignment For Promote (Session 2018-2019) students Of MCA 5-year (Through Distance Education) For session 2018-2019 Directorate of Distance Education Guru Jambeshwar University of Science & Technology,
More informationPRACTICAL LIST FOR ODD SEMESTERS Session (PGDCA/MCA/MSC (CS))
GURU JAMBHESHWAR UNIVERSITY OF SCIENCE & TECHNOLOGY, HISAR DIRECTORATE OF DISTANCE EDUCATION PRACTICAL LIST FOR ODD SEMESTERS Session 2015-16 (PGDCA/MCA/MSC (CS)) SEMSTER 1 st Programme: PGDCA/MCA/MSC
More informationList of Practical for Master in Computer Application (5 Year Integrated) (Through Distance Education)
List of Practical for Master in Computer Application (5 Year Integrated) (Through Distance Education) Directorate of Distance Education Guru Jambeshwar University of Science & Technology, Hissar First
More information(3 Hours) N.B. (1) Question No. 1 is compulsory. (2) Attempt any four from the remaining six questions. (3) Figures to the right indicate full marks.
Q. P. Code: 30990 (3 Hours) Total Marks: 0 N.B. (1) Question No. 1 is compulsory. (2) Attempt any four from the remaining six questions. (3) Figures to the right indicate full marks. Q.1 (a) What is flowchart?
More informationDBMS Lesson Plan. Name of the faculty: Ms. Kavita. Discipline: CSE. Semester: IV (January-April 2018) Subject: DBMS (CSE 202-F)
DBMS Lesson Plan Name of the faculty: Ms. Kavita Discipline: CSE Semester: IV (January-April 2018) Subject: DBMS (CSE 202-F) Week No Lecture Day Topic (including assignment/test) 1 1 Introduction to Database
More informationComputer organization by G. Naveen kumar, Asst Prof, C.S.E Department 1
Pipelining and Vector Processing Parallel Processing: The term parallel processing indicates that the system is able to perform several operations in a single time. Now we will elaborate the scenario,
More informationSESSION M12-S12 INTERNAL ASSIGNMENT
MASTER OF COMPUTER APPLICATIONS RELATIONAL DATABASE MENAGEMENT SYSTEM PAPER CODE: MCA-401 SECTION-A Answer the following questions in around 100 words. 1. What are the differences between simple and composite
More informationCPU Structure and Function
CPU Structure and Function Chapter 12 Lesson 17 Slide 1/36 Processor Organization CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Lesson 17 Slide 2/36 CPU With Systems
More informationEast Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 2 for Fall Semester, 2007
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 2 for Fall Semester, 2007 Read
More informationWilliam Stallings Computer Organization and Architecture
William Stallings Computer Organization and Architecture Chapter 11 CPU Structure and Function Rev. 3.2.1 (2005-06) by Enrico Nardelli 11-1 CPU Functions CPU must: Fetch instructions Decode instructions
More informationEast Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 3 for Fall Semester, 2005
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 3 for Fall Semester, 2005 Section
More informationOld Question Papers of PGDCA 1 st Semester H.K. Hi-Tech (College of IT & Management) H.K. Hi-Tech College of IT & Management
() Q.1 (a) What is a computer system? What are the various components of a CPU? Also explain its working. (b) What are the things that computers can do? Also explain the various characteristics of computers?
More informationii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034
No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics - I SECTION-A Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)
More informationPART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers.
Set No. 1 IV B.Tech I Semester Supplementary Examinations, March - 2017 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks:
More informationECE 341 Final Exam Solution
ECE 341 Final Exam Solution Time allowed: 110 minutes Total Points: 100 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE.
More informationHonorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore
COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science
More informationSyllabus for Computer Science General Part I
Distribution of Questions: Part I Q1. (Compulsory: 20 marks). Any ten questions to be answered out of fifteen questions, each carrying two marks (Group A 3 questions, Group B, Group C and Group D 4 questions
More informationBSc. (Hons) Web Technologies. Examinations for 2017 / Semester 1
BSc. (Hons) Web Technologies Cohort: BWT/17A/FT Examinations for 2017 / Semester 1 MODULE: NETWORK ESSENTIALS MODULE CODE: CAN 1104C Duration: 2 ½ hours Instructions to Candidates: 1. Answer ALL 4 (four)
More informationJNTUWORLD. 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15]
Code No: 09A50402 R09 Set No. 2 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15] 2. (a) Discuss asynchronous serial transfer concept? (b) Explain in
More informationUNIT II SYSTEM BUS STRUCTURE 1. Differentiate between minimum and maximum mode 2. Give any four pin definitions for the minimum mode. 3. What are the pins that are used to indicate the type of transfer
More information(Following Paper ID and Roll No. to be filled by the student in the Answer Book)
F:/Academic/27 Refer/WI/ACAD/10 SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGG. & MANAGEMENT PAPER ID: 1602 (Following Paper ID and Roll No. to be filled by the student in the Answer Book) Roll No. B.Tech. SEM
More informationCSE A215 Assembly Language Programming for Engineers
CSE A215 Assembly Language Programming for Engineers Lecture 4 & 5 Logic Design Review (Chapter 3 And Appendices C&D in COD CDROM) September 20, 2012 Sam Siewert ALU Quick Review Conceptual ALU Operation
More informationPost Graduate Diploma in Computer Applications I Semester INTERNAL ASSIGNMENT QUESTIONS (November, 2017)
Post Graduate Diploma in Computer Applications I Semester INTERNAL ASSIGNMENT QUESTIONS (November, 2017) DIRECTOR Prof. SHIVARAJ PROF. G. RAM REDDY CENTRE FOR DISTANCE EDUCATION (RECOGNISED BY THE DISTANCE
More informationKeywords and Review Questions
Keywords and Review Questions lec1: Keywords: ISA, Moore s Law Q1. Who are the people credited for inventing transistor? Q2. In which year IC was invented and who was the inventor? Q3. What is ISA? Explain
More informationComputer Organization
A Text Book of Computer Organization and Architecture Prof. JATINDER SINGH Director, GGI, Dhaliwal Er. AMARDEEP SINGH M.Tech (IT) AP&HOD, Deptt.of CSE, SVIET, Banur Er. GURJEET SINGH M.Tech (CSE) Head,
More informationGet Unique study materials from
Downloaded from www.rejinpaul.com VALLIAMMAI ENGNIEERING COLLEGE SRM Nagar, Kattankulathur 603203. DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Year & Semester : IV Section : EEE - 1 & 2 Subject Code
More informationTotal No. of Questions : 18] [Total No. of Pages : 02. M.Sc. DEGREE EXAMINATION, DEC First Year INFORMATION TECHNOLOGY.
(DMSIT01) Total No. of Questions : 18] [Total No. of Pages : 02 M.Sc. DEGREE EXAMINATION, DEC. 2016 First Year INFORMATION TECHNOLOGY Basics of IT Time : 3 Hours Maximum Marks : 70 Section - A (3 x 15
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) UNIT-I
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : CO (16MC802) Year & Sem: I-MCA & I-Sem Course & Branch: MCA Regulation:
More informationCS304,EC304,DCSE16, DETE16
CS304,EC304,DCSE16, DETE16 III SEMESTER DIPLOMA EXAMINATION, JANUARY-2013 MICROPROCESSOR Time: 3 Hours Max. Marks: 75 GROUP A : Answer any three questions. (Question No. 1 is compulsory) Q.1 What do you
More informationINTRODUCTION OF MICROPROCESSOR& INTERFACING DEVICES Introduction to Microprocessor Evolutions of Microprocessor
Course Title Course Code MICROPROCESSOR & ASSEMBLY LANGUAGE PROGRAMMING DEC415 Lecture : Practical: 2 Course Credit Tutorial : 0 Total : 5 Course Learning Outcomes At end of the course, students will be
More informationMLR INSTITUTE OF TECHNOLOGY DUNDIGAL , HYDERABAD QUESTION BANK
MLR INSTITUTE OF TECHNOLOGY DUNDIGAL - 500 043, HYDERABAD QUESTION BANK Course Name : EMBEDDED SYSTEMS Course Code : A57043 Class : IV B. Tech I Semester Branch : ECE Year : 2015 2016 Course Faculty :
More informationG.PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY
G.PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY Pasupala(V), Nadikotkur Road, Kurnool-518002 www.gpcet.ac.in DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING II B.TECH II Semester II (2017-2018)
More information5. (a) What is secondary storage? How does it differ from a primary storage? (b) Explain the functions of (i) cache memory (ii) Register
General Concepts 1. (a) What are combinational circuits? (b) Perform the following: (i) Convert (0.5625) 10 = ( ) 2 (ii) (010010) 2 (100011) 2 = ( ) 2 2. (a) Using truth table prove that A B= A+ B (b)
More informationREDUCED INSTRUCTION SET COMPUTERS (RISC)
Datorarkitektur Fö 5/6-1 Datorarkitektur Fö 5/6-2 What are RISCs and why do we need them? REDUCED INSTRUCTION SET COMPUTERS (RISC) RISC architectures represent an important innovation in the area of computer
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA
More informationTime: 3 hours. Full Marks: 70. The figures in the margin indicate full marks. Answers from all the Groups as directed. Group A.
COPYRIGHT RESERVED End Sem (V) MCA (XXVIII) 2017 Time: 3 hours Full Marks: 70 Candidates are required to give their answers in their own words as far as practicable. The figures in the margin indicate
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More informationCS6303-COMPUTER ARCHITECTURE UNIT I OVERVIEW AND INSTRUCTIONS PART A
CS6303-COMPUTER ARCHITECTURE UNIT I OVERVIEW AND INSTRUCTIONS 1. Define Computer Architecture 2. Define Computer H/W 3. What are the functions of control unit? 4. 4.Define Interrupt 5. What are the uses
More informationECE 486/586. Computer Architecture. Lecture # 7
ECE 486/586 Computer Architecture Lecture # 7 Spring 2015 Portland State University Lecture Topics Instruction Set Principles Instruction Encoding Role of Compilers The MIPS Architecture Reference: Appendix
More informationEND-TERM EXAMINATION
(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationCS 351 Final Exam Solutions
CS 351 Final Exam Solutions Notes: You must explain your answers to receive partial credit. You will lose points for incorrect extraneous information, even if the answer is otherwise correct. Question
More informationCHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1
CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1 Data representation: (CHAPTER-3) 1. Discuss in brief about Data types, (8marks)
More informationCPU Structure and Function
Computer Architecture Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com http://www.yildiz.edu.tr/~naydin CPU Structure and Function 1 2 CPU Structure Registers
More informationBCA (Part II) EXAMINATION 2008 C++ PROGRAMMING Max Time : 3 Hours Max. Marks : 50
C++ PROGRAMMING 1. (a) What are the characteristics of object-oriented language? What are the advantages of using OOPS? (b) What are the Application of Public, Private, and Protected keywords? Explain.
More informationSIR C R REDDY COLLEGE OF ENGINEERING
SIR C R REDDY COLLEGE OF ENGINEERING DEPARTMENT OF INFORMATION TECHNOLOGY Course Outcomes II YEAR 1 st SEMESTER Subject: Data Structures (CSE 2.1.1) 1. Describe how arrays, records, linked structures,
More informationBEng (Hons.) Telecommunications. BSc (Hons.) Computer Science with Network Security
BEng (Hons.) Telecommunications BSc (Hons.) Computer Science with Network Security Cohorts: BTEL/15B/FT BCNS/16B/FT Examinations for 2016-2017 / Semester 2 Resit Examinations for BTEL/13B/FT & BTEL/15B/FT
More informationRISC & Superscalar. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 12. Instruction Pipeline no hazard.
COMP 212 Computer Organization & Architecture Pipeline Re-Cap Pipeline is ILP -Instruction Level Parallelism COMP 212 Fall 2008 Lecture 12 RISC & Superscalar Divide instruction cycles into stages, overlapped
More informationMain Points of the Computer Organization and System Software Module
Main Points of the Computer Organization and System Software Module You can find below the topics we have covered during the COSS module. Reading the relevant parts of the textbooks is essential for a
More informationmrrj izns k jktf kz V.Mu eqdr fo ofo ky;]bykgkckn
dk;zdze vf/ku;kl सत र 2018-19 Course Code: PGDCA-01 Discrete Mathematics 1. Answer the following: a. Out of 7 consonants and 4 vowels, how many words of 3 consonants and 2 vowels can be formed? b. In a
More informationCache Controller with Enhanced Features using Verilog HDL
Cache Controller with Enhanced Features using Verilog HDL Prof. V. B. Baru 1, Sweety Pinjani 2 Assistant Professor, Dept. of ECE, Sinhgad College of Engineering, Vadgaon (BK), Pune, India 1 PG Student
More informationNOW Handout Page 1. Review from Last Time #1. CSE 820 Graduate Computer Architecture. Lec 8 Instruction Level Parallelism. Outline
CSE 820 Graduate Computer Architecture Lec 8 Instruction Level Parallelism Based on slides by David Patterson Review Last Time #1 Leverage Implicit Parallelism for Performance: Instruction Level Parallelism
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationDr. Rafiq Zakaria Campus. Maulana Azad College of Arts, Science & Commerce, Aurangabad. Department of Computer Science. Academic Year
Dr. Rafiq Zakaria Campus Maulana Azad College of Arts, Science & Commerce, Aurangabad Department of Computer Science Academic Year 2015-16 MCQs on Operating System Sem.-II 1.What is operating system? a)
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF COMPUTER SCIENCE ENGINEERING EC6504 MICROPROCESSOR AND MICROCONTROLLER YEAR / SEMESTER: II / IV ACADEMIC YEAR: 2015-2016 (EVEN
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital
Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CP7204 Advanced Operating Systems Regulation 2013 Academic Year
More informationCS146 Computer Architecture. Fall Midterm Exam
CS146 Computer Architecture Fall 2002 Midterm Exam This exam is worth a total of 100 points. Note the point breakdown below and budget your time wisely. To maximize partial credit, show your work and state
More informationFinal Exam Fall 2007
ICS 233 - Computer Architecture & Assembly Language Final Exam Fall 2007 Wednesday, January 23, 2007 7:30 am 10:00 am Computer Engineering Department College of Computer Sciences & Engineering King Fahd
More informationComputer Organization (Autonomous)
2-7-27 Computer Organization (Autonomous) UNIT IV Sections - A & D SYLLABUS The Memory System: Memory Hierarchy, - RAM and ROM Chips, Memory Address Maps, Memory Connection to, Auxiliary Magnetic Disks,
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationChapter 13 Reduced Instruction Set Computers
Chapter 13 Reduced Instruction Set Computers Contents Instruction execution characteristics Use of a large register file Compiler-based register optimization Reduced instruction set architecture RISC pipelining
More informationComputer Organisation CS303
Computer Organisation CS303 Module Period Assignments 1 Day 1 to Day 6 1. Write a program to evaluate the arithmetic statement: X=(A-B + C * (D * E-F))/G + H*K a. Using a general register computer with
More informationModule 4c: Pipelining
Module 4c: Pipelining R E F E R E N C E S : S T A L L I N G S, C O M P U T E R O R G A N I Z A T I O N A N D A R C H I T E C T U R E M O R R I S M A N O, C O M P U T E R O R G A N I Z A T I O N A N D A
More informationUNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Computer Architecture ECE 568
UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 568 Sample Midterm I Questions Israel Koren ECE568/Koren Sample Midterm.1.1 1. The cost of a pipeline can
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING QUESTION BANK VI SEMESTER EE6602 EMBEDDED SYSTEMS Regulation 2013 Academic Year
More informationS = 32 2 d kb (1) L = 32 2 D B (2) A = 2 2 m mod 4 (3) W = 16 2 y mod 4 b (4)
1 Cache Design You have already written your civic registration number (personnummer) on the cover page in the format YyMmDd-XXXX. Use the following formulas to calculate the parameters of your caches:
More informationInstruction Set Overview
MicroBlaze Instruction Set Overview ECE 3534 Part 1 1 The Facts MicroBlaze Soft-core Processor Highly Configurable 32-bit Architecture Master Component for Creating a MicroController Thirty-two 32-bit
More informationWhere Does The Cpu Store The Address Of The
Where Does The Cpu Store The Address Of The Next Instruction To Be Fetched The three most important buses are the address, the data, and the control buses. The CPU always knows where to find the next instruction
More informationIII) EXAMINATION, 2015 CS 331 : SYSTEM PROGRAMMING AND OPERATING SYSTEM I
Total No. of Questions 4] [Total No. of Printed Pages 4 Seat No. [4718]-31 T.Y. B.Sc. (Computer Science) (Semester III) EXAMINATION, 2015 CS 331 : SYSTEM PROGRAMMING AND OPERATING SYSTEM I Paper I (2008
More informationCourse Description: This course includes concepts of instruction set architecture,
Computer Architecture Course Title: Computer Architecture Full Marks: 60+ 20+20 Course No: CSC208 Pass Marks: 24+8+8 Nature of the Course: Theory + Lab Credit Hrs: 3 Course Description: This course includes
More informationUNIT I BASIC STRUCTURE OF COMPUTERS Part A( 2Marks) 1. What is meant by the stored program concept? 2. What are the basic functional units of a
UNIT I BASIC STRUCTURE OF COMPUTERS Part A( 2Marks) 1. What is meant by the stored program concept? 2. What are the basic functional units of a computer? 3. What is the use of buffer register? 4. Define
More informationMemory Hierarchy Basics
Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Memory Hierarchy Basics Six basic cache optimizations: Larger block size Reduces compulsory misses Increases
More informationECE 653: Computer Networks Mid Term Exam all
ECE 6: Computer Networks Mid Term Exam 16 November 004. Answer all questions. Always be sure to answer each question concisely but precisely! All questions have points each. 1. What are the different layers
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationEKT 303 WEEK Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ EKT 303 WEEK 13 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 15 Reduced Instruction Set Computers (RISC) Table 15.1 Characteristics of Some CISCs, RISCs, and Superscalar
More informationArchitectures & instruction sets R_B_T_C_. von Neumann architecture. Computer architecture taxonomy. Assembly language.
Architectures & instruction sets Computer architecture taxonomy. Assembly language. R_B_T_C_ 1. E E C E 2. I E U W 3. I S O O 4. E P O I von Neumann architecture Memory holds data and instructions. Central
More information(1) Define following terms: Instruction, Machine Cycle, Opcode, Oprand & Instruction Cycle. Instruction:
(1) Define following terms: Instruction, Machine Cycle, Opcode, Oprand & Instruction Cycle. Instruction: Instruction is the command given by the programmer to the Microprocessor to Perform the Specific
More informationLesson Plan. Name of Faculty: Sana Bharti. Discipline: MCA. Semester: 4 th. Subject: Data Mining and Warehousing (MCA-16-43)
Lesson Plan Name of Faculty: Sana Bharti Discipline: MCA Semester: 4 th Subject: Data Mining and Warehousing (MCA-16-43) Lesson Plan Duration: 15 Weeks Workload (Lecture) Per Week: 4 Lecture Per Week Week
More informationSemester: I Credits: 5. Category: MC No.of hrs/week: 5 CA PROGRAMMING IN C
Semester: I Credits: 5 Category: MC No.of hrs/week: 5 CA1505 - PROGRAMMING IN C Objective: This course aims at explaining the basic concepts of computers and an easy understanding of C Language by the
More informationUNIVERSITI SAINS MALAYSIA. CCS522 Advanced Data Communication & Computer Network
UNIVERSITI SAINS MALAYSIA First Semester Examination Academic Session 2003/2004 September/October 2003 CCS522 Advanced Data Communication & Computer Network Duration : 3 hours INSTRUCTION TO CANDIDATE:
More informationCSE 820 Graduate Computer Architecture. week 6 Instruction Level Parallelism. Review from Last Time #1
CSE 820 Graduate Computer Architecture week 6 Instruction Level Parallelism Based on slides by David Patterson Review from Last Time #1 Leverage Implicit Parallelism for Performance: Instruction Level
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK VII SEMESTER EC6013 Advanced Microprocessors and Microcontrollers
More informationFACULTY OF ENGINEERING B.E. 4/4 (CSE) II Semester (Old) Examination, June Subject : Information Retrieval Systems (Elective III) Estelar
B.E. 4/4 (CSE) II Semester (Old) Examination, June 2014 Subject : Information Retrieval Systems Code No. 6306 / O 1 Define Information retrieval systems. 3 2 What is precision and recall? 3 3 List the
More informationPESIT- Bangalore South Campus Hosur Road (1km Before Electronic city) Bangalore
Data Warehousing Data Mining (17MCA442) 1. GENERAL INFORMATION: PESIT- Bangalore South Campus Hosur Road (1km Before Electronic city) Bangalore 560 100 Department of MCA COURSE INFORMATION SHEET Academic
More informationADMINISTRATIVE MANAGEMENT COLLEGE
First Semester ADMINISTRATIVE MANAGEMENT COLLEGE BACHELOR OF COMPUTER APPLICATION COURSE OUTCOME (CO) Problem solving techniques Using C CO 1: Understand the basic concepts of programming, software and
More informationINTELLIGENCE PLUS CHARACTER - THAT IS THE GOAL OF TRUE EDUCATION UNIT-I
UNIT-I 1. List and explain the functional units of a computer with a neat diagram 2. Explain the computer levels of programming languages 3. a) Explain about instruction formats b) Evaluate the arithmetic
More informationECE 411 Exam 1 Practice Problems
ECE 411 Exam 1 Practice Problems Topics Single-Cycle vs Multi-Cycle ISA Tradeoffs Performance Memory Hierarchy Caches (including interactions with VM) 1.) Suppose a single cycle design uses a clock period
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
More informationObject Oriented Programming
Program Structure for Master of Computer Application (MCA) Mumbai University (With Effect from 2012-2013) Semester I Object Oriented Programming 1 C++ Fundamentals: Data types, Operators, Preprocessor
More informationDOT NET Syllabus (6 Months)
DOT NET Syllabus (6 Months) THE COMMON LANGUAGE RUNTIME (C.L.R.) CLR Architecture and Services The.Net Intermediate Language (IL) Just- In- Time Compilation and CLS Disassembling.Net Application to IL
More informationTutorial 11. Final Exam Review
Tutorial 11 Final Exam Review Introduction Instruction Set Architecture: contract between programmer and designers (e.g.: IA-32, IA-64, X86-64) Computer organization: describe the functional units, cache
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-11: 80x86 Architecture
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-11: 80x86 Architecture 1 The 80x86 architecture processors popular since its application in IBM PC (personal computer). 2 First Four generations
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationUNIVERSITY OF MALTA THE MATRICULATION CERTIFICATE EXAMINATION INTERMEDIATE LEVEL COMPUTING. May 2012 MARKING SCHEME
UNIVERSITY OF MALTA THE MATRICULATION CERTIFICATE EXAMINATION INTERMEDIATE LEVEL COMPUTING May 2012 MARKING SCHEME MATRICULATION AND SECONDARY EDUCATION CERTIFICATE EXAMINATIONS BOARD Section A (Answer
More informationUniversity of Toronto Faculty of Applied Science and Engineering
Print: First Name:............ Solutions............ Last Name:............................. Student Number:............................................... University of Toronto Faculty of Applied Science
More informationWilliam Stallings Computer Organization and Architecture. Chapter 12 Reduced Instruction Set Computers
William Stallings Computer Organization and Architecture Chapter 12 Reduced Instruction Set Computers Major Advances in Computers(1) The family concept IBM System/360 1964 DEC PDP-8 Separates architecture
More informationASSIGNMENT - 1 M.C.A.DEGREE EXAMINATION, MAY 2019 Second Year SOFTWARE ENGINEERING. Maximum : 30 MARKS Answer ALL questions.
ASSIGNMENT - 1 M.C.A.DEGREE EXAMINATION, MAY 2019 SOFTWARE ENGINEERING (DMCA201) Q1) Explain Spiral model with suitable example. Also explain how it differs from Software Prototyping model. Q2) a) Draw
More informationWorkshop on Digital Circuit Design in FPGA
Workshop on Digital Circuit Design in FPGA Session-1 Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com The field-programmable
More information