Chapter 10: Design Options of Digital Systems
|
|
|
- Ashlyn Patterson
- 5 years ago
- Views:
Transcription
1 Chapter 10: Design Options of Digital Systems Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-1
2 Syllabus Objectives Design options of digital systems PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-2
3 Objectives After completing this chapter, you will be able to: Describe the features of system-level design options Describe basic structures and features of cell-based ASICs Describe basic structures and features of gate array ASICs Describe basic structures and features of programmable logic devices (PLDs) Describe basic structures and features of field-programmable gate arrays (FPGAs) Understand how to model PLAs (including PLDs) Understand the issues of voltage tolerance and voltage compliance Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-3
4 Syllabus Objectives Design options of digital systems Design options Cell-based designs Gate-array-based designs Field-programmable devices PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-4
5 Design Options of Digital Systems Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-5
6 System-Level Design Options Chapter 10: Design Options of Digital Systems PCB (printed-circuit board)-based platforms SoPC (System on a programmable chip)-based platforms Also called programmable system chip (PSC) Soft IP+ cell_library-based platforms Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-6
7 PCB-Based Platforms Consist of discrete standard components µp/µc, peripherals, and memory devices NRE cost low May need additional CPLD/FPGA devices Examples 8051 PIC ARM family Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-7
8 SoPC-Based Platforms Chapter 10: Design Options of Digital Systems Consist of hard or soft IPs May need additional customized logic modules Examples Xilinx VirtexII pro Spartan 3 (MicroBlaze) Altera Cyclone Series (NIOS) Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-8
9 Soft IP+ Cell Library-Based platforms Consist of soft IP being configured into an optimized system hardware An example Tensilica s Xtensa Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-9
10 Design Alternatives of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-10
11 Comparison of Design Options Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-11
12 Syllabus Objectives Design options of digital systems Design options Cell-based designs Gate-array-based designs Field-programmable devices PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-12
13 Basic Structure of Cell-Based ASICs I/O Pads Routing channel Macro Routing channel Complex macro Routing channel Routing channel Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-13
14 Basic Cell Types Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-14
15 A Cell-Based D-Type Flip Flop Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-15
16 Syllabus Objectives Design options of digital systems Design options Cell-based designs Gate-array-based designs Field-programmable devices PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-16
17 Basic Structures of Gate-Array ASICs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-17
18 Basic Structures of Gate Arrays Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-18
19 Basic Structures of Gate Arrays Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-19
20 Syllabus Objectives Design options of digital systems Design options Cell-based designs Gate-array-based designs Field-programmable devices PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-20
21 Shorthand Notations Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-21
22 Programmable Logic Devices Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-22
23 Basic Structures of CPLDs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-23
24 Basic Structures of FPGAs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-24
25 Basic Structures of PICs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-25
26 Comparison of PICs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-26
27 Syllabus Objectives Design options of digital systems PLD modeling ROM /PLA /PAL PLA modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-27
28 Basic Structures of ROMs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-28
29 Basic Structures of PLAs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-29
30 Basic Applications of PLAs Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-30
31 A PAL Example R8 Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-31
32 Syllabus Objectives Design options of digital systems PLD modeling ROM /PLA /PAL PLA modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-32
33 PLA Modeling PLA device structures SOP (sum of product) = AND plane + OR plane AND plus OR array NAND plus NAND array POS (product of sum) = OR plane + AND plane OR plus AND array NOR plus NOR array An AND plane or an OR plane a personality array (or memory) Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-33
34 PLA Modeling A PLA device is modeled by a group of system tasks an appropriate combination of two system tasks A PLA device can be modeled as: Asynchronous Synchronous Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-34
35 PLA Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-35
36 PLA Modeling $async$logic$array(mem_type, input_terms, output_terms); $sync$logic$array(mem_type, input_terms, output_terms); wire a1, a2, a3, a4, a5, a6, a7; reg b1, b2, b3; wire [1:7] awire; reg [1:3] breg; reg [1:7] mem [1:3]; // define personality memory // asynchronous AND plane $async$and$array(mem, {a1, a2, a3, a4, a5, a6, a7}, {b1, b2, b3}); // or using the following statement $async$and$array(mem, awire, breg); // synchronous AND plane clock) $sync$and$array(mem, {a1, a2, a3, a4, a5, a6, a7}, {b1, b2, b3}); Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-36
37 Logic Array Personality Defined as an array of reg Width: the number of input terms Depth: the number of output terms Loaded into memory using Chapter 10: Design Options of Digital Systems System tasks $readmemb or $readmemh The procedural assignment statements Can be changed dynamically during simulation Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-37
38 PLA Modeling The array format 1: taken 0: not taken The plane format (complies with Espresso) 1: true 0: complement? or z: don t care Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-38
39 PLA Modeling Define PLA personality from file In this example only one and plane is considered module async_array(a1, a2, a3, a4, a5, a6, a7, b1, b2, b3); input a1, a2, a3, a4, a5, a6, a7 ; output b1, b2, b3; reg [1:7] mem[1:3]; // memory declaration for array personality reg b1, b2, b3; initial begin b1 = a1 & a2 // setup the personality from the file array.dat $readmemb ("array.dat", mem); // setup an asynchronous logic array with the input // and output terms expressed as concatenations $async$and$array (mem,{a1, a2, a3, a4, a5, a6, a7},{b1, b2, b3}); end b2 = a3 & a4 & a5 b3 = a5 & a6 & a Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-39
40 PLA Modeling The Array Format Chapter 10: Design Options of Digital Systems Define PLA personality using procedural assignment statements In this example only one and plane is considered input a0, a1, a2, a3, a4, a5, a6, a7; output b0, b1, b2; reg b0, b1, b2; reg [7:0] mem[0:2]; // an example of the usage of array format initial begin // using procedural assignment statements. mem[0] = 8'b ; mem[1] = 8'b ; mem[2] = 8'b ; $async$and$array(mem, {a0,a1,a2,a3,a4,a5,a6,a7}, {b0,b1,b2}); end Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-40
41 PLA Modeling A = {a0, a1, a2, a3, a4, a5, a6, a7} B = {b0, b1, b2} mem[0] = 8'b ; mem[1] = 8'b ; mem[2] = 8'b ; A = > B = 100 A = > B = 010 A = > B = 001 A = > B = 000 A = > B = 000 A = > B = 000 A = > B = 011 Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-41
42 A PLA Modeling Example --- Logic Circuit Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-42
43 A PLA Modeling Example The Array Format // An example of the usage of the array format reg p0, p1, p2, p3; // internal minterms # 0 ns x x x x x # 5 ns reg [0:5] mem_and[0:3]; # 10 ns reg [0:3] mem_or[1:2]; # 15 ns wire x_n, y_n, z_n; # 20 ns assign x_n= ~x, y_n= ~y, z_n= ~z; # 25 ns initial begin: pla_model_array # 30 ns mem_and[0] = 6'b100100; // AND plane # 35 ns mem_and[1] = 6'b100010; # 40 ns mem_and[2] = 6'b000110; mem_and[3] = 6'b011001; $async$and$array(mem_and, {x, x_n, y, y_n, z, z_n}, {p0, p1, p2, p3}); mem_or[1] = 4'b1101; // OR plane mem_or[2] = 4'b0110; $async$or$array(mem_or, {p0, p1, p2, p3}, {f1, f2}); end Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-43
44 A PLA Modeling Example The Plane Format reg p0, p1, p2, p3; // internal minterms reg [0:2] mem_and[0:3]; // and plane personality matrix reg [0:3] mem_or[1:2]; // or plane personality matrix // An example of the usage of the plane format initial begin: pla_model_plane $async$and$plane(mem_and, {x, y, z}, {p0, p1, p2, p3}); mem_and[0] = 3'b10?; // define AND plane mem_and[1] = 3'b1?1; mem_and[2] = 3'b?01; mem_and[3] = 3'b010; $async$or$plane(mem_or, {p0, p1, p2, p3}, {f1, f2}); mem_or[1] = 4'b11?1; // define OR plane mem_or[2] = 4'b?11?; end # 0 ns x x x x x # 5 ns # 10 ns # 15 ns # 20 ns # 25 ns # 30 ns # 35 ns # 40 ns Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-44
45 Initializing Memory from Files Chapter 10: Design Options of Digital Systems $readmemb( <file_name>,<memory_name>); $readmemb( <file_name>,<memory_name>, <start_addr>); $readmemb( <file_name>,<memory_name>, <start_addr>, <end_addr>); $readmemh( <file_name>,<memory_name>); $readmemh( <file_name>,<memory_name>, <start_addr>); $readmemh( <file_name>,<memory_name>, <start_addr>, <end_addr>); reg [7:0] mem[1:256]; initial $readmemb( mem.data, mem); initial $readmemb( mem.data, mem, 16); initial $readmemb( mem.data, mem, 128, 1); Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-45
46 Data File Formats Addresses specified specified as hexadecimal numbers Data can contain x or z and is separated by white spaces Uninitialized locations default to x For // data will be read into memory from location // data will be read into memory from location zz1z Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-46
47 Syllabus Objectives Design options of digital systems PLD modeling CPLD XC9500 family MAX7000 family FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-47
48 Basic Structure of CPLD: XC9500XL Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-48
49 CPLD: XC9500XL --- Function Block Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-49
50 CPLD: XC9500XL --- Macro of Function Block Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-50
51 CPLD: XC9500XL --- Switch Matrix Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-51
52 CPLD: XC9500XL --- I/O Block Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-52
53 Syllabus Objectives Design options of digital systems PLD modeling CPLD XC9500 family MAX7000 family FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-53
54 MAX7000 Family --- Basic Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-54
55 MAX7000 Family --- Macrocell Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-55
56 MAX7000 Family --- Sharable Expander Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-56
57 MAX7000 Family --- Parallel Expander Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-57
58 MAX7000 Family --- IOB Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-58
59 Syllabus Objectives Design options of digital systems PLD modeling CPLD FPGA Xilinx FPGA devices Altera FPGA devices Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-59
60 Basic Structure of FPGA: XC4000XL Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-60
61 FPGA: XC4000XL --- Configurable Logic Block Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-61
62 FPGA: XC4000XL --- PIA Interconnection lines: Single-length lines Double-length lines Global long-length lines Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-62
63 FPGA: XC4000XL --- PIA Chapter 10: Design Options of Digital Systems Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-63
64 FPGA: XC4000XL --- Input/Output Block Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-64
65 FPGA: XC4000XL --- Macro Library Example Types of macros Soft macros Hard macros Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-65
66 Syllabus Objectives Design options of digital systems PLD modeling CPLD FPGA Xilinx FPGA devices Altera FPGA devices Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-66
67 APEX 20K Family --- Basic Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-67
68 APEX 20K Family --- MegaLAB Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-68
69 APEX 20K Family --- Logic Element Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-69
70 APEX 20K Family --- Structure of ESB Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-70
71 Altera Stratix Family --- Basic Structure Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-71
72 Syllabus Objectives Design options of digital systems PLD modeling CPLD FPGA Practical issues Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-72
73 Single Ended vs. Differential Signals Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-73
74 Voltage Tolerance and Voltage Compliance Voltage tolerant Input voltage tolerance Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-74
75 Voltage Tolerance and Voltage Compliance Output voltage tolerance Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 10-75
Digital Integrated Circuits
Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
FYSE420 DIGITAL ELECTRONICS. Lecture 7
FYSE420 DIGITAL ELECTRONICS Lecture 7 1 [1] [2] [3] DIGITAL LOGIC CIRCUIT ANALYSIS & DESIGN Nelson, Nagle, Irvin, Carrol ISBN 0-13-463894-8 DIGITAL DESIGN Morris Mano Fourth edition ISBN 0-13-198924-3
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES This chapter in the book includes: Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders
Programmable Logic Devices
Programmable Logic Devices INTRODUCTION A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD
CS310 Embedded Computer Systems. Maeng
1 INTRODUCTION (PART II) Maeng Three key embedded system technologies 2 Technology A manner of accomplishing a task, especially using technical processes, methods, or knowledge Three key technologies for
ECE 331 Digital System Design
ECE 331 Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals of Logic
Basic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
Programmable Logic. Any other approaches?
Programmable Logic So far, have only talked about PALs (see 22V10 figure next page). What is the next step in the evolution of PLDs? More gates! How do we get more gates? We could put several PALs on one
Field Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
Introduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.
Programmable Logic Devices (PLDs)
Programmable Logic Devices (PLDs) 212: Digital Design I, week 13 PLDs basically store binary information in a volatile/nonvolatile device. Data is specified by designer and physically inserted (Programmed)
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
Memory and Programmable Logic
Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),
Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN
Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 Implementation in Sequential Logic 2 PAL Logic Implementation Design Example: BCD to Gray Code Converter A B
PLAs & PALs. Programmable Logic Devices (PLDs) PLAs and PALs
PLAs & PALs Programmable Logic Devices (PLDs) PLAs and PALs PLAs&PALs By the late 1970s, standard logic devices were all the rage, and printed circuit boards were loaded with them. To offer the ultimate
Chapter 13 Programmable Logic Device Architectures
Chapter 13 Programmable Logic Device Architectures Chapter 13 Objectives Selected areas covered in this chapter: Describing different categories of digital system devices. Describing different types of
LSN 6 Programmable Logic Devices
LSN 6 Programmable Logic Devices Department of Engineering Technology LSN 6 What Are PLDs? Functionless devices in base form Require programming to operate The logic function of the device is programmed
Chapter 5: Tasks, Functions, and UDPs
Chapter 5: Tasks, Functions, and UDPs Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL
Evolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
Embedded Controller Design. CompE 270 Digital Systems - 5. Objective. Application Specific Chips. User Programmable Logic. Copyright 1998 Ken Arnold 1
CompE 270 Digital Systems - 5 Programmable Logic Ken Arnold Objective Application Specific ICs Introduce User Programmable Logic Common Architectures Programmable Array Logic Address Decoding Example Development
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
An Introduction to Programmable Logic
Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor
EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
Programable Logic Devices
Programable Logic Devices In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND- OR array that makes it easy to implement
Code No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
Chapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and
Chapter 2a: Structural Modeling
Chapter 2a: Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs
Programmable Logic Devices
Programmable Logic Devices Programmable Logic Devices Fig. (1) General structure of PLDs Programmable Logic Device (PLD): is an integrated circuit with internal logic gates and/or connections that can
Memory and Programmable Logic
Digital Circuit Design and Language Memory and Programmable Logic Chang, Ik Joon Kyunghee University Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM
Computer Structure. Unit 2: Memory and programmable devices
Computer Structure Unit 2: Memory and programmable devices Translated from Francisco Pérez García (fperez at us.es) by Mª Carmen Romero (mcromerot at us.es, Office G1.51, 954554324) Electronic Technology
Code No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
FPGA How do they work?
ent FPGA How do they work? ETI135, Advanced Digital IC Design What is a FPGA? Manufacturers Distributed RAM History FPGA vs ASIC FPGA and Microprocessors Alternatives to FPGAs Anders Skoog, Stefan Granlund
Follow-up question: now, comment on what each of these acronyms actually means, going beyond a mere recitation of the definition.
Question 1 Define the following acronyms as they apply to digital logic circuits: ASIC PAL PLA PLD CPLD FPGA file 03041 Answer 1 ASIC: Application-Specific Integrated Circuit PAL: Programmable Array Logic
FPGA for Dummies. Introduc)on to Programmable Logic
FPGA for Dummies Introduc)on to Programmable Logic FPGA for Dummies Historical introduc)on, where we come from; FPGA Architecture: Ø basic blocks (Logic, FFs, wires and IOs); Ø addi)onal elements; FPGA
(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
Code No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
Outline. Field Programmable Gate Arrays. Programming Technologies Architectures. Programming Interfaces. Historical perspective
Outline Field Programmable Gate Arrays Historical perspective Programming Technologies Architectures PALs, PLDs,, and CPLDs FPGAs Programmable logic Interconnect network I/O buffers Specialized cores Programming
Hardware Synthesis. References
Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Email: ce.srbiau@gmail.com 1 References 2 1 Chapter 1 Digital Design Using VHDL and PLDs 3 Some Definitions
Programmable logic technology
Programmable logic technology This worksheet and all related files are licensed under the Creative Commons Attribution License, version 1.0. To view a copy of this license, visit http://creativecommons.org/licenses/by/1.0/,
Introduction to Digital Logic Missouri S&T University CPE 2210 Hardware Implementations
Introduction to Digital Logic Missouri S&T University CPE 2210 Hardware Implementations Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
FPGA Implementations
FPGA Implementations Smith Text: Chapters 4-8 Online version at: http://www10.edacafe.com/book/asic/asics.php Topic outline Chapter 4 Programmable ASIC technologies Chapter 5 Programmable logic cells Chapter
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
Altera FLEX 8000 Block Diagram
Altera FLEX 8000 Block Diagram Figure from Altera technical literature FLEX 8000 chip contains 26 162 LABs Each LAB contains 8 Logic Elements (LEs), so a chip contains 208 1296 LEs, totaling 2,500 16,000
PINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE4220. PROGRAMMABLE LOGIC DEVICES (PLDs)
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE4220 PROGRAMMABLE LOGIC DEVICES (PLDs) A PLD, or programmable logic device, is an electronic component that is used
VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
Laboratory Exercise 3
Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
Combinational Logic Design with Verilog. ECE 152A Winter 2012
Combinational Logic Design with Verilog ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.10 Introduction to Verilog 2.10.1 Structural Specification of Logic
Digital System Design Lecture 7: Altera FPGAs. Amir Masoud Gharehbaghi
Digital System Design Lecture 7: Altera FPGAs Amir Masoud Gharehbaghi amgh@mehr.sharif.edu Table of Contents Altera FPGAs FLEX 8000 FLEX 10k APEX 20k Sharif University of Technology 2 FLEX 8000 Block Diagram
register:a group of binary cells suitable for holding binary information flip-flops + gates
9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the
EECS150 - Digital Design Lecture 16 - Memory
EECS150 - Digital Design Lecture 16 - Memory October 17, 2002 John Wawrzynek Fall 2002 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: data & program storage general purpose registers buffering table lookups
EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200
Programmable Logic Devices
Programmable Logic Devices Luis Entrena, Celia López, Mario García, Enrique San Millán Universidad Carlos III de Madrid Outline Tecnologies for implementing programmable circuits Simple Programmable Logic
Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles
Class 330 Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles Steven Knapp (sknapp) Arye Ziklik (arye) Triscend Corporation www.triscend.com Copyright 1998,
L2: FPGA HARDWARE : ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA
L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA 18-545: FALL 2014 2 Admin stuff Project Proposals happen on Monday Be prepared to give an in-class presentation Lab 1 is
Introduction to Programmable Logic Devices (Class 7.2 2/28/2013)
Introduction to Programmable Logic Devices (Class 7.2 2/28/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Today s Topics Complexity issues Implementation
Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE
FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints
EECS150 - Digital Design Lecture 16 Memory 1
EECS150 - Digital Design Lecture 16 Memory 1 March 13, 2003 John Wawrzynek Spring 2003 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: Whenever a large collection of state elements is required. data &
Digital Electronics 27. Digital System Design using PLDs
1 Module -27 Digital System Design 1. Introduction 2. Digital System Design 2.1 Standard (Fixed function) ICs based approach 2.2 Programmable ICs based approach 3. Comparison of Digital System Design approaches
Field Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
Fig. 6-1 Conventional and Array Logic Symbols for OR Gate
6- (a) Conventional symbol (b) Array logic symbol Fig. 6- Conventional and Array Logic Symbols for OR Gate 2 Prentice Hall, Inc. 6-2 k address lines Read n data input lines emory unit 2 k words n bits
Overview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
System-on Solution from Altera and Xilinx
System-on on-a-programmable-chip Solution from Altera and Xilinx Xun Yang VLSI CAD Lab, Computer Science Department, UCLA FPGAs with Embedded Microprocessors Combination of embedded processors and programmable
Product Obsolete/Under Obsolescence
0 APPLICATION NOTE XAPP100 December 3, 1998 (Version 1.4) 0 14* Application Note by Peter Alfke Summary This Application Note describes the various Xilinx product families. Differences between the families
Code No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
QUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
FPGAs in a Nutshell - Introduction to Embedded Systems-
FPGAs in a Nutshell - Introduction to Embedded Systems- Dipl.- Ing. Falk Salewski Lehrstuhl Informatik RWTH Aachen salewski@informatik.rwth-aachen.de Winter term 6/7 Contents History FPGA architecture
Field Program mable Gate Arrays
Field Program mable Gate Arrays M andakini Patil E H E P g r o u p D H E P T I F R SERC school NISER, Bhubaneshwar Nov 7-27 2017 Outline Digital electronics Short history of programmable logic devices
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah
B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents FPGA Technology Programmable logic Cell (PLC) Mux-based cells Look up table PLA
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
Copyright by Syed Ashad Mustufa Younus Copyright by Syed Ashad Mustufa Younus
Copyright by Syed Ashad Mustufa Younus Copyright by Syed Ashad Mustufa Younus Microcontroller & Applications Week 2 Instructor: Syed Ashad Mustufa Younus HP: +92 (0) 300 240 8943 Email: :sashad@iqra.edu.pks
I 4 I 3 I 2 I 1 I 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 T-125. ROM Truth Table (Partial) 1997 by Prentice-Hall, Inc.
997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458 T-5 Inputs Outputs I 4 I 3 I I I A 7 A 6 A 5 A 4 A 3 A A A...... RO Truth Table (Partial) 997 by Prentice-Hall, Inc. ano & Kime
Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial
Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio
EEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 8: Short Introduction to Verilog * Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 Overview Recap + Questions? What is a HDL? Why do we
Digital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of
UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable
MEMORY AND PROGRAMMABLE LOGIC
MEMORY AND PROGRAMMABLE LOGIC Memory is a device where we can store and retrieve information It can execute a read and a write Programmable Logic is a device where we can store and retrieve information
Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog
Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C
Digital Circuit Design Using Xilinx ISE Tools
Digital Circuit Design Using Xilinx ISE Tools Poras T. Balsara and Prashant Vallur Table of Contents 1. Introduction 2. Programmable logic devices: FPGA and CPLD 3. Creating a new project in Xilinx Foundation
EEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description
Lab 4: Register File and Memory 50 points Instructor: Yifeng Zhu Due: One week
Objectives: Lab 4: Register File and Memory 50 points Instructor: Yifeng Zhu Due: One week Build Register File Build Instruction Memory and Data Memory 1. Overview A combinational circuit neither contains
ELCT 501: Digital System Design
ELCT 501: Digital System Lecture 3: Memory and Programmable Logic (continue) Dr. Mohamed Abd El Ghany, Memory Model 32-bit address space can address up to 4 GB (2 32 ) different memory locations 0x00000000
Programmable Memory Blocks Supporting Content-Addressable Memory
Programmable Memory Blocks Supporting Content-Addressable Memory Frank Heile, Andrew Leaver, Kerry Veenstra Altera 0 Innovation Dr San Jose, CA 95 USA (408) 544-7000 {frank, aleaver, kerry}@altera.com
Typical applications where a CPLD may be the best design approach:
By: Carlos Barberis, dba Bartek Technologies Description of Bartek s CPLD1 development board. For some of us CPLD s are familiar devices and for others just another acronym in the electronic device industry.
Chapter 3: Dataflow Modeling
Chapter 3: Dataflow Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 3-1 Objectives After completing this chapter, you will be able to: Describe
SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
ECE 645: Lecture 1. Basic Adders and Counters. Implementation of Adders in FPGAs
ECE 645: Lecture Basic Adders and Counters Implementation of Adders in FPGAs Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting,
Readings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops. Each flip-flop stores 1 bit of information.
Registers Readings: 5.8-5.9.3 Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information ff ff ff ff 178 Controlled Register Reset Load Action
! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!