Pad Ring and Floor Planning
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1 Pad Ring and Floor Planning Pad Ring Core Block 1 Block 2 Block Block 3 Block 6 Block 5 The core of the chip (made up of one or more top level blocks) is surrounded by a ring of pads. The design of the blocks and the arrangement of blocks and pads can significantly affect the overall chip area (and hence the cost/yield). 5001
2 Pad Ring Pad Ring Pad Ring Core Core Pad Limited: small core and/or many pads minimum pad to pad distance gaps around core Core Limited: large core and/or few pads gaps between pads 1 1 these gaps will be filled with special filler cells 5002
3 Floor Planning Re-arrange and re-orient blocks to: create a minimum number of major routing channels 2 reduce block to block and block to pad routing At top of the hierarchy, chips should be near square, other constraints exist at lower levels. 2 for multi layer metal processes ( 5 metal layers or more) it should be possible to route over the blocks allowing closer placement 5003
4 Block Design for easy Floor Planning Block shape Where blocks share a common width, efficient placement is much easier. Block ports If possible arrange the ports on a block for ease of routing to pads and other blocks. 500
5 Floor Planning for Standard Cell Layout Automatic layout: Flatten hierarchy. Placement is controlled by algorithms designed to minmize routing. Aspect ratio easy to control, also control number of columns and rows. Manual layout: Placement based on layout hierarchy (essential for managing complexity). Aspect ratio and port position must be considered early as there is seldom time for iteration. 5005
6 Global Routing Route critical signals first. Buffer global and time critical signals. Clock distribution should be arranged to avoid skew across the chip buffering may actually increase delays while reducing skew 5006
7 VLSI Pad Ring and Floor Planning Pad ring pre-defined a Operand1 Operand1 0V Operand2[6] Operand2 [7] 3.3Vpads Req [6] [7] pads Done SDO create pad ring -multiplier Operand1[5] Operand2[5] Operand1[] Operand2[] Control Result[7] Result[6] Result[5] Result[] <xsize> <ysize> Two blocks in core Bitslice Datapath 3.3Vcore Operand1[3] Operand2[3] Datapath 0V core Result[3] Result[2] Synthesized Control Pad limited Operand1[2] Operand2[2] Result[1] Result[0] Clock distribution built in to cell library Operand2 Operand2 SDI Clock [1] [0] Operand1 Operand1 3.3V Test Reset [1] [0] pads [0] a design blocks to reduce routing since pads can t be moved Datapath will be designed and placed to permit easy wiring of Operand and Result buses to left and right hand pads. Control will be designed and placed to permit easy wiring of control signals to the datapath. 5007
8 VLSI AMS 0.35µm CMOS Pads Core Power Supply Pads GND3IP VDD3IP Input pad ICP 0V 3.3V A A Y Bi directional pad BBC8P Pad Ring Power Supply Pads GND3ALLP VDD3ALLP Output pad BU8P EN A 0V 3.3V A Y Large buffers on output pads allow for drive of very large external loads. Separate dirty power supply pads are provided for the main pad drive transistors to reduce switching noise in the core. Bi-directional pads require three connections to the core. 5008
9 Input / Output I/O Pads IN ENB IN A brief look at a selection of simple digital CMOS I/O pads 5009
10 Output Pads Output pad driver ratioed inverters are used to provide appropriate drive capability final drive transistors are carefully designed to avoid latch-up pad rings are frequently powered separately (dirty power) to confine switching noise 5010
11 Input Pads Input protection must protect floating transistor gates from permanent damage via electrostatic discharge 5011
12 Bidirectional Pads Simple bidirectional pad ENB IN ENB IN bidirectional pad is a tristate inverter output driver combined with an input pad even when IN and are connected internally, we need buffering and an enable control signal note input protection is not shown here 5012
13 Bidirectional Pads Bidirectional pad with increased drive capability ENB IN IN ENB redesign to avoid series output transistors 5013
14 Bidirectional Pads Advanced bidirectional pad design EN EN ENB EN EN EN IN EN logic gates are merged output transistors act as diodes when not enabled low value diffusion resistor completes input protection circuit 501
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