Programmable Logic. Dr. Edward Gatt

Transcription

1 Programmable Logic Dr. Edward Gatt 1

2 Programmable Read Only Memory (PROM) Storing code in ROM was an expensive process that required ROM vendor to create a unique semiconductor mask set for each customer Changes to the code were impossible without creating a new mask and chip Lead time for making changes was far too long PROM solved the problem Initially PROM intended for storing code and constants but then also used to implement logic PROM is programmed and retains data even after power off 2

3 Programmable Read Only Memory (PROM) [2] State machine logic could be programmed into PROM micro-coded state machine Code could easily be changed to fix bugs, add new functions and optimise existing designs Eventually erasable PROMswere developed which allow users to program, erase, re-program devices using inexpensive programmers EPROMsare programmed using high-voltage electrical signals and erased by flooding with UV light 3

4 Programmable Read Only Memory (PROM) [3] ROM Cell One-time progammable diode/transistor based PROM Cell 4

5 Programmable Read Only Memory (PROM) [4] Electrically erasable programmable ROMs (EEPROMs) are programmed and erased by applying high voltages to the device Flash EPROM are programmed/erased electrically and have sections that can be erased electrically in short time and independently of other sections within the design PROMsare excellent for implementing combinational logic with a limited number of inputs and outputs Each address bit for PROM can be considered a logic input and each output bit is programmed to have the required combinatorial function 5

6 Programmable Read Only Memory (PROM) [5] Combinational-logic Implemented on PROM 6

7 Programmable Read Only Memory (PROM) [6] For sequential logic, external clocked-devices such as flip-flops or microprocessors are needed PROM can be used to combine inputs with buts representing the current state of the machine, to produce outputs and the next state of the machine Microcode is often decoded within a microprocessor using this method 7

8 Programmable Read Only Memory (PROM) [7] PROM-based state machine 8

9 Programmable Read Only Memory (PROM) [8] Problem with PROM is that they are extremely slow Also, PROMsare not easily integrated into logic circuits on a chip because they require a different technology and therefore a different set of masks and processes than for logic circuits -> requiring extra costs 9

10 Programmable Logic Arrays (PLAs) PLAsare a solution to the speed and input limitations of PROMs PLAsconsist of a large number of inputs connected to an AND plane, where different combinations of signals can be logically ANDed together according to programming requirements Outputs of AND plane go into OR plane where terms are ORedtogether in different combinations and finally outputs are produced 10

11 Programmable Logic Arrays (PLAs) [2] At inputs and outputs there are no NOTs-> so logical NOT cannot be obtained PLAscan implement large number of combinatorial functions but cant implement every possible mapping like PROMs However, faster and allow more inputs than PROMs PLA Architecture 11

12 Programmable Logic Arrays (PLAs) [3] PLAscan also be combined with flip-flops to create state-machines Each AND, OR connection can be programmed to connect or disconnect Boolean equations can be created by selectively connecting wires within AND/OR planes 12

13 Programmable Array Logic (PAL) PAL variation of PLA PAL has wide, programmable AND plane for ANDing inputs together Programming elements at each intersection in the AND plane allow perpendicular traces to be connected or left open creating product terms Product terms are then ORed together 13

14 Programmable Array Logic (PAL) [2] In PAL, OR plane is fixed limiting number of terms that can be ORed Still allows a large number of Boolean equations to be implemented PAL Architecture 14

15 Programmable Array Logic (PAL) [3] Including inverters reduces the need for large OR plane, which allows the extra silicon area on chip to be used for multiplexers, XORsand latches Clocked-elements such as flip-flops can be included in PALsallowing state-machine implementations Also, PALsare extremely fast 15

16 Complex Programmable Logic Devices (CPLDs) CPLDsare designed to appear just like a large number of PALsin a single chip, connected to each other through a cross-point switch Idea was to make them appealing to previous users of PALs CPLDsuse same development tools and programmers as PALsand are based on same technology but can handle more complex operations 16

17 Complex Programmable Logic Devices (CPLDs) [2] CPLD Architecture 17

18 Function Blocks A function block is similar to the PAL architecture with wide AND plane and fixed number of OR gates AND plane can accept inputs from I/O blocks or from other function blocks or feedback from the same block Programming elements at each intersection in the AND plane allow perpendicular traces to be connected or left open to create product of terms -> just like PAL Product terms can be ORedtogether and sent straight out of block or through clocked flip-flop 18

19 Function Blocks [2] Multiplexers are also included (shown as M in the diagram) Each multiplexer has an FET transistor beneath it representing a programmable element attached to the select line Multiplexer can be programmed to output one of the inputs Clear Select selects the signal used to clear flip flop Clock/Enable Select allows outputs to control clock and the clock enable input to the flip flop Register Bypass allows the output of functional block to be registered signal (output of flip flop) or a combinatorial signal (output from combinational logic) 19

20 Function Blocks [3] CPLD function block 20

21 Function Blocks [4] Many CPLDsinclude specialisedlogic eg. XOR, which can be bypassed by programming 1 input to logic 0 XOR useful for generating parity in bus for simple error detection Each function block would have many OR gates, logic gates, multiplexers, flip flops 21

22 I/O Blocks I/O Blocks are used to drive signals to the pins of the CPLD device at appropriate voltage levels (eg. TTL,CMOS,ECL etc) I/O Blocks allow each I/O pin to be individually configured for input, output or bi-directional operation I/O pins have a tri-state output buffer that can be controlled by global output enable signals or directly connected to ground or VCC Each output can also be configured to be open drain 22

23 I/O Blocks [2] Outputs can often be programmed to drive different voltage levels enabling CPLD to be interfaced to many different devices One particular useful feature in high speed CPLDs is ability to control rise and fall times of output drivers by controlling slew rate For fast speed devices, delay through logic I low Disadvantage of fast transitions are overshoots and under-shoots which can potentially damage device the CPLD is driving 23

24 I/O Blocks [3] Another disadvantage of fast transition is noise Programming of slew rates allows avoidance of such problems Input signal from I/O block goes to switch matrix in order to be routed to appropriate functional block In some architectures, particular inputs have direct paths to particular functional blocks in order to lower delay on the input, reducing signal setup time In most architectures, specific pins of the device connect to the specific I/O blocks that can drive global signals like reset or clock 24

25 I/O Blocks [4] CPLD I/O Block 25

26 Clock Drivers Synchronous design is the only accepted design methodology that will ensure that CPLD-based design is reliable In order to design synchronous CPLDs, clock signal must arrive at each flip flop in the design at about the same time and with very little delay from input pin To accomplish this, special I/O blocks have clock drivers that use very fast input buffers and which drive input clock signal onto internal clock tree Clock tree is named so as it resembles a tree with each branch driving the clock input of a fixed number of flip flops 26

27 Clock Drivers [2] Clock driver is designed to drive entire tree very quickly Trees are designed to minimiseskew between clock signals arriving at different flip flops through device Each branch of tree is approximately equal in length and if not, buffers are used to balance skew along different branches Clock signals are only driven through clock input pins that connect to these special drivers 27

28 Clock Drivers [3] In large devices, there may be several clock input pins connected to different clock drivers This feature helps in designs that use multiple clocks No. of clocks should be equal to no. of clocks needed in design Different clocks will need to be considered asynchronous with each other, because CPLD vendor does not guarantee skew between multiple clocks 28

29 Interconnect CPLD interconnect is a very large programmable switch matrix that allows signals from all parts of the device to go to all other parts of the device Switch matrix takes outputs from function blocks and is programmed to send these outputs to other function blocks Designer can route any output signal to any destination 29

30 Interconnect [2] Advantage of switch matrix routing is that delays through chip are deterministic Designers can determine delays for any signal by computing delay through function blocks, I/O blocks and switch matrix All delays are fixed and delays due to routing along metal traces are negligible Designers can easily calculate delays from input pints to output pins by using worst-case timings provided by vendors CPLD Matrix Switch 30

31 CPLD Technology Different technologies used EPROM, EEPROM, Flash EPROM Erasable technology allows in-system programmability of the device Serial interface on chip is used to send programmable data into chip -> 4-pin JTAG interface normally adopted 31

32 Embedded Devices Could include SRAM memories Flash memories Microcontrollers Microprocessors DSPs Phase Locked Loops (PLLs) Network Processors 32

33 CPLD Selection Criteria Programming technology as this determines the equipment needed to program the device and whether it can be reprogrammed In-system programmability preferred if the system wants to allow updating Function block capabilities if combinational logic prefer large number of inputs, parity checking prefer XORs, pipelining prefers flip-flops No. of function blocks defines complexity 33

34 CPLD Selection Criteria [2] Kind of flip flop control -egglobal resets simplify initialization, clock enable useful in state machine design Embedded devices types can allow specialised functions No. and type of I/O pins No. of clock input pins 34

35 Field Programmable Gate Arrays (FPGAs) Each FPGA vendor has its own architecture but in general terms they all consist of configurable logic blocks, configurable I/O blocks and programmable interconnect to route signals between logic blocks and I/O blocks Also there is clock circuitry for driving clock signals to each flip flop in each logic block Additional logic resources such as ALUs, memory and decoders may also be available 35

36 Field Programmable Gate Arrays (FPGAs) [2] Most important thing for FPGA architecture is it regular ASIC-like structure Regular structure makes FPGAsuseful for all kinds of logic designs 36

37 Configurable Logic Blocks (CLBs) CLBscontain the programmable logic for the FPGAs Typical CLB contains RAM for creating arbitrary combinatorial logic functions Contains also flip flops for clocked storage elements and multiplexers to route logic within the block and to route logic to and from external resources 37

38 Configurable Logic Blocks (CLBs) [2] 38

39 Configurable Logic Blocks (CLBs) [3] On the left, there are two 4-input memories, also known as 4-input look-up tables (4-LUTs) They can implement any 4-input Boolean equation Feeding the output of the two 4-LUTs into a 3-LUT produces a wide variety of outputs (for up to 9 inputs) C1-C4 are inputs from other CLBsor I/O Blocks on the chip These interconnect inputs allow designers to partition large logic functions among several CLBs They also are the basis for connecting CLBsin order to create large, functioning designs 39

40 Configurable Logic Blocks (CLBs) [4] Multiplexers throughout the CLB are programmed statically -> i.e. when FPGA is programmed, select lines are set high or low and remain in that state Some multiplexers allow signal path through the chip to be programmed e.g. M1 is programmed so that the top right flip flop data is either input C2 or output of one of the two 4-LUTs or output of 3-LUT 40

41 Configurable Logic Blocks (CLBs) [5] Some multiplexers are programmed to affect the operation of the CLB flip flops e.g. M2 is programmed to allow top flip flop to transition on rising or falling edge of the clock signal or M3 is programmed to always enable top flip flop or to enable only when input signal C4 is asserted to enable it Note that clock input to flip flops must come only from global clock signal 41

42 Configurable Logic Blocks (CLBs) [6] Designers can use CLB to create simple combinational logic but multiple CLBscan be connected together to implement complex boolean logic Unfortunately, routing delay in an FPGA is a significant amount of overall delay This results in an overall decrease in the speed of the design 42

43 Configurable Logic Blocks (CLBs) [7] Two types of CLBs Large grain Fine grain Large grain contain larger functionality logic e.g. contain two or more flip flops design that does not require them will result in poor utilisation of resources Fine grain contain only small very basic elements such as NANDs/NORs 43

44 Configurable I/O Blocks Configurable I/O Blocks are used to bring signals onto the chip and send them back off again Output buffer has programmable controls to make them tri-state, open collector and skew rate control Allows FPGA to output to most standard TTL or CMOS Input buffer can be programmed for different threshold voltages, typically TTL or CMOS levels 44

45 Configurable I/O Blocks [2] Combination of input and output buffers on each pin and their programmability, means that each I/O block can be used for input, output or bidirectional signal Pull up resistors are normally available, take up little space on chip and can be used to pull-up tristate buses on a board Floating buses increase noise in a system, increase power consumption and can create meta-stability problems 45

46 Configurable I/O Blocks [3] 46

47 Configurable I/O Blocks [4] Small logic blocks can be included in the I/O blocks for two reasons: there is available space and can be accommodated routing in FPGA is much more significant than logic delay -> routing is done via programmed multiplexers in SRAM based devices and through conducting viasin anti-fuse based -> both technologies add significant delay unlike ASICsusing metal lines -> multiplexers have gate delay associated with them plus conducting vias have high resistances, causing RC delay 47

48 Configurable I/O Blocks [5] Because of large routing delays, if input signal needs to be routed from input buffer through internal interconnect to a flip flop in a CLB within the chip, there would be a large delay d from input pin to data input of flip flop In order to meet hold time requirement of the internal flip flop, h, hold time requirement of the signal with respect to the clock at the pins of the chip would be (d+h) which would be large and difficult to meet for devices interfacing with the FPGA 48

49 Configurable I/O Blocks [6] 49

50 Configurable I/O Blocks [7] To improve this flip flops are placed in I/O blocks, delay is reduced and reasonable hold time can be achieved at pins of the chip Similarly, if output is needed to be routed from flip flop within CLB to output buffer, there would be large delay from flip flop output to the pin of the chip This means that clock-to-output delay for all signals would be delay of the flip flop (c) plus delay of routing (d) Chips interfaced with FPGA would need to have very small setup time requirement or fast clock speed Solution is to have output flip flop inside I/O blocks to reduce routing delay Thus input and output flip flops in I/O blocks speed up operation 50

51 Embedded Devices Newer FPGAsarchitectures incorporate complex devices including Address decoders Multipliers ALUs DSPs Microcontrollers or microprocessors Embedded systems are optimisedand allow integration of entire systems onto single chip Advantages -> save board area and power consumption, save cost and increase speed, devices are already tested and save design time 51

52 Embedded Devices [2] Disadvantage ->design will tend to be tied with particular vendor losing portability as vendors tend to have specific devices embedded in FPGAs -> in case of embedded processors, each vendor usually licenses a specific core from a processor manufacturer Good for FPGA vendor because once they have a design win, design is committed to their FPGA (allow large vendors to maintain market from small vendors) 52

53 Programmable Interconnect Interconnect of FPGA is very different from that of CPLD and is similar to gate array ASIC Each CLB is connected with immediate neighbouring CLBs-> short line connections These connections allow logic that is too complex to fit in 1 CLB to be mapped to multiple CLBs Other routing resources consist of traces that pass by a number of CLBsbefore reaching switch matrices 53

54 Programmable Interconnect [2] Switch matrices allow signals to be routed from 1 switch matrix to another to another, eventually connecting CLBsthat are far from each other Disadvantage is that each trip through chip results in significant delay Often routing delay becomes greater than logic delay 54

55 Programmable Interconnect [3] FPGA programmable interconnect 55

56 Programmable Interconnect [4] Third type of routing resource is long line, which designers can use to connect critical CLBsthat are physically far from each other on the chip without inducing much delay These lines go from one end of the die to the other without connecting to a switch matrix For critical path logic, long lines ensure that there will not be significant delay Long lines can also be used as buses within chip 56

57 Programmable Interconnect [5] Tri-state buffers are used to connect many CLBsto a long line, creating a bus In ASICs tri-state buses should be avoided because tristate buses present a possible danger of contention or floating nodes -> which can present long-term reliability problems unless designed carefully -> multiplexers are used in ASICs to combine many inputs Solution is not applicable for FPGAsas sometimes the outputs are spread over a large selection of the chip requiring the signals to go through may switch matrices to reach final destination 57

58 Programmable Interconnect [6] This introduces very significant delay and CLBs close to long lines drive these long lines with tristate drivers to reduce routing delay CLBsas said earlier has connections to local interconnect to connect to neighbouringclbsbut also uses multiplexers onto longer interconnects to connect it to devices at other parts of the chip Usually, inputs from interconnects go directly into CLB, where logic decides whether to use it or ignore it 58

59 Programmable Interconnect [7] 59

60 Programmable Interconnect [8] CLBsthemselves can be used for routing In cases of congestions on chip, where routing resources are used up and not all signals and CLBsare connected, CLBscan be used for routing In this case, logic and multiplexers are set up so that the signal coming in simply goes out without any logical changes This effectively increases routing resources in a densely packed design but with additional significant delay 60

61 Clock Circuitry Special I/O blocks with special high drive clock buffers clock drivers are distributed around the chip Buffers are connected to clock input pins and drive clock signals onto global clock lines distributed throughout the device in a clock tree configuration Clock lines are designed to have low skew and fast propagation times Synchronous design is a must in FPGAsbecause absolute skew times and delay times for signals cannot be guaranteed using the routing resources of the FPGA Only from these clock buffers can relative delays and skew times be small and predictable 61

62 SRAM Programming SRAM programming involves static RAM bits as the programming elements These bits can be combined in single memory and used as a LUT to implement any type of combinatorial logic Individual SRAM bits can be used to control multiplexers, which select or deselect particular logic within a CLB For routing, these bits can turn on a transistor that connects two traces in a switch matrix or they can select the outputs of a multiplexer that drives an interconnect line 62

63 AntifuseProgramming A regular fuse normally makes a connection until an excessive amount of current goes through it, generating heat and breaking the connection With antifuse, there is a small link between the two conductors, that are separated by an insulator When a large voltage is applied across the link, the link melts As the link melts, the conductor material migrates across the link, creating a conducting path between the two conductors Two types of antifuses -> conductor 1 polysilicon conductor 2 n+ diffused silicon insulator is oxide-nitride-oxide and link is silicon -> both conductors are metal, insulator is amorphous silicon and link is titanium or tungsten silicide 63

64 SRAM vsantifuse SRAM allow re-programmability -> especially as FPGAs become larger and more expensive, during debugging the ability to reprogram is important -> allowing upgrades SRAM allow inclusion of small memories like FIFO stacks in your design, though large memories in FPGAsare not cost effective SRAM-based FPGAscan be used for re-configurable computing allowing algorithms to be compiled to run on FPGAs Disadvantage is their programmability as applications such as military ones require non-volatility and not being susceptible to changes from radiation/glitches -> antifuse better in this case 64

65 SRAM vsantifuse[2] Antifuseis much faster than SRAM Antifusehave real connection between conductors for routing traces as opposed to logic or transistors used in SRAM Antifuseconnections still have high resistance and large RC delays but this is still lower than delay in SRAM but difference in speed is not significant SRAMsare so widely used that their technology is being pushed constantly for improved speed and lower area consumption Antifusetechnology is not wide spread and there is no big drive to improve technology 65

66 SRAM vsantifuse[3] Antifusehave advantage of lower consumption over SRAM based AntifuseFPGAshave intellectual property security advantage -> with SRAM designs can be copied during programming but with antifuse, FPGA is programmed once and design is safe Newer technology is flash-based FPGA -> essentially similar to SRAM but use flash EEPROM bits for programming -> these bits are small and fast 66

67 SRAM vsantifuse[4] 67

68 FPGAsas ASIC Prototyping Designers can use FPGAsin places where an ASIC will eventually be used Designers may use FPGA in a design that needs to get to market quickly at low initial development cost FPGA can be replaced with ASIC when production volume increases to reduce part cost FPGAsnot always intended to be replaced by ASICs 68

69 FPGAsas ASIC Prototyping [2] FPGAstend to be preferred where programmability, up-front cost and time to market are more important than part cost, speed or circuit density FPGAsassist in development of chips in two situations Emulation Prototyping 69

70 FPGAsas ASIC Prototyping [3] Several companies provide standalone hardware boxes for emulating function of the ASIC Hardware emulators can be programmed with design of the chip and can be programmed to drive a target circuit board for the chip Entire target system can be run as if chip were actually available and functional Design can be debugged as if the chip were available and functioning 70

71 FPGAsas ASIC Prototyping [4] Suppose new microprocessor being designed Microprocessor design loaded into hardware emulator and emulator plugged to motherboard on top of which operating system might boot and applications tested Speed might not match of chip but system can be debugged Most hardware emulators use FPGAsas it allows users to easily load, modify designs, examine internal nodes and I/O etc.. 71

72 FPGAsas ASIC Prototyping [5] As FPGAshave become faster and denser and ASICs become larger, prototyping is important Prototyping involves loading chip design into one or more FPGAs FPGA prototypes run faster than hardware emulators because they do not have overhead required for general purpose machine and there are fewer FPGAsonly those necessary to implement the design Prototypes do not possess diagnostic tools of hardware emulator but are cheaper 72

73 FPGA Selection CLBs although all FPGAshave CLBs, there are differences in terms of number of flip flops/look-up table widths -> find the one with CLB architecture that fits the design No. of CLBs this will determine the logic capacity No. and type of I/O pins No. of clock input pins Embedded devices make design job easier if you have the required embedded devices AntifusevsSRAM technology depends on the speed, power consumption, non-volatility, security of the design or reprogrammability 73

74 CPLDsvsFPGAs 74

75 Hardware Description Languages HDL can be used to design at any level of abstraction from high level architectural models to low-level switch models Behavioural Models algorithmic, architectural Structural Models Register Transfer Level (RTL), Gate Level, Switch Level Behaviouralmodels consist of code that represents behaviourof the hardware without know the actual implementation -> algorithmic are used to describe algorithms that act on data, while architectural models specify the blocks that implement the algorithm 75

76 Hardware Description Languages [2] These models of a circuit can be compared to an algorithmic model of the same circuit to discover if a chip s architecture is correctly implementing the algorithm -> can help to find bottlenecks and inefficiencies before any low level design has begun Structural models consist of code that represent specific pieces of hardware -> RTL specifies logic on register level, actual gates are avoided although RTL code may use Boolean functions that can be implemented in gates 76

77 Hardware Description Languages [3] Behavioural Level HDL code RTL HDL Code 77

78 Hardware Description Languages [4] Gate Level modeling consists of code that specifies gates such as NAND and NOR gates Gate Level code is often output of synthesis program that reads RTL level code Gate level code can be optimisedfor placement and routing within CPLD or FPGA Note that all logic must be described in primitive functions that map directly to CLB logic -> coding is obviously longer 78

79 Hardware Description Languages [5] Lowest level is switch level model -> specifying the actual transistor switches that are combined to make gates Design is rarely done at this level Switch level code can be used for physical design of an ASIC HDL providing different levels of modeling within same language is very useful -> you don t need to learn different tools, can simulate at behavioural level and then substitute various behavioural code modules with structural code modules 79

80 Hardware Description Languages [6] With behaviouralmodels, you can test and optimise algorithms RTL code can be used to substitute behavioural blocks, one at a time, to easily test functionality of each block Design is then synthesised-> creating gate and switch level blocks that can then be re-simulated with timing numbers to get actual performance measurements This low-level code can then be use to generate netlist for layout 80

81 Top-Down Design Top-down design is the methodology where high level functions are defined first and lower level implementation details are filled in later In Figure of next slide, top level block represents entire chip, next lower layers also represent chip but divided into major function blocks of the chip Intermediate level blocks divide the functionality into more manageable pieces while bottom level contains gates and macro-functions, which are vendor-supplied high level functions 81

82 Top-Down Design [2] 82

83 Top-Down Design [3] Top-down design lends itself to using HDLs, generally accepted languages for CPLDs and FPGAs Each block in the design corresponds to the code for a self-contained module Top-level blocks corresponds to behaviouralmodel Intermediate levels correspond to RTL models that become the input to the synthesis process Lowest level of hierarchy corresponds to gate level which is the output from the synthesis software and which directly represents logic structures within the chip 83

84 Written Specifications Top-down methodology works hand in hand with a written specification that is an essential start point for the design Specification must include general aspects of the design including major functional blocks Specification is starting point for actual HDL code and specification changes can be quickly turned into HDL design changes and design changes are done quickly and easily 84

85 Allocating Resources/Design Partitioning Top-down design methodology allows more than one engineer, when necessary to design the chip System architect may be responsible for toplevel, while engineers might be responsible for one or several intermediate blocks Thus this methodology may allow designs to become large and benefit from the large capacities of newer FPGAs 85

86 Flexibility/Optimisation Top-down design allows flexibility teams can remove sections of the design and replace them with higher performance or optimised designs without affecting other sections of the design Adding new or improved functionality can also be handled by re-designing sections of the design 86

87 Re-usability When designs were small, it was no big deal to re-start from scratch but today re-using functions will save design time Top-down approach allows re-usability Today cores from third parties can be bought and re-used 87

88 Floorplanning As chips become larger, it may be necessary to help the design tools place the various functions in the device Top-down approach allows you to plan placement of each block in the chip FBsor CLBsthat implement logic in each block can be placed in proximity to each other Relationship between blocks will be more apparent 88

89 Verification Verification has become an important aspect of design process but can be very resource-intensive and often needs to be optimised Top-down design important for improving verification Top-down approach allows modular simulation independently from rest of the design This is important for complex designs where entire design can take weeks to simulate and days to debug 89

90 Synchronous Design One important concept in chip design and one of the hardest to enforce is that of synchronous design Once a chip designer uncovers a problem due to the design not being synchronous and attempts to fix it, it becomes very difficult because asynchronous problems appear intermittently due to power supply variations, temperature or semiconductor process or when the design is translated to a new process The process is compounded by the fact that the exact timing for a programmable device depends on specific routing -> you can get only timing ranges and relative delays 90

91 Synchronous Design [2] Synchronous design ensures that design will work correctly and within speed requirements as long as the timing numbers remain within certain ranges and with delays that remain relatively controlled Synchronous design more reliable than asynchronous design -> today assumed by most tools for complex designs and enforcing it 91

92 Synchronous Design [3] Rules: All data is passed through combinational logic or flip flops that are synchronised by a clock Delay is always controlled by delay elements not combinational logic No signal generated by combinational logic can be fed back to the same combinational logic without first going through a synchronising delay element Clocks cannot be gated -> clocks must go directly to clock inputs of delay elements without going through combinational logic Data signals must go only to combinational logic or data inputs of delay elements 92

93 Synchronous Design [4] Design may have multiple clocks -> in this case, design treats all signals passed between the clock domains as asynchronous Asynchronous design problems: Race Conditions Delay Dependent Logic Hold Time Violations Glitches Gated Clocked 93

94 Asynchronous Design Problems [1] Racing Condition With SIG2 low, flip flop resets to low state On rising edge of SIG2, designer wants OUT to reflect SIG1 Unfortunately due to lack information of the flip flop internal timing or routing delay of signal to clock vsrouting delay of the reset input, we cannot predict which logic arrives first -> clock or reset? If clock rising edge arrives first, output will remain low If reset arrives first, output will go high Changes in temperature, voltage or process will cause chip working correctly to suddenly work incorrectly because of arrival of signal changes Race Condition in Asynchronous Logic 94

95 Asynchronous Design Problems [2] Racing Conditions Solution is to convert to synchronous Conversion is done via state diagram State diagram allows reliable solution State signal is introduced 95

96 Asynchronous Design Problems [3] Racing Conditions Synchronous design uses more logic, adding delay and use expensive die area and more power consumption especially with fast clock especially for CMOS where power is consumed at clock edges Also more routing resources are needed However all of the above is small price to pay when reliability is a necessity 96

97 Asynchronous Design Problems [4] Delay Dependent Logic Pulse width depends on delay of individual gates If semiconductor process used makes the delay shorter, pulse width shortens to the point where logic that it feeds may not recogniseit at all Delay-Dependent Logic 97

98 Asynchronous Design Problems [5] Delay Dependent Logic Synchronous design solves the problem Pulse will depend on the clock period Changes in the semiconductor process will not cause any significant change in pulse width Delay-Independent Logic 98

99 Asynchronous Design Problems [6] Hold Time Violations Hold time violation occurs when data changes around the same time as the clock edge It is uncertain which value will be registered by the clock ->everything depends on internal characteristics of flip flop 99

100 Asynchronous Design Problems [7] Hold Time Violations Solution is to put both flip flops on the same clock and using a flip flip with an input enable 100

101 Asynchronous Design Problems [8] Glitches A glitch can occur due to small delays in a circuit E.g. multiplex switches between selecting two high inputs Multiplexers produces a glitch when switching select input Due to delay of the inverter, there is short time where SEL and SELnare both low -> neither is selected and Z-> low 101

102 Asynchronous Design Problems [9] Glitches If design is synchronised, output is send through flip flop and glitch will not appear at output 102

103 Asynchronous Design Problems [10] Gated Clocking Gated Clocking is a problem in FPGAsas GATE signal can easily be delayed so that clock signal rises before GATE signal can prevent it Data gets clocked into flip flop on a cycle when it is not supposed to Improved is obtained by putting logic on the data input GATE signal is now used to enable and disable the flip flop as GATE input controls the multiplexer 103

104 Asynchronous Design Problems [11] Gated Clocking Asynchronous Clock Gating Synchronous Logic Gating 104

105 Asynchronous Signals and Metastability Metastabilityrefers to a condition that arises when an asynchronous signal is clocked into a synchronous flip flop Although designers would prefer everything to be synchronous, we have signals that depend on users pushing buttons or interrupts from processors Metastability may occur 105

106 Metastability If ASYNC_IN goes high around same time as clock, it creates hold time violation If certain internal transistors of flip flop do not have enough time to charge to correct level, flop flopwill go undefined 106

107 Metastability[2] Metalevel will remain until transistor voltage leaks off or until next clock cycle where a good clean value gets clocked in In some cases, metalevel may oscillate between 0 and 1 107

108 Metastability [3] Metalevel on IN is not real problem but Gates may interprete metalevel differently and give different outputs, which should not occur Differences is probably due to routing as routing can cause signal to change enough to be interpreted differently 108

109 Metastability [4] Problem of metastability is that condition is unpredictable and logic can be sent into an unexpected, unpredictable state from which it never returns 109

110 Metastability [5] Synchroniser flip flop is placed in front of logic and synchronised data is fed into the gates and will be interpreted as either 0 or 1 Solution to Metastability Problem 110

111 Metastability [6] There is still small possibility of metastable signal SYNC_IN However, with synchroniser flip flop, device does not prefer to remain in metastate and there is a good chance that it decays into a stable state by next clock edge So metastate can stabilise before a problem occurs Problem however still occurs at higher frequencies -> some vendors solve the problem by providing special synchroniser flip flops whose output transistors decay very quickly 111

112 Allowable Uses of Asynchronous Logic Asynchronous Reset if vendor s library includes flip flops with asynchronous reset inputs, designers can tie the reset input to a master reset in order to reduce routing congestion and to reduce logic required for a synchronous reset FPGAs and CPLDs have master reset signals built in their architecture Using these signals to reset state machines frees up the interconnect (routing) for other uses especially because routing resources are often the limiting density of an FPGA design 112

113 Allowable Uses of Asynchronous Logic [2] Asynchronous reset are used only to initialise the chip Assert the reset signal at least for 1 clock cycle After reset, every state machine should be in an idle state waiting for an input to change The inputs to the chip should be stable and not change for at least 1 clock cycle after the reset is removed 113

114 Allowable Uses of Asynchronous Logic [3] Some buses are designed to be asynchronous -> in order to interface with these buses, designers need to use asynchronous latches to capture addresses or data Once the data is captured, it must be synchronised to the internal clock Many buses have an address latch enable (ALE) to latch addresses and a data strobe (DSTROBE) to latch data A clock frequency higher than the data rate of the bus will be used to synchronise the data 114

115 Floating Nodes Floating nodes are internal nodes of a circuit that are not driven to logic 0 or logic 1 This should be avoided For circuit shown, if SEL_A and SEL_B are both not asserted, signal OUT will float 115

116 Floating Nodes [2] Downstream logic may interpret OUT as a logic 1 or a logic 0 and may cause metastability In particular, any CMOS circuitry that uses signal OUT as an input will use up power because CMOS dissipates power when input is in the threshold region -> as it is neither ON or OFF Also, the signal can bounce up and down, causing noise in the system and inducing noise in surrounding signals 116

117 Floating Nodes [3] Solutions Use internal pull-up resistors and OUT will be pulled to a good logic level -> active resistors are faster and more power conservative Make sure that something is driving the output at all times 117

118 Bus Contention Bus contention occurs when two outputs drive the same signal at the same time This reduces the reliability of the chip because it has multiple drivers fighting each other to drive a common output If bus contention occurs regularly, even for short times, possibility of damage to the drivers increases To avoid bus contention, designer must ensure that both drivers cannot be asserted simultaneously -> can be accomplished by adding logic 118

119 Bus Contention [2] Bus Contention - Problem Bus Contention - Solution Logic for each buffer has been modified so that the buffer is not turned on until its select line is asserted and all other select lines have been de-asserted 119

120 Bus Contention [3] Due to routing delays, some contentions may still occur but using above logic reduces contention Multiplexers may be used instead of tri-state drivers to avoid contention, though multiplexers are often more difficult to implement 120

121 One-Hot State Encoding For large-grained FPGA architecture, normal method of state-machines is not optimal -> because the normal approach to FSMs tends to couple few flip flops that encode state to a large network of combinational logic requiring a large number of bits -that decodes the state In FPGA, large combinational logic must be built by aggregating several CLBs -> therefore decoding state representation can involve many CLBs 121

122 One-Hot State Encoding [2] This means that routing becomes involved, adding to circuit delay, slowing clock One-hot state encoding reduces the number of inputs to combinational logic, reducing routing and allowing faster clocks For one-hot state encoding, each state is represented by 1 bit (or 1 flip flop) rather than encoding from several state bits -> this reduces combinational logic because only 1 bit needs to be checked to determine the current state 122

123 One-Hot State Encoding [3] Many synthesis tools recognise need for onehot encoding for FPGAs and optimise synthesis accordingly Initially all states need to be reset except idle Usual method 123

124 One-Hot State Encoding [4] One-hot encoding 124