Solutions - Homework 2 (Due date: October 9:30 am) Presentation and clarity are very important!

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1 ECE-8L: Computer Logic Design Fall Solutions - Homework (Due date: October 9: am) Presentation and clarit are ver important! PROBLEM ( PTS) Complete the following table. Use the fewest number of bits for ever case. Show our procedure. Decimal Sign-and-magnitude 's complement 's complement PROBLEM (5 PTS) We need to perform the following operations, where numbers are represented in 's complement: For each case: Determine the minimum number of bits required to represent both summands. You might need to sign-etend one of the summands, since for proper summation, both summands must have the same number of bits. Perform the binar addition in s complement arithmetic. The result must have the same number of bits as the summands. Determine whether there is overflow b: i. Using, (carries). ii. Performing the operation in the decimal sstem and checking whether the result is within the allowed range for bits, where is the minimum number of bits for the summands. If we want to avoid overflow, what is the minimum number of bits required to represent the summands and the result? n = 8 bits c8= c7= +7 = + +5 = +8 = overflow = c 8 c 7 = -> no overflow +8 [- 7, 7 -] -> no overflow n = 9 bits n = 8 bits c8= c7= -5 = + +6 = +9 = overflow = c 8 c 7 = -> no overflow +9 [- 7, 7 -] -> no overflow c9= c8= -9 = + +8 = - = overflow = c 9 c 8 = -> no overflow - [- 8, 8 -] -> no overflow

2 ECE-8L: Computer Logic Design Fall n = 9 bits c9= c8= -55 = + - = overflow = c 9 c 8 = -> overflow! -55-=-85 [- 8, 8 -] -> overflow! To avoid overflow: n = bits (sign-etension): n = bits c= c9= +9 = + +7 = overflow = c c 9 = -> overflow! 9+7=57 [- 9, 9 -] -> overflow! To avoid overflow: n = bits (sign-etension): PROBLEM (5 PTS) c= c9= -55 = + - = -85 = overflow = c c 9 = -> no overflow -85 [- 9, 9 -] -> no overflow n = bits c= c= +99 = + + = overflow = c c = -> overflow! 99+= [-, -] -> overflow! Sign-etension in s complement: Whenever we need to increase the number of bits for representing a number, we append the MSB to the left as man times as needed: Eamples: = = + =5 = = + + = = We can think of the sign-etended number as an -bit number, where > : = Demonstrate that represents the same decimal number as, i.e., demonstrate that sign-etension is correct for an >. Useful formula: =, c= c= +9 = + +7 = +57 = overflow = c c = -> no overflow +57 [-, -] -> no overflow To avoid overflow: n = bits (sign-etension): c= c= +99 = + + = += overflow = c c = -> no overflow + [-, -] -> no overflow We need to demonstrate that: = =, where: =, =, +,, Using the formula for 's complement numbers: + = +

3 ECE-8L: Computer Logic Design Fall + + = + + = + =, = = + = + = = PROBLEM (5 PTS) Implement the following functions using i) decoders and ii) multipleers: = + + = + +,, =,, = Fa Fb Fc Fd w w w s = Fa s = Fb s = Fc s = Fd w w w w w w w w w w w w Fa Fb Fc Fd Using onl -to- MUXs, implement the XOR and XNOR gates. f XOR f XNOR s = f XOR s = f XNOR f XOR f XNOR

4 ECE-8L: Computer Logic Design Fall Using onl a -to- MUX, implement the following functions.,, =,,,,, =,,,, =,,,, =, Fa Fb Fc Fd s = OR Fa s = OR Fb s = Fc s = Fd Fa Fb s = s = PROBLEM 5 ( PTS) A -bit address line in a µprocessor handles up to = of addresses, each address containing one-bte of information. We want to connect four 56KB memor chips to the µprocessor. Sketch the circuit that: i) addresses the memor chips, and ii) enables onl one memor chip (via CE: chip enable) when the address falls in the corresponding range. Eample: if = 5, onl memor chip is enabled (CE=). If =, onl memor chip is enabled. 56KB 56KB 56KB 56KB FFFF 7FFFF 8 BFFFF C FFFFF Memor space address Memor devices 56 KB 56 KB 56 KB CE CE CE ? 56 KB CE 56KB 56KB 56KB 56KB FFFF 7FFFF 8 BFFFF C FFFFF Memor space address Memor devices 56 KB 56 KB 56 KB CE CE address(7..) address(8) address(9) w w CE 56 KB CE

ECE-8L: Computer Logic Design Fall PROBLEM 6 (5 PTS) Complete the timing diagram of the circuit shown below: w w E DECODER k E P P P Unknown P s s P P P P PRIORITY ENCODER f k f The following VHDL

5 ECE-8L: Computer Logic Design Fall PROBLEM 6 (5 PTS) Complete the timing diagram of the circuit shown below: w w E DECODER k E P P P Unknown P s s P P P P PRIORITY ENCODER f k f The following VHDL code corresponds to the shaded circuit. Complete the timing diagram: a b c d tst.vhd DEMUX s s librar ieee; use ieee.std_logic_6.all; entit tst is port (b,c,d: in std_logic; : out std_logic_vector( downto )); end tst; architecture bhv of circ is signal, : std_logic; process (b,c,d) <= c & d; if b = then case d is when => <= ; when others => <= ; end case; else if c = then <= ; end if; end if; end process; end bhv; a b c d Unknown

6 ECE-8L: Computer Logic Design Fall PROBLEM 7 ( PTS) A straightforward implementation of the multiplication operation (for positive or unsigned numbers) is called Arra Multiplier: the partial products are added up at ever column. The figure depicts the hardware implementation for multipling two unsigned number of bits. a a a a cin b b b b FULL ADDER cout s a b a b a b a b a b a b a b a b a b a b a b a b a b a b a b a b p 7 p 6 p 5 p p p p p b() b() b() b() a() a b a b a b a b m m m m s s s s a() c c c a b a b a b a b m m m m p() s s s c c c s a() a b a b a b a b m m m m p() s s s c c c s a() a b a b a b a b m m m m p() s s s c c c s m m m m p() p(7) p(6) p(5) p() One of the drawbacks of this approach is the long dela between the input and the output. In the figure, the bits,,, require the inputs to pass through adders as well as AND gates.

7 ECE-8L: Computer Logic Design Fall An alternative implementation, called Wallace Multiplier, features a shorter dela between the input and the output. The hardware implementation is more complicated though. The figure shows a Wallace multiplier implementation for two unsigned numbers of bits. Note how the addition operation of the rows has been rearranged so that onl rows are added up at ever stage b() b() b() b() a() a b a b a b a b cout FULL ADDER cin a() a() a b a b m m m a b m a b a b a b m m a b a b m m s a() a b m a b m a b m a b m m m m m m m m m m m m m c c c c c s s s s s m m m m c c c c c s s s s s m m m m c c c c c s s s s s P(7) P(6) P(5) P() P() P() P() P() Write the VHDL implementation for the multiplication operation of two unsigned numbers of bits using: i) Arra Multiplier, and ii) Wallace multiplier. Use the Structural Description: create a separate VHDL file for the Full Adder circuit. Simulate both circuits and make sure that the are performing the correct operation. Attach our VHDL code, testbench code, and simulation results.

8 ECE-8L: Computer Logic Design Fall ARRAY MULTIPLIER: VHDL Code: librar IEEE; use IEEE.STD_LOGIC_6.ALL; entit m_mult is generic (N: INTEGER:= ); port (A,B: in std_logic_vector (N- downto ); P: out std_logic_vector (*N- downto )); end m_mult; architecture structure of m_mult is component fulladd port( cin,, : in std_logic; s, cout : out std_logic); end component; tpe m_arra is arra (natural range <>, natural range <>) of std_logic; signal m: m_arra(n downto, N- downto ); signal s: m_arra(n- downto, N- downto ); signal c: m_arra(n- downto, N- downto ); -- Arra of N * (N-) full adders: gi: for i in to N- generate -- along rows gj: for j in to N- generate -- along columns m(i,j) <= A(i) and B(j); fa: if i /= N- and j /= N- generate fij: fulladd port map (cin => c(i,j), => s(i,j+), => m(i+,j), s => s(i+,j), cout => c(i+,j)); fb: if i = generate s(i,j) <= m(i,j); m(n,) <= ''; glj: for j in to N- generate c(,j) <= ''; s(j+,n-) <= m(j+,n-); -- Column (from rows to N-) P(j+) <= s(j+,); flj: fulladd port map (cin => c(n-,j), => s(n-,j+), => m(n,j), s => p(n+j), cout => m(n,j+)); P() <= m(,); P(*N-) <= m(n,n-); end structure; Full Adder VHDL Code: librar ieee; use ieee.std_logic_6.all; entit fulladd is port( cin,, : in std_logic; s, cout : out std_logic); end fulladd; architecture structure of fulladd is s <= or or cin; cout <= ( and ) or ( and cin) or ( and cin); end structure;

9 ECE-8L: Computer Logic Design Fall Testbench Code: LIBRARY ieee; USE ieee.std_logic_6.all; use ieee.std_logic_arith.all; ENTITY tb_m_mult IS generic (N: INTEGER:= ); END tb_m_mult; ARCHITECTURE behavior OF tb_m_mult IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT m_mult PORT( A : IN std_logic_vector(n- downto ); B : IN std_logic_vector(n- downto ); P : OUT std_logic_vector(*n- downto ) ); END COMPONENT; BEGIN END; --Inputs signal A : std_logic_vector(n- downto ) := (others => ''); signal B : std_logic_vector(n- downto ) := (others => ''); --Outputs signal P : std_logic_vector(*n- downto ); -- Instantiate the Unit Under Test (UUT) uut: m_mult PORT MAP ( A => A, B => B, P => P ); -- Stimulus process stim_proc: process -- hold reset state for ns. wait for ns; -- insert stimulus here A <= conv_std_logic_vector(,n); B <= conv_std_logic_vector (5,N); wait for ns; A <= conv_std_logic_vector(,n); B <= conv_std_logic_vector (,N); wait for ns; A <= conv_std_logic_vector(,n); B <= conv_std_logic_vector (,N); wait for ns; A <= conv_std_logic_vector(8,n); B <= conv_std_logic_vector (,N); wait for ns; A <= conv_std_logic_vector(,n); B <= conv_std_logic_vector (8,N); wait for ns; A <= conv_std_logic_vector(**n-,n); B <=conv_std_logic_vector (**N-,N); wait for ns; A <= conv_std_logic_vector(,n); B <= conv_std_logic_vector (,N); wait for ns; wait; end process;

10 ECE-8L: Computer Logic Design Fall WALLACE MULTIPLIER (-BIT): VHDL Code: librar IEEE; use IEEE.STD_LOGIC_6.ALL; entit m_wallace_bit is port (A, B: in std_logic_vector ( downto ); P : out std_logic_vector (7 downto )); end m_wallace_bit; architecture structure of m_wallace_bit is component fulladd port( cin,, : in std_logic; s, cout : out std_logic); end component; tpe m_arra is arra (natural range <>, natural range <>) of std_logic; signal m: m_arra( downto, downto ); signal c: m_arra( downto, downto ); signal s: m_arra( downto, downto ); gi: for i in to generate -- along rows gj: for j in to generate -- along columns m(i,j) <= A(i) and B(j); c(,) <= ''; c(,) <= ''; c(,) <= ''; s(,) <= c(,); s(,) <= c(,); s(,) <= c(,); -- First Laer f: fulladd port map (cin => c(,), => m(,), => m(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => m(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => m(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => '', s => s(,), cout => c(,)); -- Second Laer f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); -- Third Laer f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); f: fulladd port map (cin => c(,), => m(,), => s(,), s => s(,), cout => c(,)); end structure; P() <= m(,); P() <= s(,); P() <= s(,); P() <= s(,); P() <= s(,); P(5) <= s(,); P(6) <= s(,); P(7) <= s(,);

11 ECE-8L: Computer Logic Design Fall Testbench Code: LIBRARY ieee; USE ieee.std_logic_6.all; use ieee.std_logic_arith.all; ENTITY tb_m_wallace_bit IS END tb_m_wallace_bit; ARCHITECTURE behavior OF tb_m_wallace_bit IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT m_wallace_bit PORT( A : IN std_logic_vector( downto ); B : IN std_logic_vector( downto ); P : OUT std_logic_vector(7 downto ) ); END COMPONENT; BEGIN END; --Inputs signal A : std_logic_vector( downto ) := (others => ''); signal B : std_logic_vector( downto ) := (others => ''); --Outputs signal P : std_logic_vector(7 downto ); -- Instantiate the Unit Under Test (UUT) uut: m_wallace_bit PORT MAP ( A => A, B => B, P => P ); -- Stimulus process stim_proc: process -- hold reset state for ns. wait for ns; -- insert stimulus here li: for i in to 5 loop A <= conv_std_logic_vector(i,); lj: for j in to 5 loop B <= conv_std_logic_vector (j,); wait for ns; end loop; end loop; A <= ""; B <= ""; wait for ns; wait; end process;

Solutions - Homework 2 (Due date: February 5 5:30 pm) Presentation and clarity are very important! Show your procedure!

Solutions - Homework 2 (Due date: February 5 5:30 pm) Presentation and clarity are very important! Show your procedure! Solutions - Homework (Due date: Februar 5 th @ 5: pm) Presentation and clarit are ver important! Show our procedure! PROBLEM ( PTS) In these problems, ou MUST show our conversion procedure. a) Convert